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Post AvchHVoKxItG7cSs08 by [email protected] |
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Post #AvchHVoKxItG7cSs08 by [email protected] |
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Embarrassing concurrency question (from debate at work): do MFENCE barriers nee… |
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Post #AvchHVuMati8QJHgOW by [email protected] |
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@tobinbaker MFENCE is x86, so TSO. (let's also disregard the interaction of… |
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Post #AvchHW16Br6AlCR3tQ by [email protected] |
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@pkhuong Yeah, I can see how it makes sense on a single core. The specific scen… |
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Post #AvchHW6lqldT2n5ajY by [email protected] |
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@tobinbaker In practice, the potentially missing MFENCE is more than ensured by… |
