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Post AtnNOX1at5Fzy5GP6O by [email protected] |
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More posts by [email protected] |
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Post #AtnMuEDgEvSKxRT1ZQ by [email protected] |
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I got so bored assembling boards that I came up with a actually useful reason t… |
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Post #AtnMuEK3rCYnHES7W4 by [email protected] |
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@aleksorsist Programmable hardware trigger state machine? This has been on my w… |
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Post #AtnMuEQRTTfFb1RDSi by [email protected] |
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@azonenberg @aleksorsist Why did even I think "is this some kind of a Trig… |
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Post #AtnMuEXX37Krx0ksVs by [email protected] |
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@urja @azonenberg Yup! It would have edge modules, slope and delay timers. Basi… |
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Post #AtnMuEdufORKGnjySW by [email protected] |
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@aleksorsist @urja My vision a while back was a series of series of edge detect… |
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Post #AtnMuEjaKIycYOOVIe by [email protected] |
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@azonenberg @urja I wouldn't want to hard code any protocols. I'm tryin… |
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Post #AtnMuEpbxtnUr5DJh2 by [email protected] |
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@aleksorsist @urja Well that's the idea. you build the blocks then the micr… |
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Post #AtnMuEvzaAtxAsCPdg by [email protected] |
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@aleksorsist @urja but my vision is less of a CPU and more of a coarse grained … |
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Post #AtnMuF2NCS0PUfBVaK by [email protected] |
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@azonenberg @urja that's actually more what I'm thinking. Basically the… |
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Post #AtnMuF7KtzyXk3VTJw by [email protected] |
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@urja @azonenberg then we can have a fairly real-time physical trigger output a… |
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Post #AtnMuF96nPORpYKt5E by [email protected] |
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@aleksorsist @urja Yeah. So what you want IMO is a series of always-enabled dat… |
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Post #AtnMuFF8R0DK8F9hTc by [email protected] |
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@azonenberg @urja ah, you want to clock off the signals, gotya. I was thinking … |
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Post #AtnMuFLA4b2CQvyVs0 by [email protected] |
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@aleksorsist @urja When I say "clock" I mean in the digital domain.Yo… |
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Post #AtnMuFSxbbGyp7ck1g by [email protected] |
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@aleksorsist @urja You can add support for fixed time delays as well as edge de… |
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Post #AtnMuFZhCYf1A0m7Wa by [email protected] |
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@aleksorsist @urja So maybe instead you havestate 3) wait 1ms, if A still low t… |
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Post #AtnMuFg4oplTTnlDTE by [email protected] |
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@aleksorsist @urja Running completely based on sample counting won't work f… |
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Post #AtnMuFmSR6rvnakJPs by [email protected] |
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@aleksorsist @urja The other challenge will be how to handle higher speed seria… |
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Post #AtnMuFsU4hgo6HZ7oG by [email protected] |
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@azonenberg @urja it will never clock at 1 GHz because we'd be doing this o… |
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Post #AtnMuFy9jcE6NsDeeO by [email protected] |
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@aleksorsist @urja No, you're missing the point.Because you're running … |
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Post #AtnMuG4BND2ygZ2T2m by [email protected] |
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@azonenberg @aleksorsist @urja you would unroll the state machine N times and p… |
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Post #AtnMuIe3mmvygPq9FA by [email protected] |
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@aleksorsist @urja So the building blocks would be things like "convert an… |
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Post #AtnMuImZH9jv6nowVM by [email protected] |
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@aleksorsist @urja (this is a SPI trigger for SCK=CH2, SDI=CH3, CS#=CH1, matchi… |
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Post #AtnMyuTf4IYJAzAsk4 by [email protected] |
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@whitequark @aleksorsist @urja Exactly what I was getting at. It's solvable… |
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Post #AtnNOWu9KlInazmSUy by [email protected] |
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@azonenberg @whitequark @urja I joked about it being a quasi CPU and it is quic… |
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Post #AtnNOX1at5Fzy5GP6O by [email protected] |
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@azonenberg @whitequark @urja guess we doin HDL now. Once I finish these damn b… |
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Post #AtnNOX6uZJViEZkeOG by [email protected] |
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@aleksorsist @whitequark @urja Lol.A VLIW processor may actually end up being t… |
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Post #AtnNOXCaEE30WAPBEO by [email protected] |
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@aleksorsist @whitequark @urja What I don't know is what the cleanest progr… |
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Post #AtnNOXIbrorsorDzcm by [email protected] |
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@azonenberg @aleksorsist @urja RTL and partial reconfig :p |
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Post #AtnNWHlbV3GgxmTvSS by [email protected] |
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@whitequark @aleksorsist @urja Doable but you're limited by the 35T's f… |
