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Post Arj1v51IlBdIA8zNom by [email protected] |
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More posts by [email protected] |
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Post #Arj1v4qJQ2qHc3qbgm by [email protected] |
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You could totally drive SDRAM with the DQ and A pins shorted together if you we… |
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Post #Arj1v51IlBdIA8zNom by [email protected] |
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@wren6991 That's a fascinating idea! I get the gist of your idea and if I … |
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Post #Arj1v596IBs4YKdbyS by [email protected] |
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@tommythorn Yes, the drawback for writes is you need an additional short burst … |
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Post #Arj1v5HFnsOQxcS7gO by [email protected] |
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@tommythorn I keep looking at low-pin-count DRAM offerings like HyperRAM, OPI/Q… |
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Post #Arj1v5OhMCLdKhw4Ho by [email protected] |
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@wren6991 @tommythorn meanwhile I'm continuing to dream of a low pin count … |
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Post #Arj1v5W8uWIphnQ0tE by [email protected] |
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@azonenberg Looking forward to seeing this overloaded onto MOSI/MISO/WPn/HOLDn … |
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Post #Arj1v5g4JcF6Ca3wMS by [email protected] |
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@wren6991 @azonenberg terrifying |
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Post #Arj2diVRJSqLMtN1Rw by [email protected] |
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@wren6991 I mean I've seen RGMII and SGMII on the same IO buffers. It's… |
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Post #Arj2digQebdLuyVnZw by [email protected] |
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@wren6991 I was thinking of this more as a hyperram replacement though.Hyperbus… |
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Post #Arj2diqi2NrCQrK0bQ by [email protected] |
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@azonenberg @wren6991 how much power though |
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Post #Arj2xgvosPXiHDEZRg by [email protected] |
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@whitequark @wren6991 Probably more than hyperram.But 32 Gbps is closer to what… |
