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Post AjEznHluImxHSqkxSy by [email protected] |
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Post #Aj80wwG5skAfUCK6gS by [email protected] |
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I have really exciting news: I came up with a very broad methodology for buildi… |
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Post #Aj81TssfSgLaZA4kJE by [email protected] |
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teaserthis diagram only has four inserted delay cycles, and i actually know how… |
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Post #Aj81godqX91fBRJEYK by [email protected] |
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once complete (no ETAs) this will very likely land in amaranth-stdio + amaranth… |
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Post #Aj823XmPOM4tY19T16 by [email protected] |
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I'm implementing this in a way which adapts to any fixed I/O latency, that … |
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Post #Aj8dwfTUBHFJdyRuFs by [email protected] |
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i redesigned the QSPI module to require no wait states at allcheck out this dia… |
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Post #Aj8eMJRKjCH4pjfdeC by [email protected] |
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check out the source: ~200 lines for the QSPI core, ~600 lines for everything i… |
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Post #Aj8em36y3kIbikPuU4 by [email protected] |
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@whitequark QSPI device mode is where it gets hard. You have to either oversamp… |
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Post #Aj8em3CzhL7U1REisS by [email protected] |
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@azonenberg this is true, but a QSPI controller is still difficult to implement… |
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Post #Aj8htDbtisyCAiziNc by [email protected] |
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@iacore what is software-defined I/O? |
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Post #Aj8vr32DTDKi9TADh2 by [email protected] |
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the QSPI gateware works extremely well :D |
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Post #Aj91Rk3VUrJnm45GSW by [email protected] |
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i have benchmarked it against the fastest configuration of the Glasgow SPI core… |
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Post #Aj9326PJyE5nTbBn4i by [email protected] |
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work-in-progress PR https://github.com/GlasgowEmbedded/glasgow/pull/586 |
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Post #AjEznHluImxHSqkxSy by [email protected] |
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@whitequark Hi, what software are you using to make these graphs? |
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Post #AjEznHsHv43jmdk3Pc by [email protected] |
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@alj gtkwave |
