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Post Ad1g7H5kGOLmQB2ixc by [email protected] |
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More posts by [email protected] |
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Post #Ad0G8NQBQJngNLVXKi by [email protected] |
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hey RTL developers: would you be interested in a simulator integrating with a V… |
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Post #Ad0GGPjugjU9skZKE4 by [email protected] |
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what if you can also set conditional breakpoints and jump between time points w… |
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Post #Ad0J2Uj5eP9z9lEofg by [email protected] |
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@whitequark I don't use VSCode, but if it used the generic Debug Adapter Pr… |
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Post #Ad0J2UnhNGqXO3OUr2 by [email protected] |
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@lambda it does not use the DAP because the DAP is not compatible with hardware… |
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Post #Ad0V9SaRCdNNzvHLKi by [email protected] |
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@whitequark this sounds incredible |
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Post #Ad0dGiz5R0m8Vwmbg0 by [email protected] |
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@the_art_of_giving_up want to beta it? |
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Post #Ad0eGemRAIJlQiOj5M by [email protected] |
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@whitequark I would like to give it a try though I don't work with HDL on t… |
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Post #Ad0fNNaNalU65EWlMm by [email protected] |
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@whitequark this reminds me of the Light Table editor from Chris Granger and Ro… |
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Post #Ad0sJ1Ew1wOD1akRJA by [email protected] |
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@whitequark this absolutely does sound like it could be insanely useful. I have… |
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Post #Ad0sJ1JBm7nBEmjpwG by [email protected] |
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@holonium want to beta it? (it supports Verilog and VHDL and Amaranth and even … |
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Post #Ad0sRX4ZYnpS4LxcSe by [email protected] |
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@whitequark it would certainly not be an intended application, but from your de… |
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Post #Ad0sRX8TKIwqGRmjXU by [email protected] |
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@lambda you could probably shoehorn it into DAP but I'm more interested in … |
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Post #Ad0sbK72bJTKlmmf56 by [email protected] |
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@the_art_of_giving_up I can provide you (at some future point; not quite ready … |
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Post #Ad0spBGeHcYnOKsxoe by [email protected] |
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@whitequark yeah, I would be up for beta testing on it.Will be mostly working i… |
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Post #Ad0spBLG0UFLcd2e00 by [email protected] |
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@holonium do your designs synthesize with Yosys? (or at least, does the fronten… |
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Post #Ad0swV8WoDp72cZtBo by [email protected] |
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@holonium also, the frontend (Verilog or VHDL) needs a small patch to enable al… |
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Post #Ad0xDewE1ILIBDGCSO by [email protected] |
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@whitequark That is fine. I am not afraid of going through the process to patch… |
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Post #Ad0xDf0pkA1qPVPsdk by [email protected] |
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@whitequark would also like to put in that given that it is beta, I totally get… |
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Post #Ad0xDf4NWyreaV4iAK by [email protected] |
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@holonium cool! I'll ping you once it's more ready then! |
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Post #Ad0xFHdxbEkEVoUXVg by [email protected] |
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@whitequark Sounds good. Is this based on CXXRTL? Amaranth or .*Verilog? |
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Post #Ad108BDZOKJ6Q1S5Ka by [email protected] |
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@the_art_of_giving_up CXXRTL, yes. the VSCode extension supports Amaranth, Veri… |
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Post #Ad16yQ4U0koxGkUjRI by [email protected] |
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@whitequark does this imply you're currently using vs code for rtl design? |
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Post #Ad16yQ8jkwDvTwU84O by [email protected] |
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@forensicgarlic yes |
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Post #Ad1g7H5kGOLmQB2ixc by [email protected] |
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@whitequark It's one of the killer features of Verdi. I tried getting it to… |
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Post #Ad2Ax37qQoTumzd4K0 by [email protected] |
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@whitequark for VHDL, yes! |
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Post #Ad2FqNV8mBJPj9ADYm by [email protected] |
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@whitequark Most definitely! |
