head    1.1;
access;
symbols;
locks; strict;
comment @# @;


1.1
date    2007.06.29.01.38.55;    author aki;     state Exp;
branches;
next    ;


desc
@@


1.1
log
@Initial revision
@
text
@Version 4
SHEET 1 1148 680
WIRE 352 160 48 160
WIRE 400 160 352 160
WIRE 192 208 48 208
WIRE 240 208 192 208
WIRE -112 240 -160 240
WIRE 0 240 -112 240
WIRE 240 240 240 208
WIRE 400 240 400 160
WIRE -112 352 -112 320
WIRE -80 352 -112 352
WIRE 48 352 48 256
WIRE 80 352 48 352
WIRE 240 352 240 320
WIRE 272 352 240 352
WIRE 400 352 400 320
WIRE 432 352 400 352
WIRE -112 368 -112 352
WIRE -80 368 -80 352
WIRE 80 368 80 352
WIRE 272 368 272 352
WIRE 432 368 432 352
WIRE -160 384 -160 240
WIRE 240 400 240 352
WIRE 400 400 400 352
WIRE 192 416 192 208
WIRE 352 416 352 160
WIRE 48 448 48 352
WIRE -112 464 -112 448
WIRE 0 464 -112 464
WIRE 240 496 240 480
WIRE 240 496 48 496
WIRE 400 544 400 480
WIRE 400 544 48 544
FLAG 80 368 0
FLAG 272 368 0
FLAG 432 368 0
FLAG -80 368 0
FLAG -160 432 0
FLAG 192 464 0
FLAG 352 464 0
SYMBOL nmos4 0 160 R0
SYMATTR InstName Mn
SYMATTR Value Nch
SYMATTR Value2 l={length} w={10*length}
SYMBOL pmos4 0 544 M180
SYMATTR InstName Mp
SYMATTR Value Pch
SYMATTR Value2 l={length} w={10*length}
SYMBOL voltage -112 224 R0
SYMATTR InstName Vgs
SYMATTR Value 0.65
SYMBOL voltage 240 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vbs
SYMATTR Value 0
SYMBOL voltage 400 224 R0
SYMATTR InstName Vds
SYMATTR Value 0.2
SYMBOL e -112 352 R0
SYMATTR InstName Vsg
SYMATTR Value 1
SYMBOL e 240 384 R0
SYMATTR InstName Vsb
SYMATTR Value 1
SYMBOL e 400 384 R0
SYMATTR InstName Vsd
SYMATTR Value 1
TEXT -440 144 Left 0 ;.include C5_models.txt
TEXT 304 -216 Left 0 ;.lib cmosedu_models.txt
TEXT 288 -160 Left 0 ;.step param length 50n 250n 50n
TEXT 720 -160 Left 0 ;.param length 50n
TEXT -424 -184 Left 0 ;.lib '/tool/hspice/tr_model/tsmc018_3_model/log018.l' TT
TEXT -128 -64 Left 0 !.step param length 0.20u 2u 0.1u
TEXT -400 -264 Left 0 ;.lib  mosis_tsmc018_models.txt
TEXT 648 -216 Left 0 ;.step param length 1u 10u 1u
TEXT -440 -104 Left 0 ;.lib '/tool/hspice/tr_model/tsmc018_3_model/vt+.08V/tsmc018_3.lib' TT
TEXT -440 -128 Left 0 ;.lib '/tool/hspice/tr_model/tsmc018_3_model/cl018g5v.l' TT
TEXT -432 -160 Left 0 ;.lib '/tool/hspice/tr_model/tsmc018_3_model/rf018.l' TT
TEXT -528 -272 Left 0 ;CMOSN
TEXT 192 -224 Left 0 ;N_1u,50n
TEXT -488 -24 Left 0 !.dc Vgs 0 1.8 0.01 Vbs 0 -1.2 -0.1
TEXT -440 -64 Left 0 ;.param length 0.2u
TEXT -120 -16 Left 0 ;;dc Vsb_n 0 1 0.1
TEXT 544 -24 Left 0 ;.STEP param Mn list 2\n.model 1 ako:CMOSN\n.model 2 ako:NCH\n.model 3 ako:N_1u\n.model 4 ako:N_50n
TEXT 544 144 Left 0 ;.STEP param Mp list 12\n.model 11 ako:CMOSP\n.model 12 ako:PCH\n.model 13 ako:P_1u\n.model 14 ako:N_50n
TEXT -528 -184 Left 0 ;NCH
TEXT -480 8 Left 0 !;op
TEXT -464 64 Left 0 ;.lib '/tool/hspice/tr_model/k018_18/bsim3_t10/L018um_tr_typ.mod' L018process_n
TEXT -560 64 Left 0 ;L018nch
TEXT -432 -208 Left 0 !.lib '/tool/hspice/tr_model/tsmc018_2_model/tsmc018_2.lib' TT
@

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