/*
* Part comes in -170, -135 and -110MHz speed-grades.
* In 8-bit mode the max. PCLK is 135MHz for the -170 part
* and the speed-grade for the others. In 2x8-bit mode, the max.
* PCLK is the speed-grade, using the 2x doubler.
* Work out the part speed-grade from name. Name can have,
* e.g. '-135' on the end for 135MHz part.
*/
grade = 110000000;
if(p = strrchr(ctlr->name, '-'))
grade = strtoul(p+1, 0, 0) * 1000000;
/*
* If we don't already have a desired pclk,
* take it from the mode.
* Check it's within range.
*/
if(vga->f[0] == 0)
vga->f[0] = vga->mode->frequency;
/*
* Determine whether to use 2x8-bit mode or not.
* If yes and the clock has already been initialised,
* initialise it again. There is no real frequency
* restriction, it's really just a lower limit on what's
* available in some clock generator chips.
*/
if(vga->ctlr && (vga->ctlr->flag & Hpclk2x8) && vga->mode->z == 8 && vga->f[0] >= 60000000){
vga->f[0] /= 2;
resyncinit(vga, ctlr, Upclk2x8, 0);
}
if(vga->f[0] > pclk)
error("%s: invalid pclk - %ld\n", ctlr->name, vga->f[0]);
/*
* Set the mode in the RAMDAC, setting 6/8-bit colour
* as appropriate and waking the chip back up.
*/
if(vga->mode->z == 8 && 0)
mode |= 0x02;
x = attdaci(Cr1) & 0x80;
attdaco(Cr1, x);
attdaco(Cr0, mode);