/*
* Set the m/n values for the desired frequency and
* set pixel control to use compatibility mode with
* internal frequency select using the specified set
* of m/n registers.
*/
rgb524mnxo(vga, M0+vga->i[0]*2, vga->d[0]<<6|vga->m[0]);
rgb524mnxo(vga, N0+vga->i[0]*2, vga->n[0]);
rgb524mnxo(vga, PLLControl2, vga->i[0]);
rgb524mnxo(vga, PLLControl1, 0x03);
/*
* Enable pixel programming in MiscClock;
* nothing to do in MiscControl1;
* set internal PLL clock and !vga in MiscControl2;
*/
x = rgb524mnxi(vga, MiscClock) & ~0x01;
x |= 0x01;
rgb524mnxo(vga, MiscClock, x);
x = rgb524mnxi(vga, MiscControl2) & ~0x41;
x |= 0x41;
rgb524mnxo(vga, MiscControl2, x);
/*
* Syncs.
*/
x = 0;
if(vga->mode->hsync == '+')
x |= 0x10;
if(vga->mode->vsync == '+')
x |= 0x20;
rgb524mnxo(vga, SyncControl, x);
if(val = dbattr(vga->mode->attr, "hsyncdelay"))
hsyncdelay = strtol(val, 0, 0);
else switch(vga->mode->z){
default:
case 8:
hsyncdelay = 1;
break;
case 15:
case 16:
hsyncdelay = 5;
break;
case 32:
hsyncdelay = 7;
break;
}
rgb524mnxo(vga, HSyncControl, hsyncdelay);
/*
* Set the palette for the desired format.
* ****NEEDS WORK FOR OTHER THAN 8-BITS****
*/
rgb524mnxo(vga, PaletteControl, 0x00);
switch(vga->mode->z){
case 8:
rgb524mnxo(vga, PixelFormat, 0x03);
rgb524mnxo(vga, Pixel8Control, 0x00);
break;
case 15:
rgb524mnxo(vga, PixelFormat, 0x04);
rgb524mnxo(vga, Pixel16Control, 0xC4);
case 16:
rgb524mnxo(vga, PixelFormat, 0x04);
rgb524mnxo(vga, Pixel16Control, 0xC6);
break;
case 32:
rgb524mnxo(vga, PixelFormat, 0x06);
rgb524mnxo(vga, Pixel32Control, 0x03);
break;
}
}
static void
dumpclock(Vga*, Ctlr* ctlr, ulong fref, ulong m, ulong n, char* name)
{
ulong df, f;
df = (m>>6) & 0x03;
m &= 0x3F;
n &= 0x1F;
if(m == 0 || n == 0)
return;
f = (fref*(m+65))/n;
switch(df){
case 0:
f /= 8;
break;
case 1:
f /= 4;
break;
case 2:
f /= 2;
break;
case 3:
break;
}
printitem(ctlr->name, name);
Bprint(&stdout, "%12lud\n", f);
}