/*
* parameters for sysproc.c
*/
#define AOUT_MAGIC (E_MAGIC)
struct Lock
{
ulong key;
u32int sr;
uintptr pc;
Proc* p;
Mach* m;
int isilock;
};
struct Label
{
uintptr sp;
uintptr pc;
};
/*
* emulated or vfp3 floating point
*/
enum {
Maxfpregs = 32, /* could be 16 or 32, see Mach.fpnregs */
Nfpctlregs = 16,
};
struct FPsave
{
ulong status;
ulong control;
/*
* vfp3 with ieee fp regs; uvlong is sufficient for hardware but
* each must be able to hold an Internal from fpi.h for sw emulation.
*/
ulong regs[Maxfpregs][3];
int fpstate;
uintptr pc; /* of failed fp instr. */
};
struct PFPU
{
int fpstate;
FPsave fpsave[1];
};
enum
{
FPinit,
FPactive,
FPinactive,
FPemu,
/* bit or'd with the state */
FPillegal= 0x100,
};
struct Conf
{
ulong nmach; /* processors */
ulong nproc; /* processes */
Confmem mem[1]; /* physical memory */
ulong npage; /* total physical pages of memory */
usize upages; /* user page pool */
ulong copymode; /* 0 is copy on write, 1 is copy on reference */
ulong ialloc; /* max interrupt time allocation in bytes */
ulong pipeqsize; /* size in bytes of pipe queues */
ulong nimage; /* number of page cache image headers */
ulong nswap; /* number of swap pages */
int nswppo; /* max # of pageouts per segment pass */
ulong hz; /* processor cycle freq */
ulong mhz;
int monitor; /* flag */
};
/*
* MMU stuff in Mach.
*/
struct MMMU
{
PTE* mmul1; /* l1 for this processor */
int mmul1lo;
int mmul1hi;
int mmupid;
};
struct Mach
{
/* offsets known to asm */
int machno; /* physical id of processor */
uintptr splpc; /* pc of last caller to splhi */
Proc* proc; /* current process */
MMMU;
/* end of offsets known to asm */
int flushmmu; /* flush current proc mmu state */
ulong ticks; /* of the clock since boot time */
Label sched; /* scheduler wakeup */
Lock alarmlock; /* access to alarm list */
void* alarm; /* alarms bound to this clock */
int inclockintr;
Proc* readied; /* for runproc */
ulong schedticks; /* next forced context switch */
int cputype;
ulong delayloop;
/* stats */
int tlbfault;
int tlbpurge;
int pfault;
int cs;
int syscall;
int load;
int intr;
uvlong fastclock; /* last sampled value */
uvlong inidle; /* time spent in idlehands() */
ulong spuriousintr;
int lastintr;
int ilockdepth;
Perf perf; /* performance counters */
int probing; /* probeaddr() state */
int trapped;
Lock probelock;
int inidlehands;
int cpumhz;
uvlong cpuhz; /* speed of cpu */
uvlong cyclefreq; /* Frequency of user readable cycle counter */
/* vfp3 fpu */
int havefp;
int havefpvalid;
int fpon;
int fpconfiged;
int fpnregs;
ulong fpscr; /* sw copy */
int fppid; /* pid of last fault */
uintptr fppc; /* addr of last fault */
int fpcnt; /* how many consecutive at that addr */
/* save areas for exceptions, hold R0-R4 */
u32int sfiq[5];
u32int sirq[5];
u32int sund[5];
u32int sabt[5];
u32int smon[5]; /* probably not needed */
u32int ssys[5];
struct
{
Lock;
char machs[MAXMACH]; /* active CPUs */
int wfi; /* bitmap of CPUs in WFI state */
int stopped; /* bitmap of CPUs stopped */
int exiting; /* shutdown */
}active;
/* an object guaranteed to be in its own cache line */
typedef uchar Cacheline[CACHELINESZ];
struct Isolated {
Cacheline c0;
ulong word;
Cacheline c1;
};
extern Memcache cachel[]; /* arm arch v7 supports 1-7 */
extern ulong intrcount[MAXMACH];
extern int irqtooearly;
extern uintptr kseg0;
extern Isolated l1ptstable;
extern uchar *l2pages;
extern Mach* machaddr[MAXMACH];
extern ulong memsize;
extern int navailcpus;
extern int normalprint;
/*
* characteristics of cache level, kept at low, fixed address (CACHECONF).
* all offsets are known to cache.v7.s.
*/
struct Lowmemcache {
uint l1waysh; /* shifts for set/way register */
uint l1setsh;
uint l2waysh;
uint l2setsh;
};
/*
* cache capabilities. write-back vs write-through is controlled
* by the Buffered bit in PTEs.
*
* see cache.v7.s and Memcache in dat.h
*/
enum {
Cawt = 1 << 31,
Cawb = 1 << 30,
Cara = 1 << 29,
Cawa = 1 << 28,
};