Index of Abstracts from DECWRL tech report service (updated Apr 30 16:53 Abstracts/Index)
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***TECHNICAL REPORTS***
Key Author(s) Title
=======================================================================
Prospectus.87 WRL Prospectus 87-88
86/1 Nielsen Titan System Manual
86/3 Wall Global Register Allocation at Link Time
86/4 Hamburgen Optimal Finned Heat Sinks
87/1 Wall/Powell The Mahler Experience: Using an Intermediate Language
as the Machine Description
87/2 Mogul et al. The Packet Filter: An Efficient Mechanism for
User-level Network Code
87/3 Kent/Mogul Fragmentation Considered Harmful
87/4 Kent Cache Coherence in Distributed Systems
87/5 Wall Register Windows vs. Register Allocation
87/6 Asente Editing Graphical Objects using Procedural
Representations
87/7 Reid The USENET Cookbook: an Experiment in Electronic
Publication
87/8 Jouppi et al. MultiTitan: Four Architecture Papers
88/1 Dion Fast Printed Circuit Board Routing
88/2 Bartlett Compacting Garbage Collection with Ambiguous Roots
88/3 Mogul The Experimental Literature of The Internet:
An Annotated Bibliography
88/4 Boggs et al. Measured Capacity of an Ethernet: Myth and Reality
88/5 Estrin, Mogul, Visa Protocols for Controlling Inter-Organizational
Tsudik, Anand Datagram Flow: Extended Description
89/1 Bartlett SCHEME->C A Portable Scheme-to-C Compiler
89/2 Turrini Optimal Group Distribution in Carry-Skip Adders
89/3 Hamburgen Precise Robotic Paste Dot Dispensing
89/4 Mogul Simple and Flexible Datagram Access Controls for
Unix-based Gateways
89/5 Srinivasan, Spritely NFS: Implementation and Performance of
Mogul Cache-Consistency Protocols
89/7 Jouppi, Wall Available Instruction-Level Parallelism for
Superscalar and Superpipelined Machines
89/8 Jouppi, et al. A Unified Vector/Scalar Floating-Point Architecture
89/9 Jouppi Architectural and Organizational Tradeoffs in the
Design of the MultiTitan CPU
89/10 Jouppi Integration and Packaging Plateaus of Processor
Performance
89/11 Jouppi, Tang A 20-MIPS Sustained 32-bit CMOS Microprocessor with
High Ratio of Sustained to Peak Performance
89/13 Jouppi The Distribution of Instruction-Level and Machine
Parallelism and Its Effect on Performance
89/14 Borg, et al. Long Address Traces from RISC Machines: Generation
and Analysis
89/17 Wall Link-Time Code Modification
90/1 Tang,Yang Noise Issues in the ECL Circuit Family
90/2 Larrabee Efficient Generation of Test Patterns Using Boolean
Satisfiability
90/3 Larrabee Two Papers on Test Pattern Generation
90/4 Nelson Virtual Memory vs. The File System
90/5 Mogul Efficient Use of Workstations for Passive
Monitoring of Local Area Networks
90/6 Fitch A One-Dimensional Thermal Model for the
VAX 9000 Multi Chip Units
90/7 Mayo, et al. 1990 DECWRL/Livermore Magic Release
90/9 McGillis et al. Pool Boiling Enhancement Techniques for Water at Low
Pressure
91/1 McCormack Writing Fast X Servers for Dumb Color Frame Buffers
***TECHNICAL NOTES***
Key Author(s) Title
=======================================================================
TN-4 Reid, Kent TCP/IP PrintServer: Print Server Protocol
TN-7 Kent TCP/IP PrintServer: Server Architecture and
Implementation
TN-9 McCormack Smart Code, Stupid Memory A Fast X Server for
a Dumb Color Frame Memory
TN-11 Ousterhout Why Aren't Operating Systems Getting Faster
As Fast As Hardware?
TN-12 Bartlett Mostly-Copying Garbage Collection Picks Up
Generations and C++
TN-15 Wall Limits of Instruction-Level Parallelsim
TN-16 Mogul, Borg The Effect of Context Switches on Cache Performance
TN-17 Goldberg MTOOL: A Method For Detecting Memory Bottlenecks
TN-18 Wall Predicting Program Behavior Using Real or Estimated
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