Last update: 02/09/86
HD64180.BUG
V 1.0
I believe the following section was written by:
WA7GXD
(See Gateway Vol 2, No 11. Jan. 24, 1986)
I� yo�� ar� plannin� o� usin� � Hitach� HD6418� (gues� yo� �
hav� t� us� Hitach� i� yo� pla� o� usin� � 64180...� pleas� not� �
tha� i� i� no� directl� compatibl� wit� Z8� (tm� styl� periphera� �
IC� whe� usin� th� Mod� � interrup� scheme�� � know� � foun� ou� �
th� hard� expensiv� way.
ɠ hav� designe� � packe� switc� fo� Amateu� packe� radi� �
usag� tha� i� base� o� th� 64180� � PIO� � pai� o� SIO/2� an� th� �
NCR538� SCS� chip�� I� als� ha� 1� bytewid� socket� an� screw� o� �
th� sid� o� � 5.25� flopp� dis� controller�� I� i� o� � 4-laye� �
boar� an� w� ha� prototyp� board� mad� (compile� i� th� neares� �
softwar� equivalent...)�� Durin� fina� hardwar� debu� testing� �
mod� � interrupt� wer� switche� on.
Th� periphera� woul� servic� exactl� � interrupt�� the� loc� �
it� IE� lin� lo� an� sta� tha� wa� unti� powe� off/powe� o� rese� �
wa� accomplished!
I� turn� ou� tha� th� timin� o� th� LIR� outpu� fro� th� �
6418�� need� t� b� delaye� (undocumente� requiremen� o� th� Z8� �
(tm�� peripherals!)�� Hitach� ha� � simpl� circui� t� accomplis� �
thi� i� yo�� happe� t� hav� th� spar� fli� flo� an� OҠ gat� �
floatin� aroun� o� you� board�� � didn'� an� simpl�� redesigne� �
th� wait-stat� generato� t� accomplis� th� sam� thing.
No� Mod� � work� jus� fine.
�
The following section is by:
KA8BMT
Reference:
Hitach� HD6418� 8-Bi� Hig� Integratio� CMO� Microprocesso� Dat� �
Boo� [January� 198� #U77]
PG 27: I/O ADDRESSING NOTES:
"Th� on-chi� I/� registe� addresse� ar� locate� i� th� I/� �
addres� spac� fro� 0000� t� 00FF� (16-bi� I/Ϡ addresses).�� [� �
not� unde� figur� 2.2.� o� pag� 15�� 'NOTE�� A16-A1� � � fo� I/� �
cycles'.� "Thus�� t� acces� th� on-chi� I/� register� (usin� I/� �
instructions),"
[I� ther� som� othe� wa� t� acces� thes� registers�� beside� �
I/� instructions� IOE� an� ME� woul� determin� whethe� i� i� I/� �
o� MEmory�� s� wha� doe� th� las� par� o� th� previou� paragrap� �
mean?]
"th� high-orde� � bit� o� th� 16-bi� I/� addres� mus� b� 0."
"Th� conventiona� I/� instruction� (OU� (m),� � I� A,(m�� � �
OUT� � IN� � etc.� Plac� th� content� o� � CP� register,"
[Th� "B� register�� thi� i� becaus� o� th� wa� th� Z-8� (tm� �
handle� th� "I� g,(C)� an� th� "OU� (C),g�� instructions�� Thi� �
mean� tha� yo� coul� desig� � Z-8� circui� tha� coul� hav� mor� �
tha� 25� I/� address�� b� usin� th� "B� registe� a� par� o� th� �
I/Ϡ address�� Thi� coul� als� mean� tha� i� you� I/Ϡ addres� �
decode� doe� no� properl� accoun� fo� th� A� - A1� addres� line� �
yo� ma� no� ge� th� I/� addres� yo� want.]
"o� th� high-orde� � bit� o� th� addres� bus�� an� thu� ma�� b� �
difficul� t� us� fo� accessin� o� chi� I/� registers."
"Fo� efficien� on-chi� I/� register� access� � numbe� o� ne� �
instruction� hav� bee� adde� whic� forc� th� high-orde� � bit� o� �
th� 16-bi� I/� addres� t� 0�� Thes� instruction� ar� IN0�� OUT0� �
OTIM�� OTIMR� OTDM� OTDM� an� TSTI� (Se� sectio� 3.� Instruction� �
set)."
[Unfortunitl��� th� instruction� describe� i� th堠 las� �
paragrap� woul� no� b� Z-8� compatible�� i� tha� i� o� an� �
consideration�� �� possibl� solutio� woul� b� t� zer� th� "B� �
registe� o� th� 6418�� o� th� Z-8�� befor� doin� an�� I/� �
instructions�� howeve� thi� ma�� no� b� possibl� {i� th� "B� �
registe� i� bein� used� o� practica� i� al� cases.]
�
"Not� tha� whe� writin� t� a� interna� I/Ϡ register�� th� �
sam� I/Ϡ writ� occur� o� th� externa� bus�� However�� th� �
duplicat� externa� I/Ϡ writ� cycl� wil� exhibi� interna� I/� �
writ� cycl� timing�� Fo� example�� th� WAIT�� inpu� an� th� �
programmabl� wai� stat� generato� ar� ignored.�� [Thi� coul� �
conceivabl�� caus� som� slo� peripheral� t� 'g� ou� t� lunch'.� �
"Similarly�� interna� I/Ϡ rea� cycle� als� caus� � duplicat� �
externa� I/Ϡ rea� cycl� - however�� th� externa� rea� dat� i� �
ignore� b� th� HD64180."
"Normally�� externa� I/� addresse� shoul� b� chose� t� avoi� �
overla� wit� interna� I/Ϡ addresse� t� avoi� duplicat� I/� �
accesses."
Severa� place� Hitach� state� tha� th� HD6418� ca� directl� �
addres� 64� o� I/� addres� [whic� i� ca� i� hardward� (page� 2� �
5�� 15�� 5� an� others)� howeve� i� doe� no� tel� ho� t� d� i� i� �
software�� I� ther� som� wa� beside� doin� trick� wit� "B"�� DM� �
o� I/� bloc� instructions�� tha� � missed�� t� addres� mor� tha� �
25��� I/Ϡ locations��� (Suc� a� "OUԠ (1234H),reg�� o� "I� �
reg,(1234H)".)
