/*
* Z80SIM - a Z80-CPU simulator
*
* Copyright (C) 1987-92 by Udo Munk
*
* This module of the Z80-CPU simulator must not be modified by a user,
* see license agreement!
*
* History:
* 28-SEP-87 Development on TARGON/35 with AT&T Unix System V.3
* 11-JAN-89 Release 1.1
* 08-FEB-89 Release 1.2
* 13-MAR-89 Release 1.3
* 09-FEB-90 Release 1.4 Ported to TARGON/31 M10/30
* 20-DEC-90 Release 1.5 Ported to COHERENT 3.0
* 10-JUN-92 Release 1.6 long casting problem solved with COHERENT 3.2
* and some optimization
* 25-JUN-92 Release 1.7 comments in english
*/
/*
* Like the function "cpu()" this one emulates 4 byte opcodes
* starting with 0xdd 0xcb
*/
#include "sim.h"
#include "simglb.h"
long op_ddcb_handel()
{
long trap_ddcb();
long op_tb0ixd(), op_tb1ixd(), op_tb2ixd(), op_tb3ixd();
long op_tb4ixd(), op_tb5ixd(), op_tb6ixd(), op_tb7ixd();
long op_rb0ixd(), op_rb1ixd(), op_rb2ixd(), op_rb3ixd();
long op_rb4ixd(), op_rb5ixd(), op_rb6ixd(), op_rb7ixd();
long op_sb0ixd(), op_sb1ixd(), op_sb2ixd(), op_sb3ixd();
long op_sb4ixd(), op_sb5ixd(), op_sb6ixd(), op_sb7ixd();
long op_rlcixd(), op_rrcixd(), op_rlixd(), op_rrixd();
long op_slaixd(), op_sraixd(), op_srlixd();
register int d;
#ifdef WANT_TIM
register long t;
#endif
d = (char) *PC++;
#ifdef WANT_PCC
if (PC > ram + 65535) /* correct PC overrun */
PC = ram;
#endif
#ifdef WANT_TIM
t = (*op_ddcb[*PC++]) (d); /* execute next opcode */
#else
(*op_ddcb[*PC++]) (d);
#endif
#ifdef WANT_PCC
if (PC > ram + 65535) /* again correct PC overrun */
PC = ram;
#endif
#ifdef WANT_TIM
return(t);
#endif
}
/*
* This function traps all illegal opcodes following the
* initial 0xdd 0xcb of a 4 byte opcode.
*/
static long trap_ddcb()
{
cpu_error = OPTRAP4;
cpu_state = STOPPED;
#ifdef WANT_TIM
return(0L);
#endif
}
static long op_tb0ixd(data) /* BIT 0,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 1) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb1ixd(data) /* BIT 1,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 2) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb2ixd(data) /* BIT 2,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 4) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb3ixd(data) /* BIT 3,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 8) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb4ixd(data) /* BIT 4,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 16) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb5ixd(data) /* BIT 5,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 32) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb6ixd(data) /* BIT 6,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 64) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_tb7ixd(data) /* BIT 7,(IX+d) */
register int data;
{
F &= ~N_FLAG;
F |= H_FLAG;
(*(ram + IX + data) & 128) ? (F &= ~Z_FLAG) : (F |= Z_FLAG);
#ifdef WANT_TIM
return(20L);
#endif
}
static long op_rb0ixd(data) /* RES 0,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~1;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb1ixd(data) /* RES 1,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~2;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb2ixd(data) /* RES 2,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~4;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb3ixd(data) /* RES 3,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~8;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb4ixd(data) /* RES 4,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~16;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb5ixd(data) /* RES 5,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~32;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb6ixd(data) /* RES 6,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~64;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rb7ixd(data) /* RES 7,(IX+d) */
register int data;
{
*(ram + IX + data) &= ~128;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb0ixd(data) /* SET 0,(IX+d) */
register int data;
{
*(ram + IX + data) |= 1;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb1ixd(data) /* SET 1,(IX+d) */
register int data;
{
*(ram + IX + data) |= 2;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb2ixd(data) /* SET 2,(IX+d) */
register int data;
{
*(ram + IX + data) |= 4;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb3ixd(data) /* SET 3,(IX+d) */
register int data;
{
*(ram + IX + data) |= 8;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb4ixd(data) /* SET 4,(IX+d) */
register int data;
{
*(ram + IX + data) |= 16;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb5ixd(data) /* SET 5,(IX+d) */
register int data;
{
*(ram + IX + data) |= 32;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb6ixd(data) /* SET 6,(IX+d) */
register int data;
{
*(ram + IX + data) |= 64;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_sb7ixd(data) /* SET 7,(IX+d) */
register int data;
{
*(ram + IX + data) |= 128;
#ifdef WANT_TIM
return(23L);
#endif
}
static long op_rlcixd(data) /* RLC (IX+d) */
register int data;
{
register int i;
register BYTE *p;
