;;
;; HD64180 MACRO LIBRARY
;;
;; THE FOLLOWING MACROS ENABLE ASSEMBLING HD64180 INSTRUCTIONS
;; WITH DRI COMPATIBLE MACRO ASSEMBLERS.
;;
;; INVOKE WITH "MACLIB H80"
;;
;;
;;
;; MACRO FORMATS
;; ----- -------
;;
;; HD64180 Unique instructions:
;;
;; SLP ; Enter SLEEP mode
;; MLT RR ; 8 bit multiply with 16 bit result
;; IN0 R,P (or IN0 P) ; Input from internal port
;; OUT0 P,R (or OUT0 P) ; Output to internal port
;; OTIM ; Block output, increment
;; OTIMR ; Block output, increment and repeat
;; OTDM ; Block output, decrement
;; OTDMR ; Block output, decrement and repeat
;; TSTIO P ; Non destructive AND, I/O port and A
;; TSTR R (or TST R) ; Non destructive AND, reg and A
;; TSTD D (or TST ID) ; Non destructive AND, immediate data and A
;; TSTP (or TST M) ; Non destructive AND, (HL) and A
;;
;; INTEL HD64180/ZILOG TDL
;; ----- ------------- ---
;; LDX R,D LD R,(IX+D) MOV R,D(IX)
;; LDY R,D LD R,(IY+D) MOV R,D(IY)
;; STX R,D LD (IX+D),R MOV D(IX),R
;; STY R,D LD (IY+D),R MOV D(IY),R
;; MVIX NN,D LD (IX+D),NN MVI D(IX)
;; MVIY NN,D LD (IY+D),NN MVI D(IY)
;; LDAI LD A,I LDAI
;; LDAR LD A,R LDAR
;; STAI LD I,A STAI
;; STAR LD R,A STAR
;; LXIX NNNN LD IX,NNNN LXI IX,NNNN
;; LXIY NNNN LD IY,NNNN LXI IY,NNNN
;; LBCD NNNN LD BC,(NNNN) LBCD NNNN
;; LDED NNNN LD DE,(NNNN) LDED NNNN
;; LSPD NNNN LD SP,(NNNN) LSPD NNNN
;; LIXD NNNN LD IX,(NNNN) LIXD NNNN
;; LIYD NNNN LD IY,(NNNN) LIYD NNNN
;; SBCD NNNN LD (NNNN),BC SBCD NNNN
;; SDED NNNN LD (NNNN),DE SDED NNNN
;; SSPD NNNN LD (NNNN),SP SSPD NNNN
;; SIXD NNNN LD (NNNN),IX SIXD NNNN
;; SIYD NNNN LD (NNNN),IY SIYD NNNN
;; SPIX LD SP,IX SPIX
;; SPIY LD SP,IY SPIY
;; PUSHIX PUSH IX PUSH IX
;; PUSHIY PUSH IY PUSH IY
;; POPIX POP IX POP IX
;; POPIY POP IY POP IY
;; EXAF EX AF,AF' EXAF
;; EXX EXX EXX
;; XTIX EX (SP),IX XTIX
;; XTIY EX (SP),IY XTIY
;; LDI LDI LDI
;; LDIR LDIR LDIR
;; LDD LDD LDD
;; LDDR LDDR LDDR
;; CCI CPI CCI
;; CCIR CPIR CCIR
;; CCD CPD CCD
;; CCDR CPDR CCDR
;; ADDX D ADD (IX+D) ADD D(IX)
;; ADDY D ADD (IY+D) ADD D(IY)
;; ADCX D ADC (IX+D) ADC D(IX)
;; ADCY D ADC (IY+D) ADC D(IY)
;; SUBX D SUB (IX+D) SUB D(IX)
;; SUBY D SUB (IY+D) SUB D(IY)
;; SBCX D SBC (IX+D) SBB D(IX)
;; SBCY D SBC (IY+D) SBB D(IY)
;; ANDX D AND (IX+D) ANA D(IX)
;; ANDY D AND (IY+D) ANA D(IY)
;; XORX D XOR (IX+D) XRA D(IX)
;; XORY D XOR (IY+D) XRA D(IY)
;; ORX D OR (IX+D) ORA D(IX)
;; ORY D OR (IY+D) ORA D(IY)
;; CMPX D CP (IX+D) CMP D(IX)
;; CMPY D CP (IY+D) CMP D(IY)
;; INRX D INC (IX+D) INR D(IX)
;; INRY D INC (IY+D) INR D(IY)
;; DCRX D INC (IX+D) INR D(IX)
;; DCRY D DEC (IY+D) DCR D(IY)
;; NEG NEG NEG
;; IM0 IM0 IM0
;; IM1 IM1 IM1
;; IM2 IM2 IM2
;; DADC RR ADC HL,RR DADC RR
;; DSBC RR SBC HL,RR DSBC RR
;; DADX RR ADD IX,RR DADX RR
;; DADY RR ADD IY,RR DADY RR
;; INXIX INC IX INX IX
;; INXIY INC IY INX IY
;; DCXIX DEC IX DCX IX
;; DCXIY DEC IY DCX IY
;; BIT B,R BIT B,R BIT B,R
;; SETB B,R SET B,R SET B,R
;; RES B,R RES B,R RES B,R
;; BITX B,D BIT B,(IX+D) BIT B,D(IX)
;; BITY B,D BIT B,(IY+D) BIT B,D(IY)
;; SETX B,D SET B,(IX+D) SET B,D(IX)
;; SETY B,D SET B,(IY+D) SET B,D(IY)
;; RESX B,D RES B,(IX+D) RES B,D(IX)
;; RESY B,D RES B,(IY+D) RES B,D(IY)
;; JR ADDR JR ADDR-$ JMPR ADDR
;; JRC ADDR JR C,ADDR-$ JRC ADDR
;; JRNC ADDR JR NC,ADDR-$ JRNC ADDR
;; JRZ ADDR JR Z,ADDR-$ JRZ ADDR
;; JRNZ ADDR JR NZ,ADDR-$ JRNZ ADDR
;; DJNZ ADDR DJNZ ADDR-$ DJNZ ADDR
;; PCIX JMP (IX) PCIX
;; PCIY JMP (IY) PCIY
;; RETI RETI RETI
;; RETN RETN RETN
;; INP R IN R,(C) INP R
;; OUTP R OUT (C),R OUTP R
;; INI INI INI
;; INIR INIR INIR
;; OUTI OTI OUTI
;; OUTIR OTIR OUTIR
;; IND IND IND
;; INDR INDR INDR
;; OUTD OTD OUTD
;; OUTDR OTDR OUTDR
;; RLCR R RLC R RLCR R
;; RLCX D RLC (IX+D) RLCR D(IX)
;; RLCY D RLC (IY+D) RLCR D(IY)
;; RALR R RL R RALR R
;; RALX D RL (IX+D) RALR D(IX)
;; RALY D RL (IY+D) RALR D(IY)
;; RRCR R RRC R RRCR R
;; RRCX D RRC (IX+D) RRCR D(IX)
;; RRCY D RRC (IY+D) RRCR D(IY)
;; RARR R RR R RARR R
;; RARX D RR (IX+D) RARR D(IX)
;; RARY D RR (IY+D) RARR D(IY)
;; SLAR R SLA R SLAR R
;; SLAX D SLA (IX+D) SLAR D(IX)
;; SLAY D SLA (IY+D) SLAR D(IY)
;; SRAR R SRA R SRAR R
;; SRAX D SRA (IX+D) SRAR D(IX)
;; SRAY D SRA (IY+D) SRAR D(IY)
;; SRLR R SRL R SRLR R
;; SRLX D SRL (IX+D) SRLR D(IX)
;; SRLY D SRL (IY+D) SRLR D(IY)
;; RLD RLD RLD
;; RRD RRD RRD
;;
;;
;;
;; @CHK MACRO USED FOR CHECKING 8 BIT DISPLACMENTS
;;
@CHK MACRO ?DD ;; USED FOR CHECKING RANGE OF 8-BIT DISP.S
IF (?DD GT 127) AND (?DD LT -128)
'DISPLACEMENT RANGE ERROR - H80 LIB'
ENDIF
ENDM
;;
@CHKR MACRO ?DD
IF (?DD GT 128) AND (?DD LT -127)
'-----OFFSET RANGE ERROR -- H80 LIB'
ENDIF
ENDM
;;
ERRNZ MACRO ?N
IF ?N NE 00
'----- NON-ZERO MACRO ERROR -----'
ENDIF
ENDM
;;
;; HD64180 orignal command support
??BC EQU 0
??DE EQU 1
??HL EQU 2
??SP EQU 3
SLP MACRO
DB 0EDH,76H
ENDM
MLT MACRO ?R
DB 0EDH,4CH+(??&?R AND 3) SHL 4
ENDM
IN0 MACRO ?R,?P
IF NUL ?P
DB 0EDH,A SHL 3,?R
ELSE
DB 0EDH,(?R AND 7) SHL 3, ?P
ENDIF
ENDM
OUT0 MACRO ?P,?R
IF NUL ?R
DB 0EDH,1+A SHL 3,?P
ELSE
DB 0EDH,1+(?R AND 7) SHL 3,?P
ENDIF
ENDM
OTIM MACRO
DB 0EDH,83H
ENDM
OTIMR MACRO
DB 0EDH,93H
ENDM
OTDM MACRO
DB 0EDH,8BH
ENDM
OTDMR MACRO
DB 0EDH,9BH
ENDM
TSTIO MACRO ?P
DB 0EDH,74H,?P
ENDM
TSTR MACRO ?R
DB 0EDH,4+(?R AND 7) SHL 3
ENDM
TSTD MACRO ?P
DB 0EDH,64H,?P
ENDM
TSTP MACRO
DB 0EDH,34H
ENDM
TST MACRO ?R
?D SET 0
IRPC ?X,?R
?D SET ?D+1
ENDM
IF ?D EQ 1
IRPC ?X,ABCDEHLM
?Y SET ?X
IF ?X EQ ?R
EXITM
ENDIF
ENDM
IF ?Y EQ ?R
DB 0EDH,4+(?R AND 7) SHL 3
EXITM
ENDIF
ENDIF
DB 0EDH,64H,?R
ENDM
;;
;; Standard Zilog Operation Codes
;;
JR MACRO ?N
?D SET ?N-$-1
@CHKR ?D
DB 18H,?N-$-1
ENDM
JRC MACRO ?N
?D SET ?N-$-1
@CHKR ?D
DB 38H,?N-$-1
ENDM
JRNC MACRO ?N
?D SET ?N-$-1
@CHKR ?D
DB 30H,?N-$-1
ENDM
JRZ MACRO ?N
?D SET ?N-$-1
@CHKR ?D
DB 28H,?N-$-1
ENDM
JRNZ MACRO ?N
?D SET ?N-$-1
@CHKR ?D
DB 20H,?N-$-1
ENDM
DJNZ MACRO ?N
?D SET ?N-$-1
@CHKR ?D
DB 10H,?N-$-1
ENDM
;;
;;
LDX MACRO ?R,?D
@CHK ?D
DB 0DDH,?R*8+46H,?D
ENDM
