Index: external/mit/xf86-video-intel/dist/src/i830_driver.c
===================================================================
RCS file: /cvsroot/xsrc/external/mit/xf86-video-intel/dist/src/i830_driver.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 i830_driver.c
--- external/mit/xf86-video-intel/dist/src/i830_driver.c 2 Aug 2008 05:12:36 -0000 1.1.1.1
+++ external/mit/xf86-video-intel/dist/src/i830_driver.c 21 Feb 2009 02:03:42 -0000
@@ -2193,12 +2193,15 @@
/* If the pipe A PLL is active, we can restore the pipe & plane config */
if (pI830->saveDPLL_A & DPLL_VCO_ENABLE)
{
+ OUTREG(FPA0, pI830->saveFPA0);
OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE);
+ POSTING_READ(DPLL_A);
usleep(150);
}
OUTREG(FPA0, pI830->saveFPA0);
OUTREG(FPA1, pI830->saveFPA1);
OUTREG(DPLL_A, pI830->saveDPLL_A);
+ POSTING_READ(DPLL_A);
i830_dpll_settle();
if (IS_I965G(pI830))
OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
@@ -2254,12 +2257,15 @@
/* If the pipe B PLL is active, we can restore the pipe & plane config */
if (pI830->saveDPLL_B & DPLL_VCO_ENABLE)
{
+ OUTREG(FPB0, pI830->saveFPB0);
OUTREG(DPLL_B, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE);
+ POSTING_READ(DPLL_B);
usleep(150);
}
OUTREG(FPB0, pI830->saveFPB0);
OUTREG(FPB1, pI830->saveFPB1);
OUTREG(DPLL_B, pI830->saveDPLL_B);
+ POSTING_READ(DPLL_B);
i830_dpll_settle();
if (IS_I965G(pI830))
OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);
