--- /dev/null 2008-04-17 03:39:03.000000000 +0100
+++ sys/dev/pci/if_lii.c 2008-04-07 20:29:43.000000000 +0100
@@ -0,0 +1,1211 @@
+/* $NetBSD: if_lii.c,v 1.1 2008/03/29 00:16:26 cube Exp $ */
+
+/*
+ * Copyright (c) 2008 The NetBSD Foundation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for Attansic/Atheros's L2 Fast Ethernet controller
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.1 2008/03/29 00:16:26 cube Exp $");
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/types.h>
+#include <sys/device.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/sockio.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+#include <net/if_ether.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/if_liireg.h>
+
+/* #define LII_DEBUG */
+#ifdef LII_DEBUG
+#define DPRINTF(x) printf x
+#else
+#define DPRINTF(x)
+#endif
+
+struct lii_softc {
+ struct device sc_dev;
+ pci_chipset_tag_t sc_pc;
+ pcitag_t sc_tag;
+
+ bus_space_tag_t sc_mmiot;
+ bus_space_handle_t sc_mmioh;
+
+ /*
+ * We allocate a big chunk of DMA-safe memory for all data exchanges.
+ * It is unfortunate that this chip doesn't seem to do scatter-gather.
+ */
+ bus_dma_tag_t sc_dmat;
+ bus_dmamap_t sc_ringmap;
+ bus_dma_segment_t sc_ringseg;
+
+ uint8_t *sc_ring; /* the whole area */
+ size_t sc_ringsize;
+
+ struct rx_pkt *sc_rxp; /* the part used for RX */
+ struct tx_pkt_status *sc_txs; /* the parts used for TX */
+ bus_addr_t sc_txsp;
+ char *sc_txdbase;
+ bus_addr_t sc_txdp;
+
+ unsigned int sc_rxcur;
+ /* the active area is [ack; cur[ */
+ int sc_txs_cur;
+ int sc_txs_ack;
+ int sc_txd_cur;
+ int sc_txd_ack;
+ bool sc_free_tx_slots;
+
+ void *sc_ih;
+
+ struct ethercom sc_ec;
+ struct mii_data sc_mii;
+ struct callout sc_tick_ch;
+ uint8_t sc_eaddr[ETHER_ADDR_LEN];
+
+ int (*sc_memread)(struct lii_softc *, uint32_t,
+ uint32_t *);
+};
+
+static int lii_match(device_t, cfdata_t, void *);
+static void lii_attach(device_t, device_t, void *);
+
+static int lii_reset(struct lii_softc *);
+static bool lii_eeprom_present(struct lii_softc *);
+static int lii_read_macaddr(struct lii_softc *, uint8_t *);
+static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *);
+static void lii_spi_configure(struct lii_softc *);
+static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *);
+static void lii_setmulti(struct lii_softc *);
+static void lii_tick(void *);
+
+static int lii_alloc_rings(struct lii_softc *);
+static int lii_free_tx_space(struct lii_softc *);
+
+static int lii_mii_readreg(device_t, int, int);
+static void lii_mii_writereg(device_t, int, int, int);
+static void lii_mii_statchg(device_t);
+
+static int lii_media_change(struct ifnet *);
+static void lii_media_status(struct ifnet *, struct ifmediareq *);
+
+static int lii_init(struct ifnet *);
+static void lii_start(struct ifnet *);
+static void lii_stop(struct ifnet *, int);
+static void lii_watchdog(struct ifnet *);
+static int lii_ioctl(struct ifnet *, u_long, caddr_t);
+
+static int lii_intr(void *);
+static void lii_rxintr(struct lii_softc *);
+static void lii_txintr(struct lii_softc *);
+
+CFATTACH_DECL(lii, sizeof(struct lii_softc),
+ lii_match, lii_attach, NULL, NULL);
+
+/* #define LII_DEBUG_REGS */
+#ifndef LII_DEBUG_REGS
+#define AT_READ_4(sc,reg) \
+ bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
+#define AT_READ_2(sc,reg) \
+ bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
+#define AT_READ_1(sc,reg) \
+ bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
+#define AT_WRITE_4(sc,reg,val) \
+ bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
+#define AT_WRITE_2(sc,reg,val) \
+ bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
+#define AT_WRITE_1(sc,reg,val) \
+ bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
+#else
+static inline uint32_t
+AT_READ_4(struct lii_softc *sc, bus_size_t reg)
+{
+ uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
+ printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r);
+ return r;
+}
+
+static inline uint16_t
+AT_READ_2(struct lii_softc *sc, bus_size_t reg)
+{
+ uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg);
+ printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r);
+ return r;
+}
+
+static inline uint8_t
+AT_READ_1(struct lii_softc *sc, bus_size_t reg)
+{
+ uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg);
+ printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r);
+ return r;
+}
+
+static inline void
+AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val)
+{
+ printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val);
+ bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val);
+}
+
+static inline void
+AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val)
+{
+ printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val);
+ bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val);
+}
+
+static inline void
+AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val)
+{
+ printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val);
+ bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val);
+}
+#endif
+
+/*
+ * Those are the default Linux parameters.
+ */
+
+#define AT_TXD_NUM 64
+#define AT_TXD_BUFFER_SIZE 8192
+#define AT_RXD_NUM 64
+
+/*
+ * Assuming (you know what that word makes of you) the chunk of memory
+ * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the
+ * first 120 bytes of it, so that the space for the packets, and not the
+ * whole descriptors themselves, are on a 128-byte boundary.
+ */
+
+#define AT_RXD_PADDING 120
+
+static int
+lii_match(device_t parent, cfdata_t cfmatch, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+
+ return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC &&
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100);
+}
+
+static void
+lii_attach(device_t parent, device_t self, void *aux)
+{
+ struct lii_softc *sc = device_private(self);
+ struct pci_attach_args *pa = aux;
+ uint8_t eaddr[ETHER_ADDR_LEN];
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ pci_intr_handle_t ih;
+ const char *intrstr;
+ pcireg_t cmd;
+
+ aprint_naive("\n");
+ aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n");
+
+ sc->sc_pc = pa->pa_pc;
+ sc->sc_tag = pa->pa_tag;
+ sc->sc_dmat = pa->pa_dmat;
+
+ cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
+ cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
+ cmd &= ~PCI_COMMAND_IO_ENABLE;
+ pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd);
+
+ switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) {
+ case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
+ case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M:
+ case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
+ break;
+ default:
+ aprint_error("invalid base address register\n");
+ break;
+ }
+ if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0,
+ &sc->sc_mmiot, &sc->sc_mmioh, NULL, NULL) != 0) {
+ aprint_error("failed to map registers\n");
+ return;
+ }
+
+ if (lii_reset(sc))
+ return;
+
+ lii_spi_configure(sc);
+
+ if (lii_eeprom_present(sc))
+ sc->sc_memread = lii_eeprom_read;
+ else
+ sc->sc_memread = lii_spi_read;
+
+ if (lii_read_macaddr(sc, eaddr))
+ return;
+ memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN);
+
+ aprint_normal("Ethernet address %s\n",
+ ether_sprintf(eaddr));
+
+ if (pci_intr_map(pa, &ih) != 0) {
+ aprint_error("failed to map interrupt\n");
+ return;
+ }
+ intrstr = pci_intr_string(sc->sc_pc, ih);
+ sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error("failed to establish interrupt");
+ if (intrstr != NULL)
+ aprint_error(" at %s", intrstr);
+ aprint_error("\n");
+ return;
+ }
+ aprint_normal("interrupting at %s\n", intrstr);
+
+ if (lii_alloc_rings(sc)) {
+ pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
+ return;
+ }
+
+ callout_init(&sc->sc_tick_ch);
+ callout_setfunc(&sc->sc_tick_ch, lii_tick, sc);
+
+ sc->sc_mii.mii_ifp = ifp;
+ sc->sc_mii.mii_readreg = lii_mii_readreg;
+ sc->sc_mii.mii_writereg = lii_mii_writereg;
+ sc->sc_mii.mii_statchg = lii_mii_statchg;
+ ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change,
+ lii_media_status);
+ mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
+ MII_OFFSET_ANY, 0);
+ ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+
+ strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
+ ifp->if_softc = sc;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = lii_ioctl;
+ ifp->if_start = lii_start;
+ ifp->if_watchdog = lii_watchdog;
+ ifp->if_init = lii_init;
+ ifp->if_stop = lii_stop;
+ IFQ_SET_READY(&ifp->if_snd);
+
+ /*
+ * While the device does support HW VLAN tagging, there is no
+ * real point using that feature.
+ */
+ sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
+
+ if_attach(ifp);
+ ether_ifattach(ifp, eaddr);
+
+ return;
+}
+
+static int
+lii_reset(struct lii_softc *sc)
+{
+ int i;
+
+ DPRINTF(("lii_reset\n"));
+
+ AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST);
+ DELAY(1000);
+
+ for (i = 0; i < 10; ++i) {
+ if (AT_READ_4(sc, ATL2_BIS) == 0)
+ break;
+ DELAY(1000);
+ }
+
+ if (i == 10) {
+ aprint_error("reset failed\n");
+ return 1;
+ }
+
+ AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE);
+ DELAY(10);
+
+ /* Init PCI-Express module */
+ /* Magic Numbers Warning */
+ AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF);
+ AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF);
+
+ return 0;
+}
+
+static bool
+lii_eeprom_present(struct lii_softc *sc)
+{
+ /*
+ * The Linux driver does this, but then it has a very weird way of
+ * checking whether the PCI configuration space exposes the Vital
+ * Product Data capability, so maybe it's not really needed.
+ */
+
+#ifdef weirdloonix
+ uint32_t val;
+
+ val = AT_READ_4(sc, ATL2_SFC);
+ if (val & SFC_EN_VPD)
+ AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD));
+#endif
+
+ return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD,
+ NULL, NULL) == 1;
+}
+
+static int
+lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
+{
+ int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val);
+
+ DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val));
+
+ return r;
+}
+
+static void
+lii_spi_configure(struct lii_softc *sc)
+{
+ /*
+ * We don't offer a way to configure the SPI Flash vendor parameter, so
+ * the table is given for reference
+ */
+ static const struct lii_spi_flash_vendor {
+ const char *sfv_name;
+ const uint8_t sfv_opcodes[9];
+ } lii_sfv[] = {
+ { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } },
+ { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } },
+ { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } },
+ };
+#define SF_OPCODE_WRSR 0
+#define SF_OPCODE_READ 1
+#define SF_OPCODE_PRGM 2
+#define SF_OPCODE_WREN 3
+#define SF_OPCODE_WRDI 4
+#define SF_OPCODE_RDSR 5
+#define SF_OPCODE_RDID 6
+#define SF_OPCODE_SECT_ER 7
+#define SF_OPCODE_CHIP_ER 8
+
+#define SF_DEFAULT_VENDOR 0
+ static const uint8_t vendor = SF_DEFAULT_VENDOR;
+
+ /*
+ * Why isn't WRDI used? Heck if I know.
+ */
+
+ AT_WRITE_1(sc, ATL2_SFOP_WRSR,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]);
+ AT_WRITE_1(sc, ATL2_SFOP_READ,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]);
+ AT_WRITE_1(sc, ATL2_SFOP_PROGRAM,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]);
+ AT_WRITE_1(sc, ATL2_SFOP_WREN,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]);
+ AT_WRITE_1(sc, ATL2_SFOP_RDSR,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]);
+ AT_WRITE_1(sc, ATL2_SFOP_RDID,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]);
+ AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]);
+ AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE,
+ lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]);
+}
+
+#define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \
+ ( (((cssetup) & SFC_CS_SETUP_MASK) \
+ << SFC_CS_SETUP_SHIFT) \
+ | (((clkhi) & SFC_CLK_HI_MASK) \
+ << SFC_CLK_HI_SHIFT) \
+ | (((clklo) & SFC_CLK_LO_MASK) \
+ << SFC_CLK_LO_SHIFT) \
+ | (((cshold) & SFC_CS_HOLD_MASK) \
+ << SFC_CS_HOLD_SHIFT) \
+ | (((cshi) & SFC_CS_HI_MASK) \
+ << SFC_CS_HI_SHIFT) \
+ | (((ins) & SFC_INS_MASK) \
+ << SFC_INS_SHIFT))
+
+/* Magic settings from the Linux driver */
+
+#define CUSTOM_SPI_CS_SETUP 2
+#define CUSTOM_SPI_CLK_HI 2
+#define CUSTOM_SPI_CLK_LO 2
+#define CUSTOM_SPI_CS_HOLD 2
+#define CUSTOM_SPI_CS_HI 3
+
+static int
+lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
+{
+ uint32_t v;
+ int i;
+
+ AT_WRITE_4(sc, ATL2_SF_DATA, 0);
+ AT_WRITE_4(sc, ATL2_SF_ADDR, reg);
+
+ v = SFC_WAIT_READY |
+ MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI,
+ CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1);
+
+ AT_WRITE_4(sc, ATL2_SFC, v);
+ v |= SFC_START;
+ AT_WRITE_4(sc, ATL2_SFC, v);
+
+ for (i = 0; i < 10; ++i) {
+ DELAY(1000);
+ if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START))
+ break;
+ }
+ if (i == 10)
+ return EBUSY;
+
+ *val = AT_READ_4(sc, ATL2_SF_DATA);
+ return 0;
+}
+
+static int
+lii_read_macaddr(struct lii_softc *sc, uint8_t *ea)
+{
+ uint32_t offset = 0x100;
+ uint32_t val, val1, addr0 = 0, addr1 = 0;
+ uint8_t found = 0;
+
+ while ((*sc->sc_memread)(sc, offset, &val) == 0) {
+ offset += 4;
+
+ /* Each chunk of data starts with a signature */
+ if ((val & 0xff) != 0x5a)
+ break;
+ if ((*sc->sc_memread)(sc, offset, &val1))
+ break;
+
+ offset += 4;
+
+ val >>= 16;
+ switch (val) {
+ case ATL2_MAC_ADDR_0:
+ addr0 = val1;
+ ++found;
+ break;
+ case ATL2_MAC_ADDR_1:
+ addr1 = val1;
+ ++found;
+ break;
+ default:
+ continue;
+ }
+ }
+
+ if (found < 2) {
+ aprint_error("error reading MAC address\n");
+ return 1;
+ }
+
+ addr0 = htole32(addr0);
+ addr1 = htole32(addr1);
+
+ if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) ||
+ (addr0 == 0 && (addr1 & 0xffff) == 0)) {
+ addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0));
+ addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1));
+ }
+
+ ea[0] = (addr1 & 0x0000ff00) >> 8;
+ ea[1] = (addr1 & 0x000000ff);
+ ea[2] = (addr0 & 0xff000000) >> 24;
+ ea[3] = (addr0 & 0x00ff0000) >> 16;
+ ea[4] = (addr0 & 0x0000ff00) >> 8;
+ ea[5] = (addr0 & 0x000000ff);
+
+ return 0;
+}
+
+static int
+lii_mii_readreg(device_t dev, int phy, int reg)
+{
+ struct lii_softc *sc = device_private(dev);
+ uint32_t val;
+ int i;
+
+ val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
+
+ val |= MDIOC_START | MDIOC_SUP_PREAMBLE;
+ val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
+
+ val |= MDIOC_READ;
+
+ AT_WRITE_4(sc, ATL2_MDIOC, val);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; ++i) {
+ DELAY(2);
+ val = AT_READ_4(sc, ATL2_MDIOC);
+ if ((val & (MDIOC_START | MDIOC_BUSY)) == 0)
+ break;
+ }
+
+ if (i == MDIO_WAIT_TIMES)
+ aprint_error("timeout reading PHY %d reg %d\n", phy,
+ reg);
+
+ return (val & 0x0000ffff);
+}
+
+static void
+lii_mii_writereg(device_t dev, int phy, int reg, int data)
+{
+ struct lii_softc *sc = device_private(dev);
+ uint32_t val;
+ int i;
+
+ val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
+ val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT;
+
+ val |= MDIOC_START | MDIOC_SUP_PREAMBLE;
+ val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
+
+ /* val |= MDIOC_WRITE; */
+
+ AT_WRITE_4(sc, ATL2_MDIOC, val);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; ++i) {
+ DELAY(2);
+ val = AT_READ_4(sc, ATL2_MDIOC);
+ if ((val & (MDIOC_START | MDIOC_BUSY)) == 0)
+ break;
+ }
+
+ if (i == MDIO_WAIT_TIMES)
+ aprint_error("timeout writing PHY %d reg %d\n", phy,
+ reg);
+}
+
+static void
+lii_mii_statchg(device_t dev)
+{
+ struct lii_softc *sc = device_private(dev);
+ uint32_t val;
+
+ DPRINTF(("lii_mii_statchg\n"));
+
+ val = AT_READ_4(sc, ATL2_MACC);
+
+ if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX)
+ val |= MACC_FDX;
+ else
+ val &= ~MACC_FDX;
+
+ AT_WRITE_4(sc, ATL2_MACC, val);
+}
+
+static int
+lii_media_change(struct ifnet *ifp)
+{
+ struct lii_softc *sc = ifp->if_softc;
+
+ DPRINTF(("lii_media_change\n"));
+
+ if (ifp->if_flags & IFF_UP)
+ mii_mediachg(&sc->sc_mii);
+ return 0;
+}
+
+static void
+lii_media_status(struct ifnet *ifp, struct ifmediareq *imr)
+{
+ struct lii_softc *sc = ifp->if_softc;
+
+ DPRINTF(("lii_media_status\n"));
+
+ mii_pollstat(&sc->sc_mii);
+ imr->ifm_status = sc->sc_mii.mii_media_status;
+ imr->ifm_active = sc->sc_mii.mii_media_active;
+}
+
+static int
+lii_init(struct ifnet *ifp)
+{
+ struct lii_softc *sc = ifp->if_softc;
+ uint32_t val;
+ int error;
+
+ DPRINTF(("lii_init\n"));
+
+ lii_stop(ifp, 0);
+
+ memset(sc->sc_ring, 0, sc->sc_ringsize);
+
+ /* Disable all interrupts */
+ AT_WRITE_4(sc, ATL2_ISR, 0xffffffff);
+
+ /* XXX endianness */
+ AT_WRITE_4(sc, ATL2_MAC_ADDR_0,
+ sc->sc_eaddr[2] << 24 |
+ sc->sc_eaddr[3] << 16 |
+ sc->sc_eaddr[4] << 8 |
+ sc->sc_eaddr[5]);
+ AT_WRITE_4(sc, ATL2_MAC_ADDR_1,
+ sc->sc_eaddr[0] << 8 |
+ sc->sc_eaddr[1]);
+
+ AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0);
+/* XXX
+ sc->sc_ringmap->dm_segs[0].ds_addr >> 32);
+*/
+ AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO,
+ (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff)
+ + AT_RXD_PADDING);
+ AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO,
+ sc->sc_txsp & 0xffffffff);
+ AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO,
+ sc->sc_txdp & 0xffffffff);
+
+ AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4);
+ AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM);
+ AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM);
+
+ /*
+ * Inter Paket Gap Time = 0x60 (IPGT)
+ * Minimum inter-frame gap for RX = 0x50 (MIFG)
+ * 64-bit Carrier-Sense window = 0x40 (IPGR1)
+ * 96-bit IPG window = 0x60 (IPGR2)
+ */
+ AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060);
+
+ /*
+ * Collision window = 0x37 (LCOL)
+ * Maximum # of retrans = 0xf (RETRY)
+ * Maximum binary expansion # = 0xa (ABEBT)
+ * IPG to start jam = 0x7 (JAMIPG)
+ */
+ AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 |
+ MHDC_EXC_DEF_EN);
+
+ /* 100 means 200us */
+ AT_WRITE_2(sc, ATL2_IMTIV, 100);
+ AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN);
+
+ /* 500000 means 100ms */
+ AT_WRITE_2(sc, ATL2_IALTIV, 50000);
+
+ AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN
+ + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
+
+ /* unit unknown for TX cur-through threshold */
+ AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177);
+
+ AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8);
+ AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12);
+
+ sc->sc_rxcur = 0;
+ sc->sc_txs_cur = sc->sc_txs_ack = 0;
+ sc->sc_txd_cur = sc->sc_txd_ack = 0;
+ sc->sc_free_tx_slots = true;
+ AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur);
+ AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
+
+ AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN);
+ AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN);
+
+ AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT);
+
+ error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0);
+ AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff);
+ AT_WRITE_4(sc, ATL2_ISR, 0);
+ if (error) {
+ aprint_error("init failed\n");
+ goto out;
+ }
+
+ lii_setmulti(sc);
+
+ val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX;
+
+ val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY |
+ MACC_TX_FLOW_EN | MACC_RX_FLOW_EN |
+ MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN;
+
+ if (ifp->if_flags & IFF_PROMISC)
+ val |= MACC_PROMISC_EN;
+ else if (ifp->if_flags & IFF_ALLMULTI)
+ val |= MACC_ALLMULTI_EN;
+
+ val |= 7 << MACC_PREAMBLE_LEN_SHIFT;
+ val |= 2 << MACC_HDX_LEFT_BUF_SHIFT;
+
+ AT_WRITE_4(sc, ATL2_MACC, val);
+
+ mii_mediachg(&sc->sc_mii);
+
+ AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK);
+
+ callout_schedule(&sc->sc_tick_ch, hz);
+
+ ifp->if_flags |= IFF_RUNNING;
+ ifp->if_flags &= ~IFF_OACTIVE;
+
+out:
+ return error;
+}
+
+static void
+lii_tx_put(struct lii_softc *sc, struct mbuf *m)
+{
+ int left;
+ struct tx_pkt_header *tph =
+ (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur);
+
+ memset(tph, 0, sizeof *tph);
+ tph->txph_size = m->m_pkthdr.len;
+
+ sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE;
+
+ /*
+ * We already know we have enough space, so if there is a part of the
+ * space ahead of txd_cur that is active, it doesn't matter because
+ * left will be large enough even without it.
+ */
+ left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur;
+
+ if (left > m->m_pkthdr.len) {
+ m_copydata(m, 0, m->m_pkthdr.len,
+ sc->sc_txdbase + sc->sc_txd_cur);
+ sc->sc_txd_cur += m->m_pkthdr.len;
+ } else {
+ m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur);
+ m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase);
+ sc->sc_txd_cur = m->m_pkthdr.len - left;
+ }
+
+ /* Round to a 32-bit boundary */
+ sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE;
+ if (sc->sc_txd_cur == sc->sc_txd_ack)
+ sc->sc_free_tx_slots = false;
+}
+
+static int
+lii_free_tx_space(struct lii_softc *sc)
+{
+ int space;
+
+ if (sc->sc_txd_cur >= sc->sc_txd_ack)
+ space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) +
+ sc->sc_txd_ack;
+ else
+ space = sc->sc_txd_ack - sc->sc_txd_cur;
+
+ /* Account for the tx_pkt_header */
+ return (space - 4);
+}
+
+static void
+lii_start(struct ifnet *ifp)
+{
+ struct lii_softc *sc = ifp->if_softc;
+ struct mbuf *m0;
+
+ DPRINTF(("lii_start\n"));
+
+ if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
+ for (;;) {
+ IFQ_POLL(&ifp->if_snd, m0);
+ if (m0 == NULL)
+ break;
+
+ if (!sc->sc_free_tx_slots ||
+ lii_free_tx_space(sc) < m0->m_pkthdr.len) {
+ ifp->if_flags |= IFF_OACTIVE;
+ break;
+ }
+
+ lii_tx_put(sc, m0);
+
+ DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur));
+
+ sc->sc_txs[sc->sc_txs_cur].txps_update = 0;
+ sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM;
+ if (sc->sc_txs_cur == sc->sc_txs_ack)
+ sc->sc_free_tx_slots = false;
+
+ AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4);
+
+ IFQ_DEQUEUE(&ifp->if_snd, m0);
+
+#if NBPFILTER > 0
+ if (ifp->if_bpf != NULL)
+ bpf_mtap(ifp->if_bpf, m0);
+#endif
+ m_freem(m0);
+ }
+}
+
+static void
+lii_stop(struct ifnet *ifp, int disable)
+{
+ struct lii_softc *sc = ifp->if_softc;
+
+ callout_stop(&sc->sc_tick_ch);
+
+ ifp->if_timer = 0;
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+ mii_down(&sc->sc_mii);
+
+ lii_reset(sc);
+
+ AT_WRITE_4(sc, ATL2_IMR, 0);
+}
+
+static int
+lii_intr(void *v)
+{
+ struct lii_softc *sc = v;
+ uint32_t status;
+
+ status = AT_READ_4(sc, ATL2_ISR);
+ if (status == 0)
+ return 0;
+
+ DPRINTF(("lii_intr (%x)\n", status));
+
+ /* Clear the interrupt and disable them */
+ AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT);
+
+ if (status & (ISR_PHY | ISR_MANUAL)) {
+ /* Ack PHY interrupt. Magic register */
+ if (status & ISR_PHY)
+ (void)lii_mii_readreg(&sc->sc_dev, 1, 19);
+ mii_mediachg(&sc->sc_mii);
+ }
+
+ if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) {
+ lii_init(&sc->sc_ec.ec_if);
+ return 1;
+ }
+
+ if (status & ISR_RX_EVENT) {
+#ifdef LII_DEBUG
+ if (!(status & ISR_RS_UPDATE))
+ printf("rxintr %08x\n", status);
+#endif
+ lii_rxintr(sc);
+ }
+
+ if (status & ISR_TX_EVENT)
+ lii_txintr(sc);
+
+ /* Re-enable interrupts */
+ AT_WRITE_4(sc, ATL2_ISR, 0);
+
+ return 1;
+}
+
+static void
+lii_rxintr(struct lii_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct rx_pkt *rxp;
+ struct mbuf *m;
+ uint16_t size;
+
+ DPRINTF(("lii_rxintr\n"));
+
+ for (;;) {
+ rxp = &sc->sc_rxp[sc->sc_rxcur];
+ if (rxp->rxp_update == 0)
+ break;
+
+ DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur,
+ rxp->rxp_size, rxp->rxp_flags));
+ sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM;
+ rxp->rxp_update = 0;
+ if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) {
+ ++ifp->if_ierrors;
+ continue;
+ }
+
+ MGETHDR(m, M_DONTWAIT, MT_DATA);
+ if (m == NULL) {
+ ++ifp->if_ierrors;
+ continue;
+ }
+ size = rxp->rxp_size - ETHER_CRC_LEN;
+ if (size > MHLEN) {
+ MCLGET(m, M_DONTWAIT);
+ if ((m->m_flags & M_EXT) == 0) {
+ m_freem(m);
+ ++ifp->if_ierrors;
+ continue;
+ }
+ }
+
+ m->m_pkthdr.rcvif = ifp;
+ /* Copy the packet withhout the FCS */
+ m->m_pkthdr.len = m->m_len = size;
+ memcpy(mtod(m, void *), &rxp->rxp_data[0], size);
+ ++ifp->if_ipackets;
+
+#if NBPFILTER > 0
+ if (ifp->if_bpf)
+ bpf_mtap(ifp->if_bpf, m);
+#endif
+
+ (*ifp->if_input)(ifp, m);
+ }
+
+ AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
+}
+
+static void
+lii_txintr(struct lii_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct tx_pkt_status *txs;
+ struct tx_pkt_header *txph;
+
+ DPRINTF(("lii_txintr\n"));
+
+ for (;;) {
+ txs = &sc->sc_txs[sc->sc_txs_ack];
+ if (txs->txps_update == 0)
+ break;
+ DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack));
+ sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM;
+ sc->sc_free_tx_slots = true;
+
+ txs->txps_update = 0;
+
+ txph = (struct tx_pkt_header *)
+ (sc->sc_txdbase + sc->sc_txd_ack);
+
+ if (txph->txph_size != txs->txps_size)
+ aprint_error("mismatched status and packet\n");
+ /*
+ * Move ack by the packet size, taking the packet header in
+ * account and round to the next 32-bit boundary
+ * (7 = sizeof(header) + 3)
+ */
+ sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3;
+ sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE;
+
+ if (txs->txps_flags & ATL2_TXF_SUCCESS)
+ ++ifp->if_opackets;
+ else
+ ++ifp->if_oerrors;
+ ifp->if_flags &= ~IFF_OACTIVE;
+ }
+
+ if (sc->sc_free_tx_slots)
+ lii_start(ifp);
+}
+
+static int
+lii_alloc_rings(struct lii_softc *sc)
+{
+ int nsegs;
+ bus_size_t bs;
+
+ /*
+ * We need a big chunk of DMA-friendly memory because descriptors
+ * are not separate from data on that crappy hardware, which means
+ * we'll have to copy data from and to that memory zone to and from
+ * the mbufs.
+ *
+ * How lame is that? Using the default values from the Linux driver,
+ * we allocate space for receiving up to 64 full-size Ethernet frames,
+ * and only 8kb for transmitting up to 64 Ethernet frames.
+ */
+
+ sc->sc_ringsize = bs = AT_RXD_PADDING
+ + AT_RXD_NUM * sizeof(struct rx_pkt)
+ + AT_TXD_NUM * sizeof(struct tx_pkt_status)
+ + AT_TXD_BUFFER_SIZE;
+
+ if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30),
+ BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) {
+ aprint_error("bus_dmamap_create failed\n");
+ return 1;
+ }
+
+ if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30),
+ &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) {
+ aprint_error("bus_dmamem_alloc failed\n");
+ goto fail;
+ }
+
+ if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs,
+ (caddr_t *)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) {
+ aprint_error("bus_dmamem_map failed\n");
+ goto fail1;
+ }
+
+ if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring,
+ bs, NULL, BUS_DMA_NOWAIT) != 0) {
+ aprint_error("bus_dmamap_load failed\n");
+ goto fail2;
+ }
+
+ sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING);
+ sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING
+ + AT_RXD_NUM * sizeof(struct rx_pkt));
+ sc->sc_txdbase = ((char *)sc->sc_txs)
+ + AT_TXD_NUM * sizeof(struct tx_pkt_status);
+ sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr
+ + ((char *)sc->sc_txs - (char *)sc->sc_ring);
+ sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr
+ + ((char *)sc->sc_txdbase - (char *)sc->sc_ring);
+
+ return 0;
+
+fail2:
+ bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs);
+fail1:
+ bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs);
+fail:
+ bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap);
+ return 1;
+}
+
+static void
+lii_watchdog(struct ifnet *ifp)
+{
+ aprint_error("watchdog timeout\n");
+ ++ifp->if_oerrors;
+ lii_init(ifp);
+}
+
+static int
+lii_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+ struct lii_softc *sc = ifp->if_softc;
+ int s, error;
+
+ s = splnet();
+
+ switch(cmd) {
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
+ if (ifp->if_flags & IFF_RUNNING)
+ lii_setmulti(sc);
+ error = 0;
+ }
+ break;
+ case SIOCSIFMEDIA:
+ case SIOCGIFMEDIA:
+ error = ifmedia_ioctl(ifp, (struct ifreq *)data,
+ &sc->sc_mii.mii_media, cmd);
+ break;
+ default:
+ error = ether_ioctl(ifp, cmd, data);
+ if (error == ENETRESET) {
+ if (ifp->if_flags & IFF_RUNNING)
+ lii_setmulti(sc);
+ error = 0;
+ }
+ break;
+ }
+
+ splx(s);
+
+ return error;
+}
+
+static void
+lii_setmulti(struct lii_softc *sc)
+{
+ struct ethercom *ec = &sc->sc_ec;
+ struct ifnet *ifp = &ec->ec_if;
+ uint32_t mht0 = 0, mht1 = 0, crc;
+ struct ether_multi *enm;
+ struct ether_multistep step;
+
+ /* Clear multicast hash table */
+ AT_WRITE_4(sc, ATL2_MHT, 0);
+ AT_WRITE_4(sc, ATL2_MHT + 4, 0);
+
+ ifp->if_flags &= ~IFF_ALLMULTI;
+
+ ETHER_FIRST_MULTI(step, ec, enm);
+ while (enm != NULL) {
+ if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
+ ifp->if_flags |= IFF_ALLMULTI;
+ mht0 = mht1 = 0;
+ goto alldone;
+ }
+
+ crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
+
+ if (crc & (1 << 31))
+ mht1 |= (1 << (crc & 0x0000001f));
+ else
+ mht0 |= (1 << (crc & 0x0000001f));
+
+ ETHER_NEXT_MULTI(step, enm);
+ }
+
+alldone:
+ AT_WRITE_4(sc, ATL2_MHT, mht0);
+ AT_WRITE_4(sc, ATL2_MHT+4, mht1);
+}
+
+static void
+lii_tick(void *v)
+{
+ struct lii_softc *sc = v;
+ int s;
+
+ s = splnet();
+ mii_tick(&sc->sc_mii);
+ splx(s);
+
+ callout_schedule(&sc->sc_tick_ch, hz);
+}
--- /dev/null 2008-04-17 03:39:03.000000000 +0100
+++ sys/dev/pci/if_liireg.h 2008-03-31 16:05:32.000000000 +0100
@@ -0,0 +1,386 @@
+/* $NetBSD: if_liireg.h,v 1.1 2008/03/29 00:16:26 cube Exp $ */
+
+/*
+ * Copyright (c) 2008 The NetBSD Foundation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI configuration space seems to be mapped in the first 0x100 bytes of
+ * the register area.
+ */
+
+/* SPI Flash Control register */
+#define ATL2_SFC 0x0200
+#define SFC_STS_NON_RDY 0x00000001
+#define SFC_STS_WEN 0x00000002
+#define SFC_STS_WPEN 0x00000080
+#define SFC_DEV_STS_MASK 0x000000ff
+#define SFC_DEV_STS_SHIFT 0
+#define SFC_INS_MASK 0x07
+#define SFC_INS_SHIFT 8
+#define SFC_START 0x00000800
+#define SFC_EN_VPD 0x00002000
+#define SFC_LDSTART 0x00008000
+#define SFC_CS_HI_MASK 0x03
+#define SFC_CS_HI_SHIFT 16
+#define SFC_CS_HOLD_MASK 0x03
+#define SFC_CS_HOLD_SHIFT 18
+#define SFC_CLK_LO_MASK 0x03
+#define SFC_CLK_LO_SHIFT 20
+#define SFC_CLK_HI_MASK 0x03
+#define SFC_CLK_HI_SHIFT 22
+#define SFC_CS_SETUP_MASK 0x03
+#define SFC_CS_SETUP_SHIFT 24
+#define SFC_EROMPGSZ_MASK 0x03
+#define SFC_EROMPGSZ_SHIFT 26
+#define SFC_WAIT_READY 0x10000000
+
+/* SPI Flash Address register */
+#define ATL2_SF_ADDR 0x0204
+
+/* SPI Flash Data register */
+#define ATL2_SF_DATA 0x0208
+
+/* SPI Flash Configuration register */
+#define ATL2_SFCF 0x020c
+#define SFCF_LD_ADDR_MASK 0x00ffffff
+#define SFCF_LD_ADDR_SHIFT 0
+#define SFCF_VPD_ADDR_MASK 0x03
+#define SFCF_VPD_ADDR_SHIFT 24
+#define SFCF_LD_EXISTS 0x04000000
+
+/* SPI Flash op codes programmation registers */
+#define ATL2_SFOP_PROGRAM 0x0210
+#define ATL2_SFOP_SC_ERASE 0x0211
+#define ATL2_SFOP_CHIP_ERASE 0x0212
+#define ATL2_SFOP_RDID 0x0213
+#define ATL2_SFOP_WREN 0x0214
+#define ATL2_SFOP_RDSR 0x0215
+#define ATL2_SFOP_WRSR 0x0216
+#define ATL2_SFOP_READ 0x0217
+
+/* TWSI Control register, whatever that is */
+#define ATL2_TWSIC 0x0218
+#define TWSIC_LD_OFFSET_MASK 0x000000ff
+#define TWSIC_LD_OFFSET_SHIFT 0
+#define TWSIC_LD_SLV_ADDR_MASK 0x07
+#define TWSIC_LD_SLV_ADDR_SHIFT 8
+#define TWSIC_SW_LDSTART 0x00000800
+#define TWSIC_HW_LDSTART 0x00001000
+#define TWSIC_SMB_SLV_ADDR_MASK 0x7F
+#define TWSIC_SMB_SLV_ADDR_SHIFT 15
+#define TWSIC_LD_EXIST 0x00400000
+#define TWSIC_READ_FREQ_SEL_MASK 0x03
+#define TWSIC_READ_FREQ_SEL_SHIFT 23
+#define TWSIC_FREQ_SEL_100K 0
+#define TWSIC_FREQ_SEL_200K 1
+#define TWSIC_FREQ_SEL_300K 2
+#define TWSIC_FREQ_SEL_400K 3
+#define TWSIC_WRITE_FREQ_SEL_MASK 0x03
+#define TWSIC_WRITE_FREQ_SEL_SHIFT 24
+
+/* PCI-Express Device Misc. Control register? (size unknown) */
+#define ATL2_PCEDMC 0x021c
+#define PCEDMC_RETRY_BUFDIS 0x01
+#define PCEDMC_EXT_PIPE 0x02
+#define PCEDMC_SPIROM_EXISTS 0x04
+#define PCEDMC_SERDES_ENDIAN 0x08
+#define PCEDMC_SERDES_SEL_DIN 0x10
+
+/* PCI-Express PHY Miscellaneous register (size unknown) */
+#define ATL2_PCEPM 0x1000
+#define PCEPM_FORCE_RCV_DET 0x04
+
+/* PCI-Express DLL TX Control register */
+#define ATL2_PCEDTXC 0x1104
+#define PCEDTX_SEL_NOR_CLK 0x00000400
+#define PCEDTX_DEF 0x00000568
+
+/* PCI-Express-related register (LTSSM test mode) */
+#define ATL2_PCELTM 0x12fc
+#define PCELTM_DEF 0x00006500
+
+/* Selene Master Control register */
+#define ATL2_SMC 0x1400
+#define SMC_SOFT_RST 0x00000001
+#define SMC_MTIMER_EN 0x00000002
+#define SMC_ITIMER_EN 0x00000004
+#define SMC_MANUAL_INT 0x00000008
+#define SMC_REV_NUM_MASK 0xff
+#define SMC_REV_NUM_SHIFT 16
+#define SMC_DEV_ID_MASK 0xff
+#define SMC_DEV_ID_SHIFT 24
+
+/* Timer Initial Value register */
+#define ATL2_TIV 0x1404
+
+/* IRQ Moderator Timer Initial Value register */
+#define ATL2_IMTIV 0x1408
+
+/* PHY Control register */
+#define ATL2_PHYC 0x140c
+#define PHYC_ENABLE 0x0001
+
+/* IRQ Anti-Lost Timer Initial Value register
+ --> Time allowed for software to clear the interrupt */
+#define ATL2_IALTIV 0x140e
+
+/* Block Idle Status register
+ --> Bit set if matching state machine is not idle */
+#define ATL2_BIS 0x1410
+#define BIS_RXMAC 0x00000001
+#define BIS_TXMAC 0x00000002
+#define BIS_DMAR 0x00000004
+#define BIS_DMAW 0x00000008
+
+/* MDIO Control register */
+#define ATL2_MDIOC 0x1414
+#define MDIOC_DATA_MASK 0x0000ffff
+#define MDIOC_DATA_SHIFT 0
+#define MDIOC_REG_MASK 0x1f
+#define MDIOC_REG_SHIFT 16
+#define MDIOC_WRITE 0x00000000
+#define MDIOC_READ 0x00200000
+#define MDIOC_SUP_PREAMBLE 0x00400000
+#define MDIOC_START 0x00800000
+#define MDIOC_CLK_SEL_MASK 0x07
+#define MDIOC_CLK_SEL_SHIFT 24
+#define MDIOC_CLK_25_4 0
+#define MDIOC_CLK_25_6 2
+#define MDIOC_CLK_25_8 3
+#define MDIOC_CLK_25_10 4
+#define MDIOC_CLK_25_14 5
+#define MDIOC_CLK_25_20 6
+#define MDIOC_CLK_25_28 7
+#define MDIOC_BUSY 0x08000000
+/* Time to wait for MDIO, waiting for 2us in-between */
+#define MDIO_WAIT_TIMES 10
+
+/* SerDes Lock Detect Control and Status register */
+#define ATL2_SERDES 0x1424
+#define SERDES_LOCK_DETECT 0x01
+#define SERDES_LOCK_DETECT_EN 0x02
+
+/* MAC Control register */
+#define ATL2_MACC 0x1480
+#define MACC_TX_EN 0x00000001
+#define MACC_RX_EN 0x00000002
+#define MACC_TX_FLOW_EN 0x00000004
+#define MACC_RX_FLOW_EN 0x00000008
+#define MACC_LOOPBACK 0x00000010
+#define MACC_FDX 0x00000020
+#define MACC_ADD_CRC 0x00000040
+#define MACC_PAD 0x00000080
+#define MACC_PREAMBLE_LEN_MASK 0x0f
+#define MACC_PREAMBLE_LEN_SHIFT 10
+#define MACC_STRIP_VLAN 0x00004000
+#define MACC_PROMISC_EN 0x00008000
+#define MACC_DBG_TX_BKPRESSURE 0x00100000
+#define MACC_ALLMULTI_EN 0x02000000
+#define MACC_BCAST_EN 0x04000000
+#define MACC_MACLP_CLK_PHY 0x08000000
+#define MACC_HDX_LEFT_BUF_MASK 0x0f
+#define MACC_HDX_LEFT_BUF_SHIFT 28
+
+/* MAC IPG/IFG Control register */
+#define ATL2_MIPFG 0x1484
+#define MIPFG_IPGT_MASK 0x0000007f
+#define MIPFG_IPGT_SHIFT 0
+#define MIPFG_MIFG_MASK 0xff
+#define MIPFG_MIFG_SHIFT 8
+#define MIPFG_IPGR1_MASK 0x7f
+#define MIPFG_IPGR1_SHIFT 16
+#define MIPFG_IPGR2_MASK 0x7f
+#define MIPFG_IPGR2_SHIFT 24
+
+/* MAC Address registers */
+#define ATL2_MAC_ADDR_0 0x1488
+#define ATL2_MAC_ADDR_1 0x148c
+
+/* Multicast Hash Table register */
+#define ATL2_MHT 0x1490
+
+/* MAC Half-Duplex Control register */
+#define ATL2_MHDC 0x1498
+#define MHDC_LCOL_MASK 0x000003ff
+#define MHDC_LCOL_SHIFT 0
+#define MHDC_RETRY_MASK 0x0f
+#define MHDC_RETRY_SHIFT 12
+#define MHDC_EXC_DEF_EN 0x00010000
+#define MHDC_NO_BACK_C 0x00020000
+#define MHDC_NO_BACK_P 0x00040000
+#define MHDC_ABEDE 0x00080000
+#define MHDC_ABEBT_MASK 0x0f
+#define MHDC_ABEBT_SHIFT 20
+#define MHDC_JAMIPG_MASK 0x0f
+#define MHDC_JAMIPG_SHIFT 24
+
+/* MTU Control register */
+#define ATL2_MTU 0x149c
+
+/* WOL Control register */
+#define ATL2_WOLC
+#define WOLC_PATTERN_EN 0x00000001
+#define WOLC_PATTERN_PME_EN 0x00000002
+#define WOLC_MAGIC_EN 0x00000004
+#define WOLC_MAGIC_PME_EN 0x00000008
+#define WOLC_LINK_CHG_EN 0x00000010
+#define WOLC_LINK_CHG_PME_EN 0x00000020
+#define WOLC_PATTERN_ST 0x00000100
+#define WOLC_MAGIC_ST 0x00000200
+#define WOLC_LINK_CHG_ST 0x00000400
+#define WOLC_PT0_EN 0x00010000
+#define WOLC_PT1_EN 0x00020000
+#define WOLC_PT2_EN 0x00040000
+#define WOLC_PT3_EN 0x00080000
+#define WOLC_PT4_EN 0x00100000
+#define WOLC_PT0_MATCH 0x01000000
+#define WOLC_PT1_MATCH 0x02000000
+#define WOLC_PT2_MATCH 0x04000000
+#define WOLC_PT3_MATCH 0x08000000
+#define WOLC_PT4_MATCH 0x10000000
+
+/* Internal SRAM Partition register */
+#define ATL2_SRAM_TXRAM_END 0x1500
+#define ATL2_SRAM_RXRAM_END 0x1502
+
+/* Descriptor Control registers */
+#define ATL2_DESC_BASE_ADDR_HI 0x1540
+#define ATL2_TXD_BASE_ADDR_LO 0x1544
+#define ATL2_TXD_BUFFER_SIZE 0x1548
+#define ATL2_TXS_BASE_ADDR_LO 0x154c
+#define ATL2_TXS_NUM_ENTRIES 0x1550
+#define ATL2_RXD_BASE_ADDR_LO 0x1554
+#define ATL2_RXD_NUM_ENTRIES 0x1558
+
+/* DMAR Control register */
+#define ATL2_DMAR 0x1580
+#define DMAR_EN 0x01
+
+/* TX Cur-Through Control register */
+#define ATL2_TX_CUT_THRESH 0x1590
+
+/* DMAW Control register */
+#define ATL2_DMAW 0x15a0
+#define DMAW_EN 0x01
+
+/* Flow Control registers */
+#define ATL2_PAUSE_ON_TH 0x15a8
+#define ATL2_PAUSE_OFF_TH 0x15aa
+
+/* Mailbox registers */
+#define ATL2_MB_TXD_WR_IDX 0x15f0
+#define ATL2_MB_RXD_RD_IDX 0x15f4
+
+/* Interrupt Status register */
+#define ATL2_ISR 0x1600
+#define ISR_TIMER 0x00000001
+#define ISR_MANUAL 0x00000002
+#define ISR_RXF_OV 0x00000004
+#define ISR_TXF_UR 0x00000008
+#define ISR_TXS_OV 0x00000010
+#define ISR_RXS_OV 0x00000020
+#define ISR_LINK_CHG 0x00000040
+#define ISR_HOST_TXD_UR 0x00000080
+#define ISR_HOST_RXD_OV 0x00000100
+#define ISR_DMAR_TO_RST 0x00000200
+#define ISR_DMAW_TO_RST 0x00000400
+#define ISR_PHY 0x00000800
+#define ISR_TS_UPDATE 0x00010000
+#define ISR_RS_UPDATE 0x00020000
+#define ISR_TX_EARLY 0x00040000
+#define ISR_UR_DETECTED 0x01000000
+#define ISR_FERR_DETECTED 0x02000000
+#define ISR_NFERR_DETECTED 0x04000000
+#define ISR_CERR_DETECTED 0x08000000
+#define ISR_PHY_LINKDOWN 0x10000000
+#define ISR_DIS_INT 0x80000000
+
+#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \
+ ISR_HOST_TXD_UR | ISR_TS_UPDATE | \
+ ISR_TX_EARLY)
+#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \
+ ISR_HOST_RXD_OV | ISR_RS_UPDATE)
+
+/* Interrupt Mask register */
+#define ATL2_IMR 0x1604
+#define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \
+ ISR_PHY | ISR_PHY_LINKDOWN | \
+ ISR_TS_UPDATE | ISR_RS_UPDATE | \
+ ISR_MANUAL)
+
+/* MAC RX Statistics registers */
+#define ATL2_STS_RX_PAUSE 0x1700
+#define ATL2_STS_RXD_OV 0x1704
+#define ATL2_STS_RXS_OV 0x1708
+#define ATL2_STS_RX_FILTER 0x170c
+
+struct tx_pkt_header {
+ uint16_t txph_size;
+#define ATL2_TXH_ADD_VLAN_TAG 0x8000
+ uint16_t txph_vlan;
+} __packed;
+
+struct tx_pkt_status {
+ uint16_t txps_size;
+ uint16_t txps_flags :15;
+#define ATL2_TXF_SUCCESS 0x0001
+#define ATL2_TXF_BCAST 0x0002
+#define ATL2_TXF_MCAST 0x0004
+#define ATL2_TXF_PAUSE 0x0008
+#define ATL2_TXF_CTRL 0x0010
+#define ATL2_TXF_DEFER 0x0020
+#define ATL2_TXF_EXC_DEFER 0x0040
+#define ATL2_TXF_SINGLE_COL 0x0080
+#define ATL2_TXF_MULTI_COL 0x0100
+#define ATL2_TXF_LATE_COL 0x0200
+#define ATL2_TXF_ABORT_COL 0x0400
+#define ATL2_TXF_UNDERRUN 0x0800
+ uint16_t txps_update:1;
+} __packed;
+
+struct rx_pkt {
+ uint16_t rxp_size;
+ uint16_t rxp_flags :15;
+#define ATL2_RXF_SUCCESS 0x0001
+#define ATL2_RXF_BCAST 0x0002
+#define ATL2_RXF_MCAST 0x0004
+#define ATL2_RXF_PAUSE 0x0008
+#define ATL2_RXF_CTRL 0x0010
+#define ATL2_RXF_CRC 0x0020
+#define ATL2_RXF_CODE 0x0040
+#define ATL2_RXF_RUNT 0x0080
+#define ATL2_RXF_FRAG 0x0100
+#define ATL2_RXF_TRUNC 0x0200
+#define ATL2_RXF_ALIGN 0x0400
+#define ATL2_RXF_VLAN 0x0800
+ uint16_t rxp_update:1;
+ uint16_t rxp_vlan;
+ uint16_t __pad;
+ uint8_t rxp_data[1528];
+} __packed;
Index: sys/dev/pci/files.pci
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/files.pci,v
retrieving revision 1.273.2.4
diff -u -r1.273.2.4 files.pci
--- sys/dev/pci/files.pci 11 Jan 2008 17:03:16 -0000 1.273.2.4
+++ sys/dev/pci/files.pci 17 Apr 2008 14:49:03 -0000
@@ -875,3 +875,8 @@
device msk: ether, ifnet, arp, mii
attach msk at mskc
file dev/pci/if_msk.c mskc | msk
+
+# Atheros/Attansic L2 Fast-Ethernet
+device lii: ether, ifnet, arp, mii
+attach lii at pci
+file dev/pci/if_lii.c lii
Index: sys/dev/pci/pcidevs
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs,v
retrieving revision 1.855.2.20
diff -u -r1.855.2.20 pcidevs
--- sys/dev/pci/pcidevs 9 Mar 2008 11:03:05 -0000 1.855.2.20
+++ sys/dev/pci/pcidevs 17 Apr 2008 14:50:35 -0000
@@ -600,6 +600,7 @@
vendor S2IO 0x17d5 S2io Technologies
vendor LINKSYS2 0x17fe Linksys
vendor RALINK 0x1814 Ralink Technologies
+vendor ATTANSIC 0x1969 Attansic Technologies
vendor SYMPHONY2 0x1c1c Symphony Labs (2nd PCI Vendor ID)
vendor TEKRAM2 0x1de1 Tekram Technology (2nd PCI Vendor ID)
vendor DATUM 0x12e2 Datum Inc. Bancomm-Timing Division
@@ -1012,6 +1013,10 @@
/* Asustek products */
product ASUSTEK HFCPCI 0x0675 ISDN
+/* Attansic Technology Corp. */
+product ATTANSIC ETHERNET_GIGA 0x1048 L1 Gigabit Ethernet Adapter
+product ATTANSIC ETHERNET_100 0x2048 L2 100 Mbit Ethernet Adapter
+
/* ATI products */
product ATI RADEON_RV380_3150 0x3150 Radeon Mobility X600 (M24) 3150
product ATI RADEON_RV380_3154 0x3154 FireGL M24 GL 3154
Index: sys/dev/pci/pcidevs.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.854.2.20
diff -u -r1.854.2.20 pcidevs.h
--- sys/dev/pci/pcidevs.h 9 Mar 2008 11:05:04 -0000 1.854.2.20
+++ sys/dev/pci/pcidevs.h 17 Apr 2008 14:50:37 -0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs.h,v 1.854.2.20 2008/03/09 11:05:04 bouyer Exp $ */
+/* $NetBSD$ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD
+ * NetBSD: pcidevs,v 1.855.2.20 2008/03/09 11:03:05 bouyer Exp
*/
/*
@@ -607,6 +607,7 @@
#define PCI_VENDOR_S2IO 0x17d5 /* S2io Technologies */
#define PCI_VENDOR_LINKSYS2 0x17fe /* Linksys */
#define PCI_VENDOR_RALINK 0x1814 /* Ralink Technologies */
+#define PCI_VENDOR_ATTANSIC 0x1969 /* Attansic Technologies */
#define PCI_VENDOR_SYMPHONY2 0x1c1c /* Symphony Labs (2nd PCI Vendor ID) */
#define PCI_VENDOR_TEKRAM2 0x1de1 /* Tekram Technology (2nd PCI Vendor ID) */
#define PCI_VENDOR_DATUM 0x12e2 /* Datum Inc. Bancomm-Timing Division */
@@ -1019,6 +1020,10 @@
/* Asustek products */
#define PCI_PRODUCT_ASUSTEK_HFCPCI 0x0675 /* ISDN */
+/* Attansic Technology Corp. */
+#define PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA 0x1048 /* L1 Gigabit Ethernet Adapter */
+#define PCI_PRODUCT_ATTANSIC_ETHERNET_100 0x2048 /* L2 100 Mbit Ethernet Adapter */
+
/* ATI products */
#define PCI_PRODUCT_ATI_RADEON_RV380_3150 0x3150 /* Radeon Mobility X600 (M24) 3150 */
#define PCI_PRODUCT_ATI_RADEON_RV380_3154 0x3154 /* FireGL M24 GL 3154 */
Index: sys/dev/pci/pcidevs_data.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.853.2.20
diff -u -r1.853.2.20 pcidevs_data.h
--- sys/dev/pci/pcidevs_data.h 9 Mar 2008 11:05:04 -0000 1.853.2.20
+++ sys/dev/pci/pcidevs_data.h 17 Apr 2008 14:50:42 -0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs_data.h,v 1.853.2.20 2008/03/09 11:05:04 bouyer Exp $ */
+/* $NetBSD$ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD
+ * NetBSD: pcidevs,v 1.855.2.20 2008/03/09 11:03:05 bouyer Exp
*/
/*
@@ -2240,6 +2240,10 @@
"Ralink Technologies",
},
{
+ PCI_VENDOR_ATTANSIC,
+ "Attansic Technologies",
+ },
+ {
PCI_VENDOR_SYMPHONY2,
"Symphony Labs (2nd PCI Vendor ID)",
},
@@ -2380,7 +2384,7 @@
"INVALID VENDOR ID",
},
};
-const int pci_nvendors = 585;
+const int pci_nvendors = 586;
static const struct pci_product pci_products[] = {
{
@@ -3640,6 +3644,14 @@
"ISDN",
},
{
+ PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA,
+ "L1 Gigabit Ethernet Adapter",
+ },
+ {
+ PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_ETHERNET_100,
+ "L2 100 Mbit Ethernet Adapter",
+ },
+ {
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RV380_3150,
"Radeon Mobility X600 (M24) 3150",
},
@@ -13140,4 +13152,4 @@
"Video Controller",
},
};
-const int pci_nproducts = 2689;
+const int pci_nproducts = 2691;
Index: sys/dev/DEVNAMES
===================================================================
RCS file: /cvsroot/src/sys/dev/DEVNAMES,v
retrieving revision 1.222.2.1
diff -u -r1.222.2.1 DEVNAMES
--- sys/dev/DEVNAMES 19 Dec 2007 19:38:53 -0000 1.222.2.1
+++ sys/dev/DEVNAMES 17 Apr 2008 15:22:31 -0000
@@ -712,6 +712,7 @@
ledma MI
leo atari
lfmiop MI
+lii MI
lkkbd alpha
lkkbd vax
lkms vax
Index: sys/arch/i386/conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/i386/conf/GENERIC,v
retrieving revision 1.799.2.16
diff -u -r1.799.2.16 GENERIC
--- sys/arch/i386/conf/GENERIC 11 Jan 2008 17:03:17 -0000 1.799.2.16
+++ sys/arch/i386/conf/GENERIC 17 Apr 2008 15:27:04 -0000
@@ -853,6 +853,7 @@
ipw* at pci? dev ? function ? # Intel PRO/Wireless 2100
iwi* at pci? dev ? function ? # Intel PRO/Wireless 2200BG
le* at pci? dev ? function ? # PCnet-PCI Ethernet
+lii* at pci? dev ? function ? # Atheros L2 Fast-Ethernet
lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3
mskc* at pci? dev ? function ? # Marvell Yukon 2 Gigabit Ethernet
msk* at mskc? # Marvell Yukon 2 Gigabit Ethernet
Index: sys/arch/i386/conf/ALL
===================================================================
RCS file: /cvsroot/src/sys/arch/i386/conf/ALL,v
retrieving revision 1.73.2.9
diff -u -r1.73.2.9 ALL
--- sys/arch/i386/conf/ALL 27 Sep 2007 22:04:27 -0000 1.73.2.9
+++ sys/arch/i386/conf/ALL 17 Apr 2008 15:27:05 -0000
@@ -843,6 +843,7 @@
ipw* at pci? dev ? function ? # Intel PRO/Wireless 2100
iwi* at pci? dev ? function ? # Intel PRO/Wireless 2200BG
le* at pci? dev ? function ? # PCnet-PCI Ethernet
+lii* at pci? dev ? function ? # Atheros L2 Fast-Ethernet
lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3
mskc* at pci? dev ? function ? # Marvell Yukon 2 Gigabit Ethernet
msk* at mskc? # Marvell Yukon 2 Gigabit Ethernet
Index: sys/arch/i386/conf/XEN2_DOM0
===================================================================
RCS file: /cvsroot/src/sys/arch/i386/conf/XEN2_DOM0,v
retrieving revision 1.18.2.6
diff -u -r1.18.2.6 XEN2_DOM0
--- sys/arch/i386/conf/XEN2_DOM0 11 Jan 2008 17:03:18 -0000 1.18.2.6
+++ sys/arch/i386/conf/XEN2_DOM0 17 Apr 2008 15:27:05 -0000
@@ -278,6 +278,7 @@
ipw* at pci? dev ? function ? # Intel PRO/Wireless 2100
iwi* at pci? dev ? function ? # Intel PRO/Wireless 2200BG
le* at pci? dev ? function ? # PCnet-PCI Ethernet
+lii* at pci? dev ? function ? # Atheros L2 Fast-Ethernet
lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3
mskc* at pci? dev ? function ? # Marvell Yukon 2 Gigabit Ethernet
msk* at mskc? # Marvell Yukon 2 Gigabit Ethernet
Index: sys/arch/i386/conf/INSTALL
===================================================================
RCS file: /cvsroot/src/sys/arch/i386/conf/INSTALL,v
retrieving revision 1.297.2.5
diff -u -r1.297.2.5 INSTALL
--- sys/arch/i386/conf/INSTALL 9 May 2007 22:52:25 -0000 1.297.2.5
+++ sys/arch/i386/conf/INSTALL 17 Apr 2008 15:27:05 -0000
@@ -525,6 +525,7 @@
#ipw* at pci? dev ? function ? # Intel PRO/Wireless 2100
#iwi* at pci? dev ? function ? # Intel PRO/Wireless 2200BG
#le* at pci? dev ? function ? # PCnet-PCI Ethernet
+lii* at pci? dev ? function ? # Atheros L2 Fast-Ethernet
#lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3
mskc* at pci? dev ? function ? # Marvell Yukon 2 Gigabit Ethernet
msk* at mskc? # Marvell Yukon 2 Gigabit Ethernet
Index: distrib/sets/lists/man/mi
===================================================================
RCS file: /cvsroot/src/distrib/sets/lists/man/mi,v
retrieving revision 1.955.2.19
diff -u -r1.955.2.19 mi
--- distrib/sets/lists/man/mi 24 Mar 2008 20:22:37 -0000 1.955.2.19
+++ distrib/sets/lists/man/mi 17 Apr 2008 15:34:27 -0000
@@ -1038,6 +1038,7 @@
./usr/share/man/cat4/lc.0 man-sys-catman .cat
./usr/share/man/cat4/ld.0 man-sys-catman .cat
./usr/share/man/cat4/le.0 man-sys-catman .cat
+./usr/share/man/cat4/lii.0 man-sys-catman .cat
./usr/share/man/cat4/lkm.0 man-sys-catman .cat
./usr/share/man/cat4/lm.0 man-sys-catman .cat
./usr/share/man/cat4/lmc.0 man-sys-catman .cat
@@ -3455,6 +3456,7 @@
./usr/share/man/man4/ld.4 man-sys-man .man
./usr/share/man/man4/le.4 man-sys-man .man
./usr/share/man/man4/lkm.4 man-sys-man .man
+./usr/share/man/man4/lii.4 man-sys-man .man
./usr/share/man/man4/lm.4 man-sys-man .man
./usr/share/man/man4/lmc.4 man-sys-man .man
./usr/share/man/man4/lmtemp.4 man-sys-man .man
Index: share/man/man4/Makefile
===================================================================
RCS file: /cvsroot/src/share/man/man4/Makefile,v
retrieving revision 1.415.2.9
diff -u -r1.415.2.9 Makefile
--- share/man/man4/Makefile 11 Jan 2008 17:03:20 -0000 1.415.2.9
+++ share/man/man4/Makefile 17 Apr 2008 15:34:31 -0000
@@ -23,7 +23,7 @@
igsfb.4 iha.4 inet.4 ikphy.4 inphy.4 intersil7170.4 \
ioasic.4 ioat.4 iop.4 iophy.4 iopsp.4 ip.4 ipkdb.4 ipmi.4 ipw.4 \
iso.4 isp.4 it.4 iteide.4 iwi.4 ixpide.4 jmide.4 joy.4 kloader.4 kse.4 \
- ksyms.4 kttcp.4 lc.4 ld.4 lkm.4 lo.4 lxtphy.4 mainbus.4 makphy.4 \
+ ksyms.4 kttcp.4 lc.4 ld.4 lii.4 lkm.4 lo.4 lxtphy.4 mainbus.4 makphy.4 \
mbe.4 mca.4 mcclock.4 md.4 mfb.4 mfi.4 mhzc.4 midi.4 \
mii.4 mk48txx.4 mlx.4 mly.4 mpt.4 mpu.4 mtd.4 \
mtio.4 multicast.4 ne.4 neo.4 netintro.4 nfe.4 njata.4 njs.4 \
--- /dev/null 2008-04-17 03:39:03.000000000 +0100
+++ share/man/man4/lii.4 2008-03-31 16:03:07.000000000 +0100
@@ -0,0 +1,61 @@
+.\" $NetBSD: lii.4,v 1.1 2008/03/29 01:15:03 mjf Exp $
+.\"
+.\" Copyright (c) 2008 The NetBSD Foundation, Inc.
+.\" All rights reserved.
+.\"
+.\" This code is derived from software contributed to The NetBSD Foundation
+.\" by Matt Fleming.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\" 3. All advertising materials mentioning features or use of this software
+.\" must display the following acknowledgement:
+.\" This product includes software developed by the NetBSD
+.\" Foundation, Inc. and its contributors.
+.\" 4. Neither the name of The NetBSD Foundation nor the names of its
+.\" contributors may be used to endorse or promote products derived
+.\" from this software without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+.\" POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd March 29, 2008
+.Dt LII 4
+.Os
+.Sh NAME
+.Nm lii
+.Nd Attansic/Atheros L2 Fast-Ethernet device driver
+.Sh SYNOPSIS
+.Cd "lii* at pci? dev ? function ?"
+.Sh DESCRIPTION
+The
+.Nm
+provides support for the Attansic/Atheros Fast-Ethernet card.
+This card is found in a variety of low-end Asus hardware, notably the
+Asus EeePC.
+.Sh SEE ALSO
+.Xr mii 4 ,
+.Xr ukphy 4
+.Sh HISTORY
+The
+.Nm
+driver appeared in
+.Nx 5.0 .
+.Sh AUTHORS
+.An Quentin Garnier
+.Aq
[email protected]
