From 827f3463451a763be1d86320c8c6c15b419b276a Mon Sep 17 00:00:00 2001

From 827f3463451a763be1d86320c8c6c15b419b276a Mon Sep 17 00:00:00 2001
From: Arnaud Lacombe <[email protected]>
Date: Wed, 26 May 2010 21:45:02 -0400
Subject: [PATCH 1/6] ath_hal: sync with FreeBSD as of $AFEWDAYSAGO

---
sys/external/isc/atheros_hal/dist/ah.c | 330 ++--
sys/external/isc/atheros_hal/dist/ah.h | 210 +-
sys/external/isc/atheros_hal/dist/ah_desc.h | 4 +-
sys/external/isc/atheros_hal/dist/ah_eeprom.h | 2 +-
sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c | 12 +-
sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c | 21 +-
sys/external/isc/atheros_hal/dist/ah_eeprom_v14.h | 1 +
sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c | 2 +-
sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.c | 404 ++++
sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.h | 155 ++
sys/external/isc/atheros_hal/dist/ah_internal.h | 297 ++--
sys/external/isc/atheros_hal/dist/ah_regdomain.c | 2134 ++++++++------------
sys/external/isc/atheros_hal/dist/ar5210/ar5210.h | 25 +-
.../isc/atheros_hal/dist/ar5210/ar5210_attach.c | 51 +-
.../atheros_hal/dist/ar5210/ar5210_interrupts.c | 6 +-
.../isc/atheros_hal/dist/ar5210/ar5210_misc.c | 9 +-
.../isc/atheros_hal/dist/ar5210/ar5210_phy.c | 32 +-
.../isc/atheros_hal/dist/ar5210/ar5210_reset.c | 88 +-
.../isc/atheros_hal/dist/ar5210/ar5210_xmit.c | 6 +-
.../isc/atheros_hal/dist/ar5210/ar5210phy.h | 2 +-
.../isc/atheros_hal/dist/ar5210/ar5k_0007.ini | 2 +-
sys/external/isc/atheros_hal/dist/ar5211/ar5211.h | 31 +-
.../isc/atheros_hal/dist/ar5211/ar5211_attach.c | 60 +-
.../isc/atheros_hal/dist/ar5211/ar5211_beacon.c | 2 -
.../isc/atheros_hal/dist/ar5211/ar5211_keycache.c | 2 +-
.../isc/atheros_hal/dist/ar5211/ar5211_misc.c | 10 +-
.../isc/atheros_hal/dist/ar5211/ar5211_phy.c | 40 +-
.../isc/atheros_hal/dist/ar5211/ar5211_recv.c | 2 +-
.../isc/atheros_hal/dist/ar5211/ar5211_reset.c | 346 ++--
.../isc/atheros_hal/dist/ar5211/ar5211_xmit.c | 6 +-
.../isc/atheros_hal/dist/ar5211/ar5211phy.h | 2 +-
sys/external/isc/atheros_hal/dist/ar5211/boss.ini | 2 +-
sys/external/isc/atheros_hal/dist/ar5212/ar2316.c | 90 +-
sys/external/isc/atheros_hal/dist/ar5212/ar2317.c | 84 +-
sys/external/isc/atheros_hal/dist/ar5212/ar2413.c | 99 +-
sys/external/isc/atheros_hal/dist/ar5212/ar2425.c | 95 +-
sys/external/isc/atheros_hal/dist/ar5212/ar5111.c | 72 +-
sys/external/isc/atheros_hal/dist/ar5212/ar5112.c | 128 +-
sys/external/isc/atheros_hal/dist/ar5212/ar5212.h | 74 +-
.../isc/atheros_hal/dist/ar5212/ar5212_ani.c | 115 +-
.../isc/atheros_hal/dist/ar5212/ar5212_attach.c | 117 +-
.../isc/atheros_hal/dist/ar5212/ar5212_eeprom.c | 2 +-
.../isc/atheros_hal/dist/ar5212/ar5212_gpio.c | 2 +-
.../atheros_hal/dist/ar5212/ar5212_interrupts.c | 31 +-
.../isc/atheros_hal/dist/ar5212/ar5212_misc.c | 27 +-
.../isc/atheros_hal/dist/ar5212/ar5212_phy.c | 112 +-
.../isc/atheros_hal/dist/ar5212/ar5212_power.c | 4 +-
.../isc/atheros_hal/dist/ar5212/ar5212_recv.c | 14 +-
.../isc/atheros_hal/dist/ar5212/ar5212_reset.c | 637 +++---
.../isc/atheros_hal/dist/ar5212/ar5212_rfgain.c | 25 +-
.../isc/atheros_hal/dist/ar5212/ar5212_xmit.c | 26 +-
.../isc/atheros_hal/dist/ar5212/ar5212phy.h | 2 +-
.../isc/atheros_hal/dist/ar5212/ar5212reg.h | 14 +-
sys/external/isc/atheros_hal/dist/ar5212/ar5413.c | 119 +-
sys/external/isc/atheros_hal/dist/ar5312/ar5312.h | 14 +-
.../isc/atheros_hal/dist/ar5312/ar5312_attach.c | 3 +-
.../isc/atheros_hal/dist/ar5312/ar5312_gpio.c | 4 +-
.../isc/atheros_hal/dist/ar5312/ar5312_misc.c | 2 +-
.../isc/atheros_hal/dist/ar5312/ar5312_reset.c | 164 +-
.../isc/atheros_hal/dist/ar5312/ar5315_gpio.c | 2 +-
sys/external/isc/atheros_hal/dist/ar5416/ar2133.c | 33 +-
sys/external/isc/atheros_hal/dist/ar5416/ar5416.h | 52 +-
.../isc/atheros_hal/dist/ar5416/ar5416.ini | 14 +
.../isc/atheros_hal/dist/ar5416/ar5416_ani.c | 92 +-
.../isc/atheros_hal/dist/ar5416/ar5416_attach.c | 376 ++++-
.../isc/atheros_hal/dist/ar5416/ar5416_cal.c | 81 +-
.../isc/atheros_hal/dist/ar5416/ar5416_cal.h | 11 +-
.../atheros_hal/dist/ar5416/ar5416_cal_adcgain.c | 2 +-
.../isc/atheros_hal/dist/ar5416/ar5416_eeprom.c | 2 +-
.../isc/atheros_hal/dist/ar5416/ar5416_gpio.c | 193 ++-
.../atheros_hal/dist/ar5416/ar5416_interrupts.c | 20 +-
.../isc/atheros_hal/dist/ar5416/ar5416_misc.c | 2 +-
.../isc/atheros_hal/dist/ar5416/ar5416_phy.c | 104 +-
.../isc/atheros_hal/dist/ar5416/ar5416_reset.c | 1147 ++---------
.../isc/atheros_hal/dist/ar5416/ar5416_xmit.c | 11 +-
.../isc/atheros_hal/dist/ar5416/ar5416phy.h | 21 +-
.../isc/atheros_hal/dist/ar5416/ar5416reg.h | 196 ++-
.../isc/atheros_hal/dist/ar5416/ar9160.ini | 16 +-
.../isc/atheros_hal/dist/ar5416/ar9160_attach.c | 36 +-
sys/external/isc/atheros_hal/dist/ar5416/ar9280.c | 361 ++++
sys/external/isc/atheros_hal/dist/ar5416/ar9280.h | 45 +
.../isc/atheros_hal/dist/ar5416/ar9280_attach.c | 736 +++++++
.../isc/atheros_hal/dist/ar5416/ar9280v1.ini | 582 ++++++
.../isc/atheros_hal/dist/ar5416/ar9280v2.ini | 941 +++++++++
sys/external/isc/atheros_hal/dist/ar5416/ar9285.c | 64 +
sys/external/isc/atheros_hal/dist/ar5416/ar9285.h | 43 +
.../isc/atheros_hal/dist/ar5416/ar9285.ini | 699 +++++++
.../isc/atheros_hal/dist/ar5416/ar9285_attach.c | 397 ++++
.../isc/atheros_hal/dist/ar5416/ar9285_reset.c | 951 +++++++++
.../isc/atheros_hal/dist/ar5416/ar9285v2.ini | 746 +++++++
90 files changed, 9960 insertions(+), 4388 deletions(-)
create mode 100644 sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.c
create mode 100644 sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.h
mode change 100755 => 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9160.ini
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9280.c
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9280.h
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9280_attach.c
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9280v1.ini
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9280v2.ini
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9285.c
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9285.h
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9285.ini
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9285_attach.c
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9285_reset.c
create mode 100644 sys/external/isc/atheros_hal/dist/ar5416/ar9285v2.ini

diff --git a/sys/external/isc/atheros_hal/dist/ah.c b/sys/external/isc/atheros_hal/dist/ah.c
index e796843..282723a 100644
--- a/sys/external/isc/atheros_hal/dist/ah.c
+++ b/sys/external/isc/atheros_hal/dist/ah.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -22,6 +22,8 @@
#include "ah_internal.h"
#include "ah_devid.h"

+#include "ar5416/ar5416reg.h" /* NB: includes ar5212reg.h */
+
/* linker set of registered chips */
OS_SET_DECLARE(ah_chips, struct ath_hal_chip);

@@ -78,6 +80,53 @@ ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
return AH_NULL;
}

+const char *
+ath_hal_mac_name(struct ath_hal *ah)
+{
+ switch (ah->ah_macVersion) {
+ case AR_SREV_VERSION_CRETE:
+ case AR_SREV_VERSION_MAUI_1:
+ return "5210";
+ case AR_SREV_VERSION_MAUI_2:
+ case AR_SREV_VERSION_OAHU:
+ return "5211";
+ case AR_SREV_VERSION_VENICE:
+ return "5212";
+ case AR_SREV_VERSION_GRIFFIN:
+ return "2413";
+ case AR_SREV_VERSION_CONDOR:
+ return "5424";
+ case AR_SREV_VERSION_EAGLE:
+ return "5413";
+ case AR_SREV_VERSION_COBRA:
+ return "2415";
+ case AR_SREV_2425:
+ return "2425";
+ case AR_SREV_2417:
+ return "2417";
+ case AR_XSREV_VERSION_OWL_PCI:
+ return "5416";
+ case AR_XSREV_VERSION_OWL_PCIE:
+ return "5418";
+ case AR_XSREV_VERSION_SOWL:
+ return "9160";
+ case AR_XSREV_VERSION_MERLIN:
+ return "9280";
+ case AR_XSREV_VERSION_KITE:
+ return "9285";
+ }
+ return "????";
+}
+
+/*
+ * Return the mask of available modes based on the hardware capabilities.
+ */
+u_int
+ath_hal_getwirelessmodes(struct ath_hal*ah)
+{
+ return ath_hal_getWirelessModes(ah);
+}
+
/* linker set of registered RF backends */
OS_SET_DECLARE(ah_rfs, struct ath_hal_rf);

@@ -88,7 +137,6 @@ OS_SET_DECLARE(ah_rfs, struct ath_hal_rf);
struct ath_hal_rf *
ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)
{
-#ifdef AH_HAS_RF
struct ath_hal_rf * const *prf;

OS_SET_FOREACH(prf, ah_rfs) {
@@ -97,10 +145,51 @@ ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)
return rf;
}
*ecode = HAL_ENOTSUPP;
-#endif
return AH_NULL;
}

+const char *
+ath_hal_rf_name(struct ath_hal *ah)
+{
+ switch (ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+ case 0: /* 5210 */
+ return "5110"; /* NB: made up */
+ case AR_RAD5111_SREV_MAJOR:
+ case AR_RAD5111_SREV_PROD:
+ return "5111";
+ case AR_RAD2111_SREV_MAJOR:
+ return "2111";
+ case AR_RAD5112_SREV_MAJOR:
+ case AR_RAD5112_SREV_2_0:
+ case AR_RAD5112_SREV_2_1:
+ return "5112";
+ case AR_RAD2112_SREV_MAJOR:
+ case AR_RAD2112_SREV_2_0:
+ case AR_RAD2112_SREV_2_1:
+ return "2112";
+ case AR_RAD2413_SREV_MAJOR:
+ return "2413";
+ case AR_RAD5413_SREV_MAJOR:
+ return "5413";
+ case AR_RAD2316_SREV_MAJOR:
+ return "2316";
+ case AR_RAD2317_SREV_MAJOR:
+ return "2317";
+ case AR_RAD5424_SREV_MAJOR:
+ return "5424";
+
+ case AR_RAD5133_SREV_MAJOR:
+ return "5133";
+ case AR_RAD2133_SREV_MAJOR:
+ return "2133";
+ case AR_RAD5122_SREV_MAJOR:
+ return "5122";
+ case AR_RAD2122_SREV_MAJOR:
+ return "2122";
+ }
+ return "????";
+}
+
/*
* Poll the register looking for a specific value.
*/
@@ -154,14 +243,12 @@ ath_hal_computetxtime(struct ath_hal *ah,
kbps = rates->info[rateix].rateKbps;
/*
* index can be invalid duting dynamic Turbo transitions.
+ * XXX
*/
- if(kbps == 0) return 0;
+ if (kbps == 0)
+ return 0;
switch (rates->info[rateix].phy) {
-
case IEEE80211_T_CCK:
-#define CCK_SIFS_TIME 10
-#define CCK_PREAMBLE_BITS 144
-#define CCK_PLCP_BITS 48
phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
if (shortPreamble && rates->info[rateix].shortPreamble)
phyTime >>= 1;
@@ -169,81 +256,46 @@ ath_hal_computetxtime(struct ath_hal *ah,
txTime = CCK_SIFS_TIME + phyTime
+ ((numBits * 1000)/kbps);
break;
-#undef CCK_SIFS_TIME
-#undef CCK_PREAMBLE_BITS
-#undef CCK_PLCP_BITS
-
case IEEE80211_T_OFDM:
-#define OFDM_SIFS_TIME 16
-#define OFDM_PREAMBLE_TIME 20
-#define OFDM_PLCP_BITS 22
-#define OFDM_SYMBOL_TIME 4
-
-#define OFDM_SIFS_TIME_HALF 32
-#define OFDM_PREAMBLE_TIME_HALF 40
-#define OFDM_PLCP_BITS_HALF 22
-#define OFDM_SYMBOL_TIME_HALF 8
-
-#define OFDM_SIFS_TIME_QUARTER 64
-#define OFDM_PREAMBLE_TIME_QUARTER 80
-#define OFDM_PLCP_BITS_QUARTER 22
-#define OFDM_SYMBOL_TIME_QUARTER 16
-
- if (AH_PRIVATE(ah)->ah_curchan &&
- IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
- bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
- HALASSERT(bitsPerSymbol != 0);
-
- numBits = OFDM_PLCP_BITS + (frameLen << 3);
- numSymbols = howmany(numBits, bitsPerSymbol);
- txTime = OFDM_SIFS_TIME_QUARTER
- + OFDM_PREAMBLE_TIME_QUARTER
- + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
- } else if (AH_PRIVATE(ah)->ah_curchan &&
- IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
- bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
- HALASSERT(bitsPerSymbol != 0);
-
- numBits = OFDM_PLCP_BITS + (frameLen << 3);
- numSymbols = howmany(numBits, bitsPerSymbol);
- txTime = OFDM_SIFS_TIME_HALF +
- OFDM_PREAMBLE_TIME_HALF
- + (numSymbols * OFDM_SYMBOL_TIME_HALF);
- } else { /* full rate channel */
- bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
- HALASSERT(bitsPerSymbol != 0);
-
- numBits = OFDM_PLCP_BITS + (frameLen << 3);
- numSymbols = howmany(numBits, bitsPerSymbol);
- txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
- + (numSymbols * OFDM_SYMBOL_TIME);
- }
+ bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
+ HALASSERT(bitsPerSymbol != 0);
+
+ numBits = OFDM_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = OFDM_SIFS_TIME
+ + OFDM_PREAMBLE_TIME
+ + (numSymbols * OFDM_SYMBOL_TIME);
break;
+ case IEEE80211_T_OFDM_HALF:
+ bitsPerSymbol = (kbps * OFDM_HALF_SYMBOL_TIME) / 1000;
+ HALASSERT(bitsPerSymbol != 0);

-#undef OFDM_SIFS_TIME
-#undef OFDM_PREAMBLE_TIME
-#undef OFDM_PLCP_BITS
-#undef OFDM_SYMBOL_TIME
+ numBits = OFDM_HALF_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = OFDM_HALF_SIFS_TIME
+ + OFDM_HALF_PREAMBLE_TIME
+ + (numSymbols * OFDM_HALF_SYMBOL_TIME);
+ break;
+ case IEEE80211_T_OFDM_QUARTER:
+ bitsPerSymbol = (kbps * OFDM_QUARTER_SYMBOL_TIME) / 1000;
+ HALASSERT(bitsPerSymbol != 0);

+ numBits = OFDM_QUARTER_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = OFDM_QUARTER_SIFS_TIME
+ + OFDM_QUARTER_PREAMBLE_TIME
+ + (numSymbols * OFDM_QUARTER_SYMBOL_TIME);
+ break;
case IEEE80211_T_TURBO:
-#define TURBO_SIFS_TIME 8
-#define TURBO_PREAMBLE_TIME 14
-#define TURBO_PLCP_BITS 22
-#define TURBO_SYMBOL_TIME 4
- /* we still save OFDM rates in kbps - so double them */
- bitsPerSymbol = ((kbps << 1) * TURBO_SYMBOL_TIME) / 1000;
+ bitsPerSymbol = (kbps * TURBO_SYMBOL_TIME) / 1000;
HALASSERT(bitsPerSymbol != 0);

- numBits = TURBO_PLCP_BITS + (frameLen << 3);
- numSymbols = howmany(numBits, bitsPerSymbol);
- txTime = TURBO_SIFS_TIME + TURBO_PREAMBLE_TIME
- + (numSymbols * TURBO_SYMBOL_TIME);
+ numBits = TURBO_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = TURBO_SIFS_TIME
+ + TURBO_PREAMBLE_TIME
+ + (numSymbols * TURBO_SYMBOL_TIME);
break;
-#undef TURBO_SIFS_TIME
-#undef TURBO_PREAMBLE_TIME
-#undef TURBO_PLCP_BITS
-#undef TURBO_SYMBOL_TIME
-
default:
HALDEBUG(ah, HAL_DEBUG_PHYIO,
"%s: unknown phy %u (rate ix %u)\n",
@@ -254,71 +306,6 @@ ath_hal_computetxtime(struct ath_hal *ah,
return txTime;
}

-static __inline int
-mapgsm(u_int freq, u_int flags)
-{
- freq *= 10;
- if (flags & CHANNEL_QUARTER)
- freq += 5;
- else if (flags & CHANNEL_HALF)
- freq += 10;
- else
- freq += 20;
- return (freq - 24220) / 5;
-}
-
-static __inline int
-mappsb(u_int freq, u_int flags)
-{
- return ((freq * 10) + (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
-}
-
-/*
- * Convert GHz frequency to IEEE channel number.
- */
-int
-ath_hal_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
-{
- if (flags & CHANNEL_2GHZ) { /* 2GHz band */
- if (freq == 2484)
- return 14;
- if (freq < 2484) {
- if (ath_hal_isgsmsku(ah))
- return mapgsm(freq, flags);
- return ((int)freq - 2407) / 5;
- } else
- return 15 + ((freq - 2512) / 20);
- } else if (flags & CHANNEL_5GHZ) {/* 5Ghz band */
- if (ath_hal_ispublicsafetysku(ah) &&
- IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
- return mappsb(freq, flags);
- } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
- return (freq - 4000) / 5;
- } else {
- return (freq - 5000) / 5;
- }
- } else { /* either, guess */
- if (freq == 2484)
- return 14;
- if (freq < 2484) {
- if (ath_hal_isgsmsku(ah))
- return mapgsm(freq, flags);
- return ((int)freq - 2407) / 5;
- }
- if (freq < 5000) {
- if (ath_hal_ispublicsafetysku(ah) &&
- IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
- return mappsb(freq, flags);
- } else if (freq > 4900) {
- return (freq - 4000) / 5;
- } else {
- return 15 + ((freq - 2512) / 20);
- }
- }
- return (freq - 5000) / 5;
- }
-}
-
typedef enum {
WIRELESS_MODE_11a = 0,
WIRELESS_MODE_TURBO = 1,
@@ -330,15 +317,15 @@ typedef enum {
} WIRELESS_MODE;

static WIRELESS_MODE
-ath_hal_chan2wmode(struct ath_hal *ah, const HAL_CHANNEL *chan)
+ath_hal_chan2wmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
- if (IS_CHAN_CCK(chan))
+ if (IEEE80211_IS_CHAN_B(chan))
return WIRELESS_MODE_11b;
- if (IS_CHAN_G(chan))
+ if (IEEE80211_IS_CHAN_G(chan))
return WIRELESS_MODE_11g;
- if (IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_108G(chan))
return WIRELESS_MODE_108g;
- if (IS_CHAN_TURBO(chan))
+ if (IEEE80211_IS_CHAN_TURBO(chan))
return WIRELESS_MODE_TURBO;
return WIRELESS_MODE_11a;
}
@@ -352,18 +339,14 @@ static const uint8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88 };
u_int
ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
{
- const HAL_CHANNEL *c = (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *c = AH_PRIVATE(ah)->ah_curchan;
u_int clks;

/* NB: ah_curchan may be null when called attach time */
if (c != AH_NULL) {
clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
- if (IS_CHAN_HT40(c))
+ if (IEEE80211_IS_CHAN_HT40(c))
clks <<= 1;
- else if (IS_CHAN_HALF_RATE(c))
- clks >>= 1;
- else if (IS_CHAN_QUARTER_RATE(c))
- clks >>= 2;
} else
clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
return clks;
@@ -372,18 +355,14 @@ ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
u_int
ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
{
- const HAL_CHANNEL *c = (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *c = AH_PRIVATE(ah)->ah_curchan;
u_int usec;

/* NB: ah_curchan may be null when called attach time */
if (c != AH_NULL) {
usec = clks / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
- if (IS_CHAN_HT40(c))
+ if (IEEE80211_IS_CHAN_HT40(c))
usec >>= 1;
- else if (IS_CHAN_HALF_RATE(c))
- usec <<= 1;
- else if (IS_CHAN_QUARTER_RATE(c))
- usec <<= 2;
} else
usec = clks / CLOCK_RATE[WIRELESS_MODE_11b];
return usec;
@@ -507,11 +486,7 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
}
return HAL_ENOTSUPP;
case HAL_CAP_11D:
-#ifdef AH_SUPPORT_11D
return HAL_OK;
-#else
- return HAL_ENOTSUPP;
-#endif
case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
return AH_PRIVATE(ah)->ah_rxornIsFatal ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_HT:
@@ -525,6 +500,11 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
*result = pCap->halTstampPrecision;
return HAL_OK;
+ case HAL_CAP_INTRMASK: /* mask of supported interrupts */
+ *result = pCap->halIntrMask;
+ return HAL_OK;
+ case HAL_CAP_BSSIDMATCH: /* hardware has disable bssid match */
+ return pCap->halBssidMatchSupport ? HAL_OK : HAL_ENOTSUPP;
default:
return HAL_EINVAL;
}
@@ -599,6 +579,15 @@ ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,
}
return (char *) dp - (char *) dstbuf;
}
+
+static void
+ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space)
+{
+ while (space >= sizeof(HAL_REGWRITE)) {
+ OS_REG_WRITE(ah, regs->addr, regs->value);
+ regs++, space -= sizeof(HAL_REGWRITE);
+ }
+}

HAL_BOOL
ath_hal_getdiagstate(struct ath_hal *ah, int request,
@@ -613,6 +602,10 @@ ath_hal_getdiagstate(struct ath_hal *ah, int request,
case HAL_DIAG_REGS:
*resultsize = ath_hal_getregdump(ah, args, *result,*resultsize);
return AH_TRUE;
+ case HAL_DIAG_SETREGS:
+ ath_hal_setregs(ah, args, argsize);
+ *resultsize = 0;
+ return AH_TRUE;
case HAL_DIAG_FATALERR:
*result = &AH_PRIVATE(ah)->ah_fatalState[0];
*resultsize = sizeof(AH_PRIVATE(ah)->ah_fatalState);
@@ -766,7 +759,7 @@ static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93 };
* implement the ah_getChanNoise method.
*/
int16_t
-ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan)
+ath_hal_getChanNoise(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
HAL_CHANNEL_INTERNAL *ichan;

@@ -774,7 +767,7 @@ ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan)
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
return 0;
}
if (ichan->rawNoiseFloor == 0) {
@@ -813,8 +806,8 @@ ath_hal_process_noisefloor(struct ath_hal *ah)
c = &AH_PRIVATE(ah)->ah_channels[i];
if (c->rawNoiseFloor >= 0)
continue;
- mode = ath_hal_chan2wmode(ah, (HAL_CHANNEL *) c);
- HALASSERT(mode < WIRELESS_MODE_MAX);
+ /* XXX can't identify proper mode */
+ mode = IS_CHAN_5GHZ(c) ? WIRELESS_MODE_11a : WIRELESS_MODE_11g;
nf = c->rawNoiseFloor + NOISE_FLOOR[mode] +
ath_hal_getNfAdjust(ah, c);
if (IS_CHAN_5GHZ(c)) {
@@ -840,9 +833,8 @@ ath_hal_process_noisefloor(struct ath_hal *ah)
/* Apply correction factor */
c->noiseFloorAdjust = ath_hal_getNfAdjust(ah, c) +
(IS_CHAN_5GHZ(c) ? correct5 : correct2);
- HALDEBUG(ah, HAL_DEBUG_NFCAL, "%u/0x%x raw nf %d adjust %d\n",
- c->channel, c->channelFlags, c->rawNoiseFloor,
- c->noiseFloorAdjust);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL, "%u raw nf %d adjust %d\n",
+ c->channel, c->rawNoiseFloor, c->noiseFloorAdjust);
}
}

@@ -856,6 +848,7 @@ ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
{
int r;

+ HALASSERT(col < ia->cols);
for (r = 0; r < ia->rows; r++) {
OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0),
HAL_INI_VAL(ia, r, col));
@@ -869,6 +862,7 @@ ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, int col)
{
int r;

+ HALASSERT(col < ia->cols);
for (r = 0; r < ia->rows; r++)
data[r] = HAL_INI_VAL(ia, r, col);
}
diff --git a/sys/external/isc/atheros_hal/dist/ah.h b/sys/external/isc/atheros_hal/dist/ah.h
index 96002ed..7289e13 100644
--- a/sys/external/isc/atheros_hal/dist/ah.h
+++ b/sys/external/isc/atheros_hal/dist/ah.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -63,6 +63,8 @@ typedef enum {
HAL_ENOTSUPP = 13, /* Hardware revision not supported */
HAL_ESELFTEST = 14, /* Hardware self-test failed */
HAL_EINPROGRESS = 15, /* Operation incomplete */
+ HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
+ HAL_EEBADCC = 17, /* EEPROM invalid country code */
} HAL_STATUS;

typedef enum {
@@ -107,6 +109,8 @@ typedef enum {
HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
HAL_CAP_BB_HANG = 35, /* can baseband hang */
HAL_CAP_MAC_HANG = 36, /* can MAC hang */
+ HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */
+ HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */
} HAL_CAPABILITY_TYPE;

/*
@@ -293,6 +297,7 @@ typedef enum {
HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */
HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
+ HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */
} HAL_RX_FILTER;

typedef enum {
@@ -325,13 +330,14 @@ typedef enum {
HAL_INT_RXKCM = 0x00008000,
HAL_INT_SWBA = 0x00010000,
HAL_INT_BMISS = 0x00040000,
- HAL_INT_BNR = 0x00100000, /* Non-common mapping */
+ HAL_INT_BNR = 0x00100000,
HAL_INT_TIM = 0x00200000, /* Non-common mapping */
HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
HAL_INT_GPIO = 0x01000000,
HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
+ HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
HAL_INT_CST = 0x10000000, /* Non-common mapping */
HAL_INT_GTT = 0x20000000, /* Non-common mapping */
HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
@@ -339,87 +345,49 @@ typedef enum {
HAL_INT_BMISC = HAL_INT_TIM
| HAL_INT_DTIM
| HAL_INT_DTIMSYNC
- | HAL_INT_CABEND,
+ | HAL_INT_CABEND
+ | HAL_INT_TBTT,

/* Interrupt bits that map directly to ISR/IMR bits */
HAL_INT_COMMON = HAL_INT_RXNOFRM
| HAL_INT_RXDESC
| HAL_INT_RXEOL
| HAL_INT_RXORN
- | HAL_INT_TXURN
| HAL_INT_TXDESC
+ | HAL_INT_TXURN
| HAL_INT_MIB
| HAL_INT_RXPHY
| HAL_INT_RXKCM
| HAL_INT_SWBA
| HAL_INT_BMISS
+ | HAL_INT_BNR
| HAL_INT_GPIO,
} HAL_INT;

typedef enum {
+ HAL_GPIO_MUX_OUTPUT = 0,
+ HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
+ HAL_GPIO_MUX_PCIE_POWER_LED = 2,
+ HAL_GPIO_MUX_TX_FRAME = 3,
+ HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
+ HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
+ HAL_GPIO_MUX_MAC_POWER_LED = 6
+} HAL_GPIO_MUX_TYPE;
+
+typedef enum {
+ HAL_GPIO_INTR_LOW = 0,
+ HAL_GPIO_INTR_HIGH = 1,
+ HAL_GPIO_INTR_DISABLE = 2
+} HAL_GPIO_INTR_TYPE;
+
+typedef enum {
HAL_RFGAIN_INACTIVE = 0,
HAL_RFGAIN_READ_REQUESTED = 1,
HAL_RFGAIN_NEED_CHANGE = 2
} HAL_RFGAIN;

-/*
- * Channels are specified by frequency.
- */
-typedef struct {
- uint32_t channelFlags; /* see below */
- uint16_t channel; /* setting in Mhz */
- uint8_t privFlags;
- int8_t maxRegTxPower; /* max regulatory tx power in dBm */
- int8_t maxTxPower; /* max true tx power in 0.5 dBm */
- int8_t minTxPower; /* min true tx power in 0.5 dBm */
-} HAL_CHANNEL;
-
-/* channelFlags */
-#define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */
-#define CHANNEL_TURBO 0x00010 /* Turbo Channel */
-#define CHANNEL_CCK 0x00020 /* CCK channel */
-#define CHANNEL_OFDM 0x00040 /* OFDM channel */
-#define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */
-#define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */
-#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */
-#define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */
-#define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */
-#define CHANNEL_HALF 0x04000 /* Half rate channel */
-#define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
-#define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */
-#define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */
-#define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */
-
-/* privFlags */
-#define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference
- used for as AR as well as RADAR
- interference detection */
-#define CHANNEL_DFS 0x02 /* DFS required on channel */
-#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
-#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
-
-#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
-#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
-#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
-#ifdef notdef
-#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
-#else
-#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
-#endif
-#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
-#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_108A CHANNEL_T
-#define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20)
-#define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20)
-#define CHANNEL_G_HT40PLUS (CHANNEL_G|CHANNEL_HT40PLUS)
-#define CHANNEL_G_HT40MINUS (CHANNEL_G|CHANNEL_HT40MINUS)
-#define CHANNEL_A_HT40PLUS (CHANNEL_A|CHANNEL_HT40PLUS)
-#define CHANNEL_A_HT40MINUS (CHANNEL_A|CHANNEL_HT40MINUS)
-#define CHANNEL_ALL \
- (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \
- CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
-#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
+typedef uint16_t HAL_CTRY_CODE; /* country code */
+typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */

#define HAL_ANTENNA_MIN_MODE 0
#define HAL_ANTENNA_FIXED_A 1
@@ -434,14 +402,6 @@ typedef struct {
uint32_t beacons;
} HAL_MIB_STATS;

-typedef uint16_t HAL_CTRY_CODE; /* country code */
-typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
-
-enum {
- CTRY_DEBUG = 0x1ff, /* debug country code */
- CTRY_DEFAULT = 0 /* default country code */
-};
-
enum {
HAL_MODE_11A = 0x001, /* 11a channels */
HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
@@ -471,8 +431,8 @@ typedef struct {
int rateCount; /* NB: for proper padding */
uint8_t rateCodeToIndex[144]; /* back mapping */
struct {
- uint8_t valid; /* valid for rate control use */
- uint8_t phy; /* CCK/OFDM/XR */
+ uint8_t valid; /* valid for rate control use */
+ uint8_t phy; /* CCK/OFDM/XR */
uint32_t rateKbps; /* transfer rate in kbs */
uint8_t rateCode; /* rate for h/w descriptors */
uint8_t shortPreamble; /* mask for enabling short
@@ -630,6 +590,7 @@ typedef struct {
struct ath_desc;
struct ath_tx_status;
struct ath_rx_status;
+struct ieee80211_channel;

/*
* Hardware Access Layer (HAL) API.
@@ -643,8 +604,6 @@ struct ath_rx_status;
*/
struct ath_hal {
uint32_t ah_magic; /* consistency check magic number */
- uint32_t ah_abi; /* HAL ABI version */
-#define HAL_ABI_VERSION 0x08112800 /* YYMMDDnn */
uint16_t ah_devid; /* PCI device ID */
uint16_t ah_subvendorid; /* PCI subvendor ID */
HAL_SOFTC ah_sc; /* back pointer to driver/os state */
@@ -665,17 +624,25 @@ struct ath_hal {

/* Reset functions */
HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
- HAL_CHANNEL *, HAL_BOOL bChannelChange,
- HAL_STATUS *status);
+ struct ieee80211_channel *,
+ HAL_BOOL bChannelChange, HAL_STATUS *status);
HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
+ void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
+ void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
- HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *,
- HAL_BOOL *);
- HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *,
- u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
- HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *);
+ HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
+ struct ieee80211_channel *, HAL_BOOL *);
+ HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
+ struct ieee80211_channel *, u_int chainMask,
+ HAL_BOOL longCal, HAL_BOOL *isCalDone);
+ HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
+ const struct ieee80211_channel *);
+ HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
+ const struct ieee80211_channel *, uint16_t *);
HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
+ HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
+ const struct ieee80211_channel *);

/* Transmit functions */
HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
@@ -735,7 +702,8 @@ struct ath_hal {
struct ath_desc *next, uint64_t tsf,
struct ath_rx_status *);
void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
- const HAL_NODE_STATS *, HAL_CHANNEL *);
+ const HAL_NODE_STATS *,
+ const struct ieee80211_channel *);
void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
const HAL_NODE_STATS *);

@@ -758,7 +726,8 @@ struct ath_hal {
void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
const uint8_t *bssid, uint16_t assocId);
- HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
+ HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
+ uint32_t gpio, HAL_GPIO_MUX_TYPE);
HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
@@ -804,7 +773,8 @@ struct ath_hal {
HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
HAL_POWER_MODE mode, int setChip);
HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
- int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
+ int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
+ const struct ieee80211_channel *);

/* Beacon Management Functions */
void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
@@ -846,54 +816,68 @@ extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);

+extern const char *ath_hal_mac_name(struct ath_hal *);
+extern const char *ath_hal_rf_name(struct ath_hal *);
+
/*
- * Return a list of channels available for use with the hardware.
- * The list is based on what the hardware is capable of, the specified
- * country code, the modeSelect mask, and whether or not outdoor
- * channels are to be permitted.
+ * Regulatory interfaces. Drivers should use ath_hal_init_channels to
+ * request a set of channels for a particular country code and/or
+ * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
+ * this list is constructed according to the contents of the EEPROM.
+ * ath_hal_getchannels acts similarly but does not alter the operating
+ * state; this can be used to collect information for a particular
+ * regulatory configuration. Finally ath_hal_set_channels installs a
+ * channel list constructed outside the driver. The HAL will adopt the
+ * channel list and setup internal state according to the specified
+ * regulatory configuration (e.g. conformance test limits).
*
- * The channel list is returned in the supplied array. maxchans
- * defines the maximum size of this array. nchans contains the actual
- * number of channels returned. If a problem occurred or there were
- * no channels that met the criteria then AH_FALSE is returned.
+ * For all interfaces the channel list is returned in the supplied array.
+ * maxchans defines the maximum size of this array. nchans contains the
+ * actual number of channels returned. If a problem occurred then a
+ * status code != HAL_OK is returned.
*/
-extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
- HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
- uint8_t *regclassids, u_int maxregids, u_int *nregids,
- HAL_CTRY_CODE cc, u_int modeSelect,
- HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
+struct ieee80211_channel;

/*
- * Calibrate noise floor data following a channel scan or similar.
- * This must be called prior retrieving noise floor data.
+ * Return a list of channels according to the specified regulatory.
*/
-extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
+extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
+ struct ieee80211_channel *chans, u_int maxchans, int *nchans,
+ u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
+ HAL_BOOL enableExtendedChannels);

/*
- * Return bit mask of wireless modes supported by the hardware.
+ * Return a list of channels and install it as the current operating
+ * regulatory list.
*/
-extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
+extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
+ struct ieee80211_channel *chans, u_int maxchans, int *nchans,
+ u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
+ HAL_BOOL enableExtendedChannels);

/*
- * Calculate the transmit duration of a frame.
+ * Install the list of channels as the current operating regulatory
+ * and setup related state according to the country code and sku.
*/
-extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
- const HAL_RATE_TABLE *rates, uint32_t frameLen,
- uint16_t rateix, HAL_BOOL shortPreamble);
+extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
+ struct ieee80211_channel *chans, int nchans,
+ HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);

/*
- * Return if device is public safety.
+ * Calibrate noise floor data following a channel scan or similar.
+ * This must be called prior retrieving noise floor data.
*/
-extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
+extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);

/*
- * Return if device is operating in 900 MHz band.
+ * Return bit mask of wireless modes supported by the hardware.
*/
-extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *);
+extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);

/*
- * Convert between IEEE channel number and channel frequency
- * using the specified channel flags; e.g. CHANNEL_2GHZ.
+ * Calculate the transmit duration of a frame.
*/
-extern int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
+extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
+ const HAL_RATE_TABLE *rates, uint32_t frameLen,
+ uint16_t rateix, HAL_BOOL shortPreamble);
#endif /* _ATH_AH_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ah_desc.h b/sys/external/isc/atheros_hal/dist/ah_desc.h
index 79ba953..e0ce58b 100644
--- a/sys/external/isc/atheros_hal/dist/ah_desc.h
+++ b/sys/external/isc/atheros_hal/dist/ah_desc.h
@@ -36,7 +36,6 @@ struct ath_tx_status {
uint16_t ts_tstamp; /* h/w assigned timestamp */
uint8_t ts_status; /* frame status, 0 => xmit ok */
uint8_t ts_rate; /* h/w transmit rate index */
-#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
int8_t ts_rssi; /* tx ack RSSI */
uint8_t ts_shortretry; /* # short retries */
uint8_t ts_longretry; /* # long retries */
@@ -190,6 +189,9 @@ struct ath_desc {
uint32_t ds_ctl0; /* opaque DMA control 0 */
uint32_t ds_ctl1; /* opaque DMA control 1 */
uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
+};
+
+struct ath_desc_status {
union {
struct ath_tx_status tx;/* xmit status */
struct ath_rx_status rx;/* recv status */
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom.h b/sys/external/isc/atheros_hal/dist/ah_eeprom.h
index a1b5984..5e91eb1 100644
--- a/sys/external/isc/atheros_hal/dist/ah_eeprom.h
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom.h
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ah_eeprom.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ * $FreeBSD$
*/
#ifndef _ATH_AH_EEPROM_H_
#define _ATH_AH_EEPROM_H_
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c b/sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c
index 42ca0f7..5e11f1f 100644
--- a/sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c
@@ -112,7 +112,7 @@ ath_hal_v1EepromAttach(struct ath_hal *ah)
{
HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t athvals[AR_EEPROM_ATHEROS_MAX]; /* XXX off stack */
- uint16_t protect, eeprom_version, eeval;
+ uint16_t protect, version, eeval;
uint32_t sum;
int i, loc;

@@ -138,18 +138,18 @@ ath_hal_v1EepromAttach(struct ath_hal *ah)
HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", protect);
/* XXX check proper access before continuing */

- if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &eeprom_version)) {
+ if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &version)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: unable to read EEPROM version\n", __func__);
return HAL_EEREAD;
}
- if (((eeprom_version>>12) & 0xf) != 1) {
+ if (((version>>12) & 0xf) != 1) {
/*
* This code only groks the version 1 EEPROM layout.
*/
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: unsupported EEPROM version 0x%x found\n",
- __func__, eeprom_version);
+ __func__, version);
return HAL_EEVERSION;
}

@@ -183,7 +183,7 @@ ath_hal_v1EepromAttach(struct ath_hal *ah)
return HAL_ENOMEM;
}

- ee->ee_version = eeprom_version;
+ ee->ee_version = version;
ee->ee_protect = protect;
ee->ee_antenna = athvals[2];
ee->ee_biasCurrents = athvals[3];
@@ -243,7 +243,7 @@ ath_hal_v1EepromAttach(struct ath_hal *ah)
}

AH_PRIVATE(ah)->ah_eeprom = ee;
- AH_PRIVATE(ah)->ah_eeversion = eeprom_version;
+ AH_PRIVATE(ah)->ah_eeversion = version;
AH_PRIVATE(ah)->ah_eepromDetach = v1EepromDetach;
AH_PRIVATE(ah)->ah_eepromGet = v1EepromGet;
AH_PRIVATE(ah)->ah_eepromSet = v1EepromSet;
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c b/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c
index c7c2b3c..8793d3b 100644
--- a/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c
@@ -14,9 +14,8 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ah_eeprom_v14.c,v 1.4 2008/12/31 14:08:46 christos Exp $
+ * $FreeBSD$
*/
-#include <sys/endian.h>
#include "opt_ah.h"

#include "ah.h"
@@ -54,8 +53,8 @@ v14EepromGet(struct ath_hal *ah, int param, void *val)
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
__func__, ath_hal_ether_sprintf(macaddr));
return HAL_EEBADMAC;
- } else
- return HAL_OK;
+ }
+ return HAL_OK;
case AR_EEP_REGDMN_0:
return pBase->regDmn[0];
case AR_EEP_REGDMN_1:
@@ -161,20 +160,6 @@ v14EepromDiag(struct ath_hal *ah, int request,
return AH_FALSE;
}

-#if 0
-/* XXX conditionalize by target byte order */
-#ifndef bswap16
-static __inline__ uint16_t
-__bswap16(uint16_t _x)
-{
- return ((uint16_t)(
- (((const uint8_t *)(&_x))[0] ) |
- (((const uint8_t *)(&_x))[1]<< 8))
- );
-}
-#endif
-#endif
-
/* Do structure specific swaps if Eeprom format is non native to host */
static void
eepromSwap(struct ar5416eeprom *ee)
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.h b/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.h
index 7af0f6f..2b3080f 100644
--- a/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.h
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom_v14.h
@@ -76,6 +76,7 @@
#define AR5416_EEPMISC_BIG_ENDIAN 0x01
#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
#define AR5416_MAX_CHAINS 3
+#define AR5416_PWR_TABLE_OFFSET_DB -5
#define AR5416_ANT_16S 25

#define AR5416_NUM_ANT_CHAIN_FIELDS 7
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c b/sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c
index 6974da6..0a06a39 100644
--- a/sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c
@@ -1759,7 +1759,7 @@ legacyEepromDetach(struct ath_hal *ah)
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

if (ee->ee_version >= AR_EEPROM_VER4_0 && ee->ee_eepMap == 1)
- return freeEepromRawPowerCalInfo5112(ah, ee);
+ freeEepromRawPowerCalInfo5112(ah, ee);
ath_hal_free(ee);
AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
}
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.c b/sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.c
new file mode 100644
index 0000000..03bb04c
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2009 Rui Paulo <[email protected]>
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_eeprom_v14.h"
+#include "ah_eeprom_v4k.h"
+
+static HAL_STATUS
+v4kEepromGet(struct ath_hal *ah, int param, void *val)
+{
+#define CHAN_A_IDX 0
+#define CHAN_B_IDX 1
+#define IS_VERS(op, v) ((pBase->version & AR5416_EEP_VER_MINOR_MASK) op (v))
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+ const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader;
+ const BASE_EEP4K_HEADER *pBase = &ee->ee_base.baseEepHeader;
+ uint32_t sum;
+ uint8_t *macaddr;
+ int i;
+
+ switch (param) {
+ case AR_EEP_NFTHRESH_5:
+ *(int16_t *)val = pModal[0].noiseFloorThreshCh[0];
+ return HAL_OK;
+ case AR_EEP_NFTHRESH_2:
+ *(int16_t *)val = pModal[1].noiseFloorThreshCh[0];
+ return HAL_OK;
+ case AR_EEP_MACADDR: /* Get MAC Address */
+ sum = 0;
+ macaddr = val;
+ for (i = 0; i < 6; i++) {
+ macaddr[i] = pBase->macAddr[i];
+ sum += pBase->macAddr[i];
+ }
+ if (sum == 0 || sum == 0xffff*3) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
+ __func__, ath_hal_ether_sprintf(macaddr));
+ return HAL_EEBADMAC;
+ }
+ return HAL_OK;
+ case AR_EEP_REGDMN_0:
+ return pBase->regDmn[0];
+ case AR_EEP_REGDMN_1:
+ return pBase->regDmn[1];
+ case AR_EEP_OPCAP:
+ return pBase->deviceCap;
+ case AR_EEP_OPMODE:
+ return pBase->opCapFlags;
+ case AR_EEP_RFSILENT:
+ return pBase->rfSilent;
+ case AR_EEP_OB_5:
+ return pModal[CHAN_A_IDX].ob;
+ case AR_EEP_DB_5:
+ return pModal[CHAN_A_IDX].db;
+ case AR_EEP_OB_2:
+ return pModal[CHAN_B_IDX].ob;
+ case AR_EEP_DB_2:
+ return pModal[CHAN_B_IDX].db;
+ case AR_EEP_TXMASK:
+ return pBase->txMask;
+ case AR_EEP_RXMASK:
+ return pBase->rxMask;
+ case AR_EEP_RXGAIN_TYPE:
+ return AR5416_EEP_RXGAIN_ORIG;
+ case AR_EEP_TXGAIN_TYPE:
+ return IS_VERS(>=, AR5416_EEP_MINOR_VER_19) ?
+ pBase->txGainType : AR5416_EEP_TXGAIN_ORIG;
+#if 0
+ case AR_EEP_OL_PWRCTRL:
+ HALASSERT(val == AH_NULL);
+ return pBase->openLoopPwrCntl ? HAL_OK : HAL_EIO;
+#endif
+ case AR_EEP_AMODE:
+ HALASSERT(val == AH_NULL);
+ return pBase->opCapFlags & AR5416_OPFLAGS_11A ?
+ HAL_OK : HAL_EIO;
+ case AR_EEP_BMODE:
+ case AR_EEP_GMODE:
+ HALASSERT(val == AH_NULL);
+ return pBase->opCapFlags & AR5416_OPFLAGS_11G ?
+ HAL_OK : HAL_EIO;
+ case AR_EEP_32KHZCRYSTAL:
+ case AR_EEP_COMPRESS:
+ case AR_EEP_FASTFRAME: /* XXX policy decision, h/w can do it */
+ case AR_EEP_WRITEPROTECT: /* NB: no write protect bit */
+ HALASSERT(val == AH_NULL);
+ /* fall thru... */
+ case AR_EEP_MAXQCU: /* NB: not in opCapFlags */
+ case AR_EEP_KCENTRIES: /* NB: not in opCapFlags */
+ return HAL_EIO;
+ case AR_EEP_AES:
+ case AR_EEP_BURST:
+ case AR_EEP_RFKILL:
+ case AR_EEP_TURBO5DISABLE:
+ case AR_EEP_TURBO2DISABLE:
+ HALASSERT(val == AH_NULL);
+ return HAL_OK;
+ case AR_EEP_ANTGAINMAX_2:
+ *(int8_t *) val = ee->ee_antennaGainMax[1];
+ return HAL_OK;
+ case AR_EEP_ANTGAINMAX_5:
+ *(int8_t *) val = ee->ee_antennaGainMax[0];
+ return HAL_OK;
+ default:
+ HALASSERT(0);
+ return HAL_EINVAL;
+ }
+#undef IS_VERS
+#undef CHAN_A_IDX
+#undef CHAN_B_IDX
+}
+
+static HAL_BOOL
+v4kEepromSet(struct ath_hal *ah, int param, int v)
+{
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+ switch (param) {
+ case AR_EEP_ANTGAINMAX_2:
+ ee->ee_antennaGainMax[1] = (int8_t) v;
+ return HAL_OK;
+ case AR_EEP_ANTGAINMAX_5:
+ ee->ee_antennaGainMax[0] = (int8_t) v;
+ return HAL_OK;
+ }
+ return HAL_EINVAL;
+}
+
+static HAL_BOOL
+v4kEepromDiag(struct ath_hal *ah, int request,
+ const void *args, uint32_t argsize, void **result, uint32_t *resultsize)
+{
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+ switch (request) {
+ case HAL_DIAG_EEPROM:
+ *result = &ee->ee_base;
+ *resultsize = sizeof(ee->ee_base);
+ return AH_TRUE;
+ }
+ return AH_FALSE;
+}
+
+/* Do structure specific swaps if Eeprom format is non native to host */
+static void
+eepromSwap(struct ar5416eeprom_4k *ee)
+{
+ uint32_t integer, i;
+ uint16_t word;
+ MODAL_EEP4K_HEADER *pModal;
+
+ /* convert Base Eep header */
+ word = __bswap16(ee->baseEepHeader.length);
+ ee->baseEepHeader.length = word;
+
+ word = __bswap16(ee->baseEepHeader.checksum);
+ ee->baseEepHeader.checksum = word;
+
+ word = __bswap16(ee->baseEepHeader.version);
+ ee->baseEepHeader.version = word;
+
+ word = __bswap16(ee->baseEepHeader.regDmn[0]);
+ ee->baseEepHeader.regDmn[0] = word;
+
+ word = __bswap16(ee->baseEepHeader.regDmn[1]);
+ ee->baseEepHeader.regDmn[1] = word;
+
+ word = __bswap16(ee->baseEepHeader.rfSilent);
+ ee->baseEepHeader.rfSilent = word;
+
+ word = __bswap16(ee->baseEepHeader.blueToothOptions);
+ ee->baseEepHeader.blueToothOptions = word;
+
+ word = __bswap16(ee->baseEepHeader.deviceCap);
+ ee->baseEepHeader.deviceCap = word;
+
+ /* convert Modal Eep header */
+ pModal = &ee->modalHeader;
+
+ /* XXX linux/ah_osdep.h only defines __bswap32 for BE */
+ integer = __bswap32(pModal->antCtrlCommon);
+ pModal->antCtrlCommon = integer;
+
+ for (i = 0; i < AR5416_4K_MAX_CHAINS; i++) {
+ integer = __bswap32(pModal->antCtrlChain[i]);
+ pModal->antCtrlChain[i] = integer;
+ }
+
+ for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+ word = __bswap16(pModal->spurChans[i].spurChan);
+ pModal->spurChans[i].spurChan = word;
+ }
+}
+
+static uint16_t
+v4kEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)
+{
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+ HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS);
+ HALASSERT(is2GHz);
+ return ee->ee_base.modalHeader.spurChans[ix].spurChan;
+}
+
+/**************************************************************************
+ * fbin2freq
+ *
+ * Get channel value from binary representation held in eeprom
+ * RETURNS: the frequency in MHz
+ */
+static uint16_t
+fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
+{
+ /*
+ * Reserved value 0xFF provides an empty definition both as
+ * an fbin and as a frequency - do not convert
+ */
+ if (fbin == AR5416_BCHAN_UNUSED)
+ return fbin;
+ return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
+}
+
+/*
+ * Copy EEPROM Conformance Testing Limits contents
+ * into the allocated space
+ */
+/* USE CTLS from chain zero */
+#define CTL_CHAIN 0
+
+static void
+v4kEepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v4k *ee)
+{
+ RD_EDGES_POWER *rep = ee->ee_rdEdgesPower;
+ int i, j;
+
+ HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES);
+
+ for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_4K_NUM_CTLS; i++) {
+ for (j = 0; j < NUM_EDGES; j ++) {
+ /* XXX Confirm this is the right thing to do when an invalid channel is stored */
+ if (ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel == AR5416_BCHAN_UNUSED) {
+ rep[j].rdEdge = 0;
+ rep[j].twice_rdEdgePower = 0;
+ rep[j].flag = 0;
+ } else {
+ rep[j].rdEdge = fbin2freq(
+ ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel,
+ (ee->ee_base.ctlIndex[i] & CTL_MODE_M) != CTL_11A);
+ rep[j].twice_rdEdgePower = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_POWER);
+ rep[j].flag = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_FLAG) != 0;
+ }
+ }
+ rep += NUM_EDGES;
+ }
+ ee->ee_numCtls = i;
+ HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
+ "%s Numctls = %u\n",__func__,i);
+}
+
+/*
+ * Reclaim any EEPROM-related storage.
+ */
+static void
+v4kEepromDetach(struct ath_hal *ah)
+{
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+ ath_hal_free(ee);
+ AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
+}
+
+#define owl_get_eep_ver(_ee) \
+ (((_ee)->ee_base.baseEepHeader.version >> 12) & 0xF)
+#define owl_get_eep_rev(_ee) \
+ (((_ee)->ee_base.baseEepHeader.version) & 0xFFF)
+
+HAL_STATUS
+ath_hal_v4kEepromAttach(struct ath_hal *ah)
+{
+#define NW(a) (sizeof(a) / sizeof(uint16_t))
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+ uint16_t *eep_data, magic;
+ HAL_BOOL need_swap;
+ u_int w, off, len;
+ uint32_t sum;
+
+ HALASSERT(ee == AH_NULL);
+
+ if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s Error reading Eeprom MAGIC\n", __func__);
+ return HAL_EEREAD;
+ }
+ HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",
+ __func__, magic);
+ if (magic != AR5416_EEPROM_MAGIC) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
+ return HAL_EEMAGIC;
+ }
+
+ ee = ath_hal_malloc(sizeof(HAL_EEPROM_v4k));
+ if (ee == AH_NULL) {
+ /* XXX message */
+ return HAL_ENOMEM;
+ }
+
+ eep_data = (uint16_t *)&ee->ee_base;
+ for (w = 0; w < NW(struct ar5416eeprom_4k); w++) {
+ off = owl_eep_start_loc + w; /* NB: AP71 starts at 0 */
+ if (!ath_hal_eepromRead(ah, off, &eep_data[w])) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s eeprom read error at offset 0x%x\n",
+ __func__, off);
+ return HAL_EEREAD;
+ }
+ }
+ /* Convert to eeprom native eeprom endian format */
+ if (isBigEndian()) {
+ for (w = 0; w < NW(struct ar5416eeprom_4k); w++)
+ eep_data[w] = __bswap16(eep_data[w]);
+ }
+
+ /*
+ * At this point, we're in the native eeprom endian format
+ * Now, determine the eeprom endian by looking at byte 26??
+ */
+ need_swap = ((ee->ee_base.baseEepHeader.eepMisc & AR5416_EEPMISC_BIG_ENDIAN) != 0) ^ isBigEndian();
+ if (need_swap) {
+ HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
+ "Byte swap EEPROM contents.\n");
+ len = __bswap16(ee->ee_base.baseEepHeader.length);
+ } else {
+ len = ee->ee_base.baseEepHeader.length;
+ }
+ len = AH_MIN(len, sizeof(struct ar5416eeprom_4k)) / sizeof(uint16_t);
+
+ /* Apply the checksum, done in native eeprom format */
+ /* XXX - Need to check to make sure checksum calculation is done
+ * in the correct endian format. Right now, it seems it would
+ * cast the raw data to host format and do the calculation, which may
+ * not be correct as the calculation may need to be done in the native
+ * eeprom format
+ */
+ sum = 0;
+ for (w = 0; w < len; w++) {
+ sum ^= eep_data[w];
+ }
+ /* Check CRC - Attach should fail on a bad checksum */
+ if (sum != 0xffff) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "Bad EEPROM checksum 0x%x (Len=%u)\n", sum, len);
+ return HAL_EEBADSUM;
+ }
+
+ if (need_swap)
+ eepromSwap(&ee->ee_base); /* byte swap multi-byte data */
+
+ /* swap words 0+2 so version is at the front */
+ magic = eep_data[0];
+ eep_data[0] = eep_data[2];
+ eep_data[2] = magic;
+
+ HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
+ "%s Eeprom Version %u.%u\n", __func__,
+ owl_get_eep_ver(ee), owl_get_eep_rev(ee));
+
+ /* NB: must be after all byte swapping */
+ if (owl_get_eep_ver(ee) != AR5416_EEP_VER) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "Bad EEPROM version 0x%x\n", owl_get_eep_ver(ee));
+ return HAL_EEBADSUM;
+ }
+
+ v4kEepromReadCTLInfo(ah, ee); /* Get CTLs */
+
+ AH_PRIVATE(ah)->ah_eeprom = ee;
+ AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version;
+ AH_PRIVATE(ah)->ah_eepromDetach = v4kEepromDetach;
+ AH_PRIVATE(ah)->ah_eepromGet = v4kEepromGet;
+ AH_PRIVATE(ah)->ah_eepromSet = v4kEepromSet;
+ AH_PRIVATE(ah)->ah_getSpurChan = v4kEepromGetSpurChan;
+ AH_PRIVATE(ah)->ah_eepromDiag = v4kEepromDiag;
+ return HAL_OK;
+#undef NW
+}
diff --git a/sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.h b/sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.h
new file mode 100644
index 0000000..fd0c699
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ah_eeprom_v4k.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2009 Rui Paulo <[email protected]>
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#ifndef _AH_EEPROM_V4K_H_
+#define _AH_EEPROM_V4K_H_
+
+#include "ah_eeprom.h"
+#include "ah_eeprom_v14.h"
+
+#undef owl_eep_start_loc
+#ifdef __LINUX_ARM_ARCH__ /* AP71 */
+#define owl_eep_start_loc 0
+#else
+#define owl_eep_start_loc 64
+#endif
+
+// 16-bit offset location start of calibration struct
+#define AR5416_4K_EEP_START_LOC 64
+#define AR5416_4K_NUM_2G_CAL_PIERS 3
+#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
+#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3
+#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3
+#define AR5416_4K_NUM_CTLS 12
+#define AR5416_4K_NUM_BAND_EDGES 4
+#define AR5416_4K_NUM_PD_GAINS 2
+#define AR5416_4K_MAX_CHAINS 1
+
+/*
+ * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
+ * and length are swapped). We reverse their position after reading
+ * the data into host memory so the version field is at the same
+ * offset as in previous EEPROM layouts. This makes utilities that
+ * inspect the EEPROM contents work without looking at the PCI device
+ * id which may or may not be reliable.
+ */
+typedef struct BaseEepHeader4k {
+ uint16_t version; /* NB: length in EEPROM */
+ uint16_t checksum;
+ uint16_t length; /* NB: version in EEPROM */
+ uint8_t opCapFlags;
+ uint8_t eepMisc;
+ uint16_t regDmn[2];
+ uint8_t macAddr[6];
+ uint8_t rxMask;
+ uint8_t txMask;
+ uint16_t rfSilent;
+ uint16_t blueToothOptions;
+ uint16_t deviceCap;
+ uint32_t binBuildNumber;
+ uint8_t deviceType;
+ uint8_t txGainType; /* high power tx gain table support */
+} __packed BASE_EEP4K_HEADER; // 32 B
+
+typedef struct ModalEepHeader4k {
+ uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 12
+ uint32_t antCtrlCommon; // 4
+ int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t switchSettling; // 1
+ uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t adcDesiredSize; // 1
+ int8_t pgaDesiredSize; // 1
+ uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t txEndToXpaOff; // 1
+ uint8_t txEndToRxOn; // 1
+ uint8_t txFrameToXpaOn; // 1
+ uint8_t thresh62; // 1
+ uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t xpdGain; // 1
+ uint8_t xpd; // 1
+ int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1
+ int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t pdGainOverlap; // 1
+ uint8_t ob; // 1
+ uint8_t db; // 1
+ uint8_t xpaBiasLvl; // 1
+#if 0
+ uint8_t pwrDecreaseFor2Chain; // 1
+ uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
+#endif
+ uint8_t txFrameToDataStart; // 1
+ uint8_t txFrameToPaOn; // 1
+ uint8_t ht40PowerIncForPdadc; // 1
+ uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t swSettleHt40; // 1
+ uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1
+ uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
+ uint8_t db_ch1; // 1
+ uint8_t flagBits; // 1
+#define AR5416_EEP_FLAG_USEANT1 0x01 /* +1 configured antenna */
+#define AR5416_EEP_FLAG_FORCEXPAON 0x02 /* force XPA bit for 5G */
+#define AR5416_EEP_FLAG_LOCALBIAS 0x04 /* enable local bias */
+#define AR5416_EEP_FLAG_FEMBANDSELECT 0x08 /* FEM band select used */
+#define AR5416_EEP_FLAG_XLNABUFIN 0x10
+#define AR5416_EEP_FLAG_XLNAISEL 0x60
+#define AR5416_EEP_FLAG_XLNAISEL_S 5
+#define AR5416_EEP_FLAG_XLNABUFMODE 0x80
+ uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
+ uint16_t xpaBiasLvlFreq[3]; // 6
+ uint8_t futureModal[2]; // 2
+
+ SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
+} __packed MODAL_EEP4K_HEADER; // == 68 B
+
+typedef struct CalCtlData4k {
+ CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
+} __packed CAL_CTL_DATA_4K;
+
+typedef struct calDataPerFreq4k {
+ uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+ uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+} __packed CAL_DATA_PER_FREQ_4K;
+
+struct ar5416eeprom_4k {
+ BASE_EEP4K_HEADER baseEepHeader; // 32 B
+ uint8_t custData[20]; // 20 B
+ MODAL_EEP4K_HEADER modalHeader; // 68 B
+ uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
+ CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
+ CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
+ CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
+ CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
+ CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
+ uint8_t ctlIndex[AR5416_4K_NUM_CTLS];
+ CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS];
+ uint8_t padding;
+} __packed;
+
+typedef struct {
+ struct ar5416eeprom_4k ee_base;
+#define NUM_EDGES 8
+ uint16_t ee_numCtls;
+ RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
+ /* XXX these are dynamically calculated for use by shared code */
+ int8_t ee_antennaGainMax[2];
+} HAL_EEPROM_v4k;
+#endif /* _AH_EEPROM_V4K_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ah_internal.h b/sys/external/isc/atheros_hal/dist/ah_internal.h
index 09b3b74..882d557 100644
--- a/sys/external/isc/atheros_hal/dist/ah_internal.h
+++ b/sys/external/isc/atheros_hal/dist/ah_internal.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -27,6 +27,8 @@
#define AH_MIN(a,b) ((a)<(b)?(a):(b))
#define AH_MAX(a,b) ((a)>(b)?(a):(b))

+#include <net80211/_ieee80211.h>
+
#ifndef NBBY
#define NBBY 8 /* number of bits/byte */
#endif
@@ -42,21 +44,16 @@
#define offsetof(type, field) ((size_t)(&((type *)0)->field))
#endif

-/*
- * Remove const in a way that keeps the compiler happy.
- * This works for gcc but may require other magic for
- * other compilers (not sure where this should reside).
- * Note that uintptr_t is C99.
- */
-#ifndef __DECONST
-#define __DECONST(type, var) ((type)(unsigned long)(const void *)(var))
-#endif
-
typedef struct {
uint16_t start; /* first register */
uint16_t end; /* ending register or zero */
} HAL_REGRANGE;

+typedef struct {
+ uint32_t addr; /* regiser address/offset */
+ uint32_t value; /* value to write */
+} HAL_REGWRITE;
+
/*
* Transmit power scale factor.
*
@@ -87,12 +84,12 @@ struct ath_hal_chip {
};
#ifndef AH_CHIP
#define AH_CHIP(_name, _probe, _attach) \
-static struct ath_hal_chip name##_chip = { \
+static struct ath_hal_chip _name##_chip = { \
.name = #_name, \
.probe = _probe, \
.attach = _attach \
}; \
-OS_DATA_SET(ah_chips, name##_chip)
+OS_DATA_SET(ah_chips, _name##_chip)
#endif

/*
@@ -118,32 +115,44 @@ OS_DATA_SET(ah_rfs, _name##_rf)
struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);

/*
- * Internal form of a HAL_CHANNEL. Note that the structure
- * must be defined such that you can cast references to a
- * HAL_CHANNEL so don't shuffle the first two members.
+ * Maximum number of internal channels. Entries are per unique
+ * frequency so this might be need to be increased to handle all
+ * usage cases; typically no more than 32 are really needed but
+ * dynamically allocating the data structures is a bit painful
+ * right now.
+ */
+#ifndef AH_MAXCHAN
+#define AH_MAXCHAN 96
+#endif
+
+/*
+ * Internal per-channel state. These are found
+ * using ic_devdata in the ieee80211_channel.
*/
typedef struct {
- uint32_t channelFlags;
- uint16_t channel; /* NB: must be first for casting */
+ uint16_t channel; /* h/w frequency, NB: may be mapped */
uint8_t privFlags;
- int8_t maxRegTxPower;
- int8_t maxTxPower;
- int8_t minTxPower; /* as above... */
-
- HAL_BOOL bssSendHere;
- uint8_t gainI;
- HAL_BOOL iqCalValid;
- uint8_t calValid; /* bitmask of cal types */
+#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
+#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
+#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
+ uint8_t calValid; /* bitmask of cal types */
int8_t iCoff;
int8_t qCoff;
int16_t rawNoiseFloor;
int16_t noiseFloorAdjust;
- int8_t antennaMax;
- uint32_t regDmnFlags; /* Flags for channel use in reg */
- uint32_t conformanceTestLimit; /* conformance test limit from reg domain */
- uint16_t mainSpur; /* cached spur value for this cahnnel */
+ uint16_t mainSpur; /* cached spur value for this channel */
} HAL_CHANNEL_INTERNAL;

+/* channel requires noise floor check */
+#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
+
+/* all full-width channels */
+#define IEEE80211_CHAN_ALLFULL \
+ (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
+#define IEEE80211_CHAN_ALLTURBOFULL \
+ (IEEE80211_CHAN_ALLTURBO - \
+ (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
+
typedef struct {
uint32_t halChanSpreadSupport : 1,
halSleepAfterBeaconBroken : 1,
@@ -184,7 +193,8 @@ typedef struct {
halExtChanDfsSupport : 1,
halForcePpmSupport : 1,
halEnhancedPmSupport : 1,
- halMbssidAggrSupport : 1;
+ halMbssidAggrSupport : 1,
+ halBssidMatchSupport : 1;
uint32_t halWirelessModes;
uint16_t halTotalQueues;
uint16_t halKeyCacheSize;
@@ -197,8 +207,11 @@ typedef struct {
uint8_t halNumGpioPins;
uint8_t halNumAntCfg2GHz;
uint8_t halNumAntCfg5GHz;
+ uint32_t halIntrMask;
} HAL_CAPABILITIES;

+struct regDomain;
+
/*
* The ``private area'' follows immediately after the ``public area''
* in the data structure returned by ath_hal_attach. Private data are
@@ -231,14 +244,8 @@ struct ath_hal_private {
uint16_t *data);
HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
uint16_t data);
- HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
- HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
- uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
- HAL_BOOL (*ah_gpioSet)(struct ath_hal *,
- uint32_t gpio, uint32_t val);
- void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
- HAL_CHANNEL *, uint32_t);
+ struct ieee80211_channel *);
int16_t (*ah_getNfAdjust)(struct ath_hal *,
const HAL_CHANNEL_INTERNAL*);
void (*ah_getNoiseFloor)(struct ath_hal *,
@@ -264,9 +271,10 @@ struct ath_hal_private {
uint16_t ah_phyRev; /* PHY revision */
uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
-
+ uint8_t ah_ispcie; /* PCIE, special treatment */

HAL_OPMODE ah_opmode; /* operating mode from reset */
+ const struct ieee80211_channel *ah_curchan;/* operating channel */
HAL_CAPABILITIES ah_caps; /* device capabilities */
uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
int16_t ah_powerLimit; /* tx power cap */
@@ -277,14 +285,13 @@ struct ath_hal_private {
/*
* State for regulatory domain handling.
*/
- HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */
- HAL_CTRY_CODE ah_countryCode; /* current country code */
- HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */
- u_int ah_nchan; /* valid channels in list */
- HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */
+ HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
+ HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
+ u_int ah_nchan; /* valid items in ah_channels */
+ const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
+ const struct regDomain *ah_rd5GHz; /* reg state for 5G band */

uint8_t ah_coverageClass; /* coverage class */
- HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */
/*
* RF Silent handling; setup according to the EEPROM.
*/
@@ -307,25 +314,33 @@ struct ath_hal_private {
AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
#define ath_hal_eepromWrite(_ah, _off, _data) \
AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
-#define ath_hal_gpioCfgOutput(_ah, _gpio) \
- AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio)
+#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
+ (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
#define ath_hal_gpioCfgInput(_ah, _gpio) \
- AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio)
+ (_ah)->ah_gpioCfgInput(_ah, _gpio)
#define ath_hal_gpioGet(_ah, _gpio) \
- AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio)
+ (_ah)->ah_gpioGet(_ah, _gpio)
#define ath_hal_gpioSet(_ah, _gpio, _val) \
- AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val)
+ (_ah)->ah_gpioSet(_ah, _gpio, _val)
#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
- AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
-#define ath_hal_getpowerlimits(_ah, _chans, _nchan) \
- AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan)
+ (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
+#define ath_hal_getpowerlimits(_ah, _chan) \
+ AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
#define ath_hal_getNfAdjust(_ah, _c) \
AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
#define ath_hal_getNoiseFloor(_ah, _nfArray) \
AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
-
-#define ath_hal_eepromDetach(_ah) \
- AH_PRIVATE(_ah)->ah_eepromDetach(_ah)
+#define ath_hal_configPCIE(_ah, _reset) \
+ (_ah)->ah_configPCIE(_ah, _reset)
+#define ath_hal_disablePCIE(_ah) \
+ (_ah)->ah_disablePCIE(_ah)
+#define ath_hal_setInterrupts(_ah, _mask) \
+ (_ah)->ah_setInterrupts(_ah, _mask)
+
+#define ath_hal_eepromDetach(_ah) do { \
+ if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
+ AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
+} while (0)
#define ath_hal_eepromGet(_ah, _param, _val) \
AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
#define ath_hal_eepromSet(_ah, _param, _val) \
@@ -337,38 +352,22 @@ struct ath_hal_private {
#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)

-#if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
+#ifndef _NET_IF_IEEE80211_H_
/*
* Stuff that would naturally come from _ieee80211.h
*/
#define IEEE80211_ADDR_LEN 6

-#define IEEE80211_WEP_KEYLEN 5 /* 40bit */
#define IEEE80211_WEP_IVLEN 3 /* 24bit */
#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */

#define IEEE80211_CRC_LEN 4

-#define IEEE80211_MTU 1500
#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
(IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
-
-enum {
- IEEE80211_T_DS, /* direct sequence spread spectrum */
- IEEE80211_T_FH, /* frequency hopping */
- IEEE80211_T_OFDM, /* frequency division multiplexing */
- IEEE80211_T_TURBO, /* high rate DS */
- IEEE80211_T_HT, /* HT - full GI */
-};
-#define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */
#endif /* _NET_IF_IEEE80211_H_ */

-/* NB: these are defined privately until XR support is announced */
-enum {
- ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */
-};
-
#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001

#define INIT_AIFS 2
@@ -421,43 +420,11 @@ typedef enum {
#define HAL_BIN_WIDTH_TURBO_100HZ 6250
#define HAL_MAX_BINS_ALLOWED 28

-/*
- * A = 5GHZ|OFDM
- * T = 5GHZ|OFDM|TURBO
- *
- * IS_CHAN_A(T) will return TRUE. This is probably
- * not the default behavior we want. We should migrate to a better mask --
- * perhaps CHANNEL_ALL.
- *
- * For now, IS_CHAN_G() masks itself with CHANNEL_108G.
- *
- */
-
-#define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A)
-#define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
-#define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G)
-#define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
-#define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
-#define IS_CHAN_PUREG(_c) \
- (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
-
-#define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0)
-#define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
-#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
-#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
-#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
-#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
-#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
-#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
+#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
+#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))

#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)

-#define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
-#define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40)
-#define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0)
-#define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20)
-#define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0)
-
/*
* Deduce if the host cpu has big- or litt-endian byte order.
*/
@@ -496,37 +463,6 @@ isBigEndian(void)
#define OS_REG_CLR_BIT(_a, _r, _f) \
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))

-/*
- * Regulatory domain support.
- */
-
-/*
- * Return the max allowed antenna gain based on the current
- * regulatory domain.
- */
-extern u_int ath_hal_getantennareduction(struct ath_hal *,
- HAL_CHANNEL *, u_int twiceGain);
-/*
- * Return the test group for the specific channel based on
- * the current regulator domain.
- */
-extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *);
-/*
- * Return whether or not a noise floor check is required
- * based on the current regulatory domain for the specified
- * channel.
- */
-extern HAL_BOOL ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *);
-
-/*
- * Map a public channel definition to the corresponding
- * internal data structure. This implicitly specifies
- * whether or not the specified channel is ok to use
- * based on the current regulatory domain constraints.
- */
-extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
- const HAL_CHANNEL *);
-
/* system-configurable parameters */
extern int ath_hal_dma_beacon_response_time; /* in TU's */
extern int ath_hal_sw_beacon_response_time; /* in TU's */
@@ -542,7 +478,7 @@ extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
/* printf interfaces */
extern void ath_hal_printf(struct ath_hal *, const char*, ...)
__printflike(2,3);
-extern void ath_hal_vprintf(struct ath_hal *, const char*, va_list)
+extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
__printflike(2, 0);
extern const char* ath_hal_ether_sprintf(const uint8_t *mac);

@@ -585,6 +521,57 @@ extern void ath_hal_assert_failed(const char* filename,
#define HALASSERT(_x)
#endif /* AH_ASSERT */

+/*
+ * Regulatory domain support.
+ */
+
+/*
+ * Return the max allowed antenna gain and apply any regulatory
+ * domain specific changes.
+ */
+u_int ath_hal_getantennareduction(struct ath_hal *ah,
+ const struct ieee80211_channel *chan, u_int twiceGain);
+
+/*
+ * Return the test group for the specific channel based on
+ * the current regulatory setup.
+ */
+u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
+
+/*
+ * Map a public channel definition to the corresponding
+ * internal data structure. This implicitly specifies
+ * whether or not the specified channel is ok to use
+ * based on the current regulatory domain constraints.
+ */
+#ifndef AH_DEBUG
+static OS_INLINE HAL_CHANNEL_INTERNAL *
+ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
+{
+ HAL_CHANNEL_INTERNAL *cc;
+
+ HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
+ cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
+ HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
+ return cc;
+}
+#else
+/* NB: non-inline version that checks state */
+HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
+ const struct ieee80211_channel *);
+#endif /* AH_DEBUG */
+
+/*
+ * Return the h/w frequency for a channel. This may be
+ * different from ic_freq if this is a GSM device that
+ * takes 2.4GHz frequencies and down-converts them.
+ */
+static OS_INLINE uint16_t
+ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
+{
+ return ath_hal_checkchannel(ah, c)->channel;
+}
+
/*
* Convert between microseconds and core system clocks.
*/
@@ -632,16 +619,14 @@ enum {
HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */
HAL_DIAG_EEREAD = 17, /* Read EEPROM word */
HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */
- /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */
- HAL_DIAG_REGREAD = 24, /* Reg reads */
- HAL_DIAG_REGWRITE = 25, /* Reg writes */
- HAL_DIAG_GET_REGBASE = 26, /* Get register base */
+ /* 19-26 removed, do not reuse */
HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */
HAL_DIAG_RDREAD = 28, /* Get regulatory domain */
HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */
HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */
HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */
HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */
+ HAL_DIAG_SETREGS = 33, /* write registers */
};

enum {
@@ -743,7 +728,7 @@ extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
/*
* Common routine for implementing getChanNoise api.
*/
-extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan);
+int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);

/*
* Initialization support.
@@ -793,5 +778,29 @@ extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
const uint32_t data[], int regWr);

+#define CCK_SIFS_TIME 10
+#define CCK_PREAMBLE_BITS 144
+#define CCK_PLCP_BITS 48
+
+#define OFDM_SIFS_TIME 16
+#define OFDM_PREAMBLE_TIME 20
+#define OFDM_PLCP_BITS 22
+#define OFDM_SYMBOL_TIME 4
+
+#define OFDM_HALF_SIFS_TIME 32
+#define OFDM_HALF_PREAMBLE_TIME 40
+#define OFDM_HALF_PLCP_BITS 22
+#define OFDM_HALF_SYMBOL_TIME 8
+
+#define OFDM_QUARTER_SIFS_TIME 64
+#define OFDM_QUARTER_PREAMBLE_TIME 80
+#define OFDM_QUARTER_PLCP_BITS 22
+#define OFDM_QUARTER_SYMBOL_TIME 16
+
+#define TURBO_SIFS_TIME 8
+#define TURBO_PREAMBLE_TIME 14
+#define TURBO_PLCP_BITS 22
+#define TURBO_SYMBOL_TIME 4
+
#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
#endif /* _ATH_AH_INTERAL_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ah_regdomain.c b/sys/external/isc/atheros_hal/dist/ah_regdomain.c
index 0331874..240b757 100644
--- a/sys/external/isc/atheros_hal/dist/ah_regdomain.c
+++ b/sys/external/isc/atheros_hal/dist/ah_regdomain.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2005-2006 Atheros Communications, Inc.
* All rights reserved.
*
@@ -20,6 +20,10 @@
#include "opt_ah.h"

#include "ah.h"
+
+#include <net80211/_ieee80211.h>
+#include <net80211/ieee80211_regdomain.h>
+
#include "ah_internal.h"
#include "ah_eeprom.h"
#include "ah_devid.h"
@@ -34,10 +38,6 @@
#define HAL_MODE_11A_TURBO HAL_MODE_108A
#define HAL_MODE_11G_TURBO HAL_MODE_108G

-/* 10MHz is half the 11A bandwidth used to determine upper edge freq
- of the outdoor channel */
-#define HALF_MAXCHANBW 10
-
/*
* BMLEN defines the size of the bitmask used to hold frequency
* band specifications. Note this must agree with the BM macro
@@ -74,160 +74,11 @@ typedef uint64_t chanbmask_t[BMLEN];
W0(_fg) | W0(_fh) , \
W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \
W1(_fg) | W1(_fh) }
-
-/*
- * Country/Region Codes
- * Numbering from ISO 3166
- */
-enum {
- CTRY_ALBANIA = 8, /* Albania */
- CTRY_ALGERIA = 12, /* Algeria */
- CTRY_ARGENTINA = 32, /* Argentina */
- CTRY_ARMENIA = 51, /* Armenia */
- CTRY_AUSTRALIA = 36, /* Australia */
- CTRY_AUSTRIA = 40, /* Austria */
- CTRY_AZERBAIJAN = 31, /* Azerbaijan */
- CTRY_BAHRAIN = 48, /* Bahrain */
- CTRY_BELARUS = 112, /* Belarus */
- CTRY_BELGIUM = 56, /* Belgium */
- CTRY_BELIZE = 84, /* Belize */
- CTRY_BOLIVIA = 68, /* Bolivia */
- CTRY_BRAZIL = 76, /* Brazil */
- CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
- CTRY_BULGARIA = 100, /* Bulgaria */
- CTRY_CANADA = 124, /* Canada */
- CTRY_CHILE = 152, /* Chile */
- CTRY_CHINA = 156, /* People's Republic of China */
- CTRY_COLOMBIA = 170, /* Colombia */
- CTRY_COSTA_RICA = 188, /* Costa Rica */
- CTRY_CROATIA = 191, /* Croatia */
- CTRY_CYPRUS = 196,
- CTRY_CZECH = 203, /* Czech Republic */
- CTRY_DENMARK = 208, /* Denmark */
- CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
- CTRY_ECUADOR = 218, /* Ecuador */
- CTRY_EGYPT = 818, /* Egypt */
- CTRY_EL_SALVADOR = 222, /* El Salvador */
- CTRY_ESTONIA = 233, /* Estonia */
- CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
- CTRY_FINLAND = 246, /* Finland */
- CTRY_FRANCE = 250, /* France */
- CTRY_FRANCE2 = 255, /* France2 */
- CTRY_GEORGIA = 268, /* Georgia */
- CTRY_GERMANY = 276, /* Germany */
- CTRY_GREECE = 300, /* Greece */
- CTRY_GUATEMALA = 320, /* Guatemala */
- CTRY_HONDURAS = 340, /* Honduras */
- CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
- CTRY_HUNGARY = 348, /* Hungary */
- CTRY_ICELAND = 352, /* Iceland */
- CTRY_INDIA = 356, /* India */
- CTRY_INDONESIA = 360, /* Indonesia */
- CTRY_IRAN = 364, /* Iran */
- CTRY_IRAQ = 368, /* Iraq */
- CTRY_IRELAND = 372, /* Ireland */
- CTRY_ISRAEL = 376, /* Israel */
- CTRY_ITALY = 380, /* Italy */
- CTRY_JAMAICA = 388, /* Jamaica */
- CTRY_JAPAN = 392, /* Japan */
- CTRY_JAPAN1 = 393, /* Japan (JP1) */
- CTRY_JAPAN2 = 394, /* Japan (JP0) */
- CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
- CTRY_JAPAN4 = 396, /* Japan (JE1) */
- CTRY_JAPAN5 = 397, /* Japan (JE2) */
- CTRY_JAPAN6 = 399, /* Japan (JP6) */
-
- CTRY_JAPAN7 = 4007, /* Japan (J7) */
- CTRY_JAPAN8 = 4008, /* Japan (J8) */
- CTRY_JAPAN9 = 4009, /* Japan (J9) */
-
- CTRY_JAPAN10 = 4010, /* Japan (J10) */
- CTRY_JAPAN11 = 4011, /* Japan (J11) */
- CTRY_JAPAN12 = 4012, /* Japan (J12) */
-
- CTRY_JAPAN13 = 4013, /* Japan (J13) */
- CTRY_JAPAN14 = 4014, /* Japan (J14) */
- CTRY_JAPAN15 = 4015, /* Japan (J15) */
-
- CTRY_JAPAN16 = 4016, /* Japan (J16) */
- CTRY_JAPAN17 = 4017, /* Japan (J17) */
- CTRY_JAPAN18 = 4018, /* Japan (J18) */
-
- CTRY_JAPAN19 = 4019, /* Japan (J19) */
- CTRY_JAPAN20 = 4020, /* Japan (J20) */
- CTRY_JAPAN21 = 4021, /* Japan (J21) */
-
- CTRY_JAPAN22 = 4022, /* Japan (J22) */
- CTRY_JAPAN23 = 4023, /* Japan (J23) */
- CTRY_JAPAN24 = 4024, /* Japan (J24) */
-
- CTRY_JORDAN = 400, /* Jordan */
- CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
- CTRY_KENYA = 404, /* Kenya */
- CTRY_KOREA_NORTH = 408, /* North Korea */
- CTRY_KOREA_ROC = 410, /* South Korea */
- CTRY_KOREA_ROC2 = 411, /* South Korea */
- CTRY_KOREA_ROC3 = 412, /* South Korea */
- CTRY_KUWAIT = 414, /* Kuwait */
- CTRY_LATVIA = 428, /* Latvia */
- CTRY_LEBANON = 422, /* Lebanon */
- CTRY_LIBYA = 434, /* Libya */
- CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
- CTRY_LITHUANIA = 440, /* Lithuania */
- CTRY_LUXEMBOURG = 442, /* Luxembourg */
- CTRY_MACAU = 446, /* Macau */
- CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */
- CTRY_MALAYSIA = 458, /* Malaysia */
- CTRY_MALTA = 470, /* Malta */
- CTRY_MEXICO = 484, /* Mexico */
- CTRY_MONACO = 492, /* Principality of Monaco */
- CTRY_MOROCCO = 504, /* Morocco */
- CTRY_NETHERLANDS = 528, /* Netherlands */
- CTRY_NEW_ZEALAND = 554, /* New Zealand */
- CTRY_NICARAGUA = 558, /* Nicaragua */
- CTRY_NORWAY = 578, /* Norway */
- CTRY_OMAN = 512, /* Oman */
- CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
- CTRY_PANAMA = 591, /* Panama */
- CTRY_PARAGUAY = 600, /* Paraguay */
- CTRY_PERU = 604, /* Peru */
- CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
- CTRY_POLAND = 616, /* Poland */
- CTRY_PORTUGAL = 620, /* Portugal */
- CTRY_PUERTO_RICO = 630, /* Puerto Rico */
- CTRY_QATAR = 634, /* Qatar */
- CTRY_ROMANIA = 642, /* Romania */
- CTRY_RUSSIA = 643, /* Russia */
- CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
- CTRY_SINGAPORE = 702, /* Singapore */
- CTRY_SLOVAKIA = 703, /* Slovak Republic */
- CTRY_SLOVENIA = 705, /* Slovenia */
- CTRY_SOUTH_AFRICA = 710, /* South Africa */
- CTRY_SPAIN = 724, /* Spain */
- CTRY_SR9 = 5000, /* Ubiquiti SR9 (900MHz/GSM) */
- CTRY_SWEDEN = 752, /* Sweden */
- CTRY_SWITZERLAND = 756, /* Switzerland */
- CTRY_SYRIA = 760, /* Syria */
- CTRY_TAIWAN = 158, /* Taiwan */
- CTRY_THAILAND = 764, /* Thailand */
- CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
- CTRY_TUNISIA = 788, /* Tunisia */
- CTRY_TURKEY = 792, /* Turkey */
- CTRY_UAE = 784, /* U.A.E. */
- CTRY_UKRAINE = 804, /* Ukraine */
- CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
- CTRY_UNITED_STATES = 840, /* United States */
- CTRY_UNITED_STATES_FCC49 = 842, /* United States (Public Safety)*/
- CTRY_URUGUAY = 858, /* Uruguay */
- CTRY_UZBEKISTAN = 860, /* Uzbekistan */
- CTRY_VENEZUELA = 862, /* Venezuela */
- CTRY_VIET_NAM = 704, /* Viet Nam */
- CTRY_XR9 = 5001, /* Ubiquiti XR9 (900MHz/GSM) */
- CTRY_GZ901 = 5002, /* Zcomax GZ-901 (900MHz/GSM) */
- CTRY_YEMEN = 887, /* Yemen */
- CTRY_ZIMBABWE = 716 /* Zimbabwe */
-};
-
+#define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \
+ { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \
+ W0(_fg) | W0(_fh) | W0(_fi) , \
+ W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \
+ W1(_fg) | W1(_fh) | W1(_fi) }

/*
* Mask to check whether a domain is a multidomain or a single domain
@@ -299,9 +150,9 @@ enum {
APL2_ETSIC = 0x56, /* Venezuela */
APL5_WORLD = 0x58, /* Chile */
APL6_WORLD = 0x5B, /* Singapore */
- APL7_FCCA = 0x5C, /* Taiwan 5.47 Band */
- APL8_WORLD = 0x5D, /* Malaysia 5GHz */
- APL9_WORLD = 0x5E, /* Korea 5GHz */
+ APL7_FCCA = 0x5C, /* Taiwan 5.47 Band */
+ APL8_WORLD = 0x5D, /* Malaysia 5GHz */
+ APL9_WORLD = 0x5E, /* Korea 5GHz */

/*
* World mode SKUs
@@ -319,6 +170,7 @@ enum {

WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */
WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */
+ WORB_WORLD = 0x6B, /* WorldB (WOB SKU) */

MKK3_MKKB = 0x80, /* Japan UNI-1 even + MKKB */
MKK3_MKKA2 = 0x81, /* Japan UNI-1 even + MKKA2 */
@@ -407,9 +259,6 @@ enum {

NULL1 = 0x0198,
WORLD = 0x0199,
- SR9_WORLD = 0x0298,
- XR9_WORLD = 0x0299,
- GZ901_WORLD = 0x029a,
DEBUG_REG_DMN = 0x01ff,
};

@@ -429,12 +278,11 @@ enum { /* conformance test limits */
*/
enum {
NO_REQ = 0x00000000, /* NB: must be zero */
- DISALLOW_ADHOC_11A = 0x00000001,
- DISALLOW_ADHOC_11A_TURB = 0x00000002,
- NEED_NFC = 0x00000004,
- ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */
- ADHOC_NO_11A = 0x00000010,
- LIMIT_FRAME_4MS = 0x00000020, /* 4msec limit on frame length*/
+ DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */
+ DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */
+ NEED_NFC = 0x00000004, /* need noise floor check */
+ ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */
+ LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */
NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */
};

@@ -466,7 +314,7 @@ enum {
* THE following table is the mapping of regdomain pairs specified by
* an 8 bit regdomain value to the individual unitary reg domains
*/
-typedef struct {
+typedef struct regDomainPair {
HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */
HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */
HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */
@@ -486,44 +334,44 @@ typedef struct {
} REG_DMN_PAIR_MAPPING;

static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
- {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
-
- {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
-
- {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
-
- {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
-
- {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
-
- {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+ {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+
+ {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+
+ {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+
+ {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+
+ {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+
+ {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },

{MKK1_MKKA, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN },
{MKK1_MKKB, MKK1, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 },
@@ -536,19 +384,19 @@ static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
{MKK2_MKKA, MKK2, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 },

/* MKK3 */
- {MKK3_MKKA, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, 0 },
+ {MKK3_MKKA, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, CTRY_DEFAULT },
{MKK3_MKKB, MKK3, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 },
- {MKK3_MKKA1, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 },
+ {MKK3_MKKA1, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_DEFAULT },
{MKK3_MKKA2,MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 },
{MKK3_MKKC, MKK3, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 },
- {MKK3_FCCA, MKK3, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, 0 },
+ {MKK3_FCCA, MKK3, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_DEFAULT },

/* MKK4 */
{MKK4_MKKB, MKK4, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 },
- {MKK4_MKKA1, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 },
+ {MKK4_MKKA1, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_DEFAULT },
{MKK4_MKKA2, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 },
{MKK4_MKKC, MKK4, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 },
- {MKK4_FCCA, MKK4, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, 0 },
+ {MKK4_FCCA, MKK4, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_DEFAULT },

/* MKK5 */
{MKK5_MKKB, MKK5, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 },
@@ -570,24 +418,22 @@ static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
{MKK8_MKKA2,MKK8, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 },
{MKK8_MKKC, MKK8, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 },

- {MKK9_MKKA, MKK9, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 },
- {MKK10_MKKA, MKK10, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 },
+ {MKK9_MKKA, MKK9, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_DEFAULT },
+ {MKK10_MKKA, MKK10, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_DEFAULT },

/* These are super domains */
- {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
- {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
- {SR9_WORLD, NULL1, SR9_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_SR9 },
- {XR9_WORLD, NULL1, XR9_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_XR9 },
- {GZ901_WORLD, NULL1, GZ901_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_GZ901 },
+ {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
+ {WORB_WORLD, WORB_WORLD, WORB_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
};

/*
@@ -597,171 +443,152 @@ static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
*/

#define DEF_REGDMN FCC1_FCCA
-#define DEF_DMN_5 FCC1
-#define DEF_DMN_2 FCCA
#define COUNTRY_ERD_FLAG 0x8000
#define WORLDWIDE_ROAMING_FLAG 0x4000
-#define SUPER_DOMAIN_MASK 0x0fff
-#define COUNTRY_CODE_MASK 0x3fff
-
-#define YES AH_TRUE
-#define NO AH_FALSE

typedef struct {
HAL_CTRY_CODE countryCode;
HAL_REG_DOMAIN regDmnEnum;
- HAL_BOOL allow11g;
- HAL_BOOL allow11aTurbo;
- HAL_BOOL allow11gTurbo;
- HAL_BOOL allow11ng20;
- HAL_BOOL allow11ng40;
- HAL_BOOL allow11na20;
- HAL_BOOL allow11na40;
- uint16_t outdoorChanStart;
} COUNTRY_CODE_TO_ENUM_RD;

static COUNTRY_CODE_TO_ENUM_RD allCountries[] = {
- {CTRY_DEBUG, NO_ENUMRD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_DEFAULT, DEF_REGDMN, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_ALBANIA, NULL1_WORLD, YES, NO, YES, YES, NO, NO, NO, 7000 },
- {CTRY_ALGERIA, NULL1_WORLD, YES, NO, YES, YES, NO, NO, NO, 7000 },
- {CTRY_ARGENTINA, APL3_WORLD, NO, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_ARMENIA, ETSI4_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_AUSTRALIA, FCC2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_AUSTRIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_AZERBAIJAN, ETSI4_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_BAHRAIN, APL6_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_BELARUS, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_BELGIUM, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_BELIZE, APL1_ETSIC, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_BOLIVIA, APL1_ETSIC, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_BRAZIL, FCC3_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_BRUNEI_DARUSSALAM,APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_BULGARIA, ETSI6_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_CANADA, FCC2_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_CHILE, APL6_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_CHINA, APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_COLOMBIA, FCC1_FCCA, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_COSTA_RICA, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_CROATIA, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_CYPRUS, ETSI1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_CZECH, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_DENMARK, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_ECUADOR, NULL1_WORLD, NO, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_EGYPT, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_EL_SALVADOR, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_ESTONIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_FINLAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_FRANCE, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_FRANCE2, ETSI3_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_GEORGIA, ETSI4_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_GERMANY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_GREECE, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_GUATEMALA, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_GZ901, GZ901_WORLD, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_HONDURAS, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_HONG_KONG, FCC2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_HUNGARY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_ICELAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_INDIA, APL6_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_INDONESIA, APL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_IRAN, APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_IRELAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_ISRAEL, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_ITALY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_JAPAN, MKK1_MKKA, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_JAPAN1, MKK1_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN2, MKK1_FCCA, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN3, MKK2_MKKA, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN4, MKK1_MKKA1, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN5, MKK1_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN6, MKK1_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JAPAN7, MKK3_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN8, MKK3_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN9, MKK3_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JAPAN10, MKK4_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN11, MKK4_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN12, MKK4_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JAPAN13, MKK5_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN14, MKK5_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN15, MKK5_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JAPAN16, MKK6_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN17, MKK6_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN18, MKK6_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JAPAN19, MKK7_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN20, MKK7_MKKA2, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_JAPAN21, MKK7_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JAPAN22, MKK8_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN23, MKK8_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_JAPAN24, MKK8_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 },
-
- {CTRY_JORDAN, APL4_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_KAZAKHSTAN, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_KOREA_NORTH, APL2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_KOREA_ROC, APL2_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_KOREA_ROC2, APL2_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_KOREA_ROC3, APL9_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_KUWAIT, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_LATVIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_LEBANON, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_LIECHTENSTEIN,ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_LITHUANIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_LUXEMBOURG, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_MACAU, FCC2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_MACEDONIA, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_MALAYSIA, APL8_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 },
- {CTRY_MALTA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_MEXICO, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_MONACO, ETSI4_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_MOROCCO, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_NETHERLANDS, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_NEW_ZEALAND, FCC2_ETSIC, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_NORWAY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_OMAN, APL6_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_PAKISTAN, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_PANAMA, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_PERU, APL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_PHILIPPINES, FCC3_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_POLAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_PORTUGAL, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_PUERTO_RICO, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_QATAR, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_ROMANIA, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_RUSSIA, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_SAUDI_ARABIA,FCC2_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_SINGAPORE, APL6_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_SLOVAKIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_SLOVENIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_SOUTH_AFRICA,FCC3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_SPAIN, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_SR9, SR9_WORLD, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_SWEDEN, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_SWITZERLAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 },
- {CTRY_SYRIA, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_TAIWAN, APL3_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_THAILAND, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_TUNISIA, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_TURKEY, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_UKRAINE, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_UAE, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_UNITED_KINGDOM, ETSI1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_UNITED_STATES, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 5825 },
- {CTRY_UNITED_STATES_FCC49,FCC4_FCCA,YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_URUGUAY, FCC1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_UZBEKISTAN, FCC3_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 },
- {CTRY_VENEZUELA, APL2_ETSIC, YES, NO, YES, YES,YES, YES, NO, 7000 },
- {CTRY_VIET_NAM, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_XR9, XR9_WORLD, YES, NO, NO, NO, NO, NO, NO, 7000 },
- {CTRY_YEMEN, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 },
- {CTRY_ZIMBABWE, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }
+ { CTRY_DEBUG, NO_ENUMRD },
+ { CTRY_DEFAULT, DEF_REGDMN },
+ { CTRY_ALBANIA, NULL1_WORLD },
+ { CTRY_ALGERIA, NULL1_WORLD },
+ { CTRY_ARGENTINA, APL3_WORLD },
+ { CTRY_ARMENIA, ETSI4_WORLD },
+ { CTRY_AUSTRALIA, FCC2_WORLD },
+ { CTRY_AUSTRIA, ETSI1_WORLD },
+ { CTRY_AZERBAIJAN, ETSI4_WORLD },
+ { CTRY_BAHRAIN, APL6_WORLD },
+ { CTRY_BELARUS, NULL1_WORLD },
+ { CTRY_BELGIUM, ETSI1_WORLD },
+ { CTRY_BELIZE, APL1_ETSIC },
+ { CTRY_BOLIVIA, APL1_ETSIC },
+ { CTRY_BRAZIL, FCC3_WORLD },
+ { CTRY_BRUNEI_DARUSSALAM,APL1_WORLD },
+ { CTRY_BULGARIA, ETSI6_WORLD },
+ { CTRY_CANADA, FCC2_FCCA },
+ { CTRY_CHILE, APL6_WORLD },
+ { CTRY_CHINA, APL1_WORLD },
+ { CTRY_COLOMBIA, FCC1_FCCA },
+ { CTRY_COSTA_RICA, NULL1_WORLD },
+ { CTRY_CROATIA, ETSI3_WORLD },
+ { CTRY_CYPRUS, ETSI1_WORLD },
+ { CTRY_CZECH, ETSI1_WORLD },
+ { CTRY_DENMARK, ETSI1_WORLD },
+ { CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA },
+ { CTRY_ECUADOR, NULL1_WORLD },
+ { CTRY_EGYPT, ETSI3_WORLD },
+ { CTRY_EL_SALVADOR, NULL1_WORLD },
+ { CTRY_ESTONIA, ETSI1_WORLD },
+ { CTRY_FINLAND, ETSI1_WORLD },
+ { CTRY_FRANCE, ETSI1_WORLD },
+ { CTRY_FRANCE2, ETSI3_WORLD },
+ { CTRY_GEORGIA, ETSI4_WORLD },
+ { CTRY_GERMANY, ETSI1_WORLD },
+ { CTRY_GREECE, ETSI1_WORLD },
+ { CTRY_GUATEMALA, FCC1_FCCA },
+ { CTRY_HONDURAS, NULL1_WORLD },
+ { CTRY_HONG_KONG, FCC2_WORLD },
+ { CTRY_HUNGARY, ETSI1_WORLD },
+ { CTRY_ICELAND, ETSI1_WORLD },
+ { CTRY_INDIA, APL6_WORLD },
+ { CTRY_INDONESIA, APL1_WORLD },
+ { CTRY_IRAN, APL1_WORLD },
+ { CTRY_IRELAND, ETSI1_WORLD },
+ { CTRY_ISRAEL, NULL1_WORLD },
+ { CTRY_ITALY, ETSI1_WORLD },
+ { CTRY_JAPAN, MKK1_MKKA },
+ { CTRY_JAPAN1, MKK1_MKKB },
+ { CTRY_JAPAN2, MKK1_FCCA },
+ { CTRY_JAPAN3, MKK2_MKKA },
+ { CTRY_JAPAN4, MKK1_MKKA1 },
+ { CTRY_JAPAN5, MKK1_MKKA2 },
+ { CTRY_JAPAN6, MKK1_MKKC },
+
+ { CTRY_JAPAN7, MKK3_MKKB },
+ { CTRY_JAPAN8, MKK3_MKKA2 },
+ { CTRY_JAPAN9, MKK3_MKKC },
+
+ { CTRY_JAPAN10, MKK4_MKKB },
+ { CTRY_JAPAN11, MKK4_MKKA2 },
+ { CTRY_JAPAN12, MKK4_MKKC },
+
+ { CTRY_JAPAN13, MKK5_MKKB },
+ { CTRY_JAPAN14, MKK5_MKKA2 },
+ { CTRY_JAPAN15, MKK5_MKKC },
+
+ { CTRY_JAPAN16, MKK6_MKKB },
+ { CTRY_JAPAN17, MKK6_MKKA2 },
+ { CTRY_JAPAN18, MKK6_MKKC },
+
+ { CTRY_JAPAN19, MKK7_MKKB },
+ { CTRY_JAPAN20, MKK7_MKKA2 },
+ { CTRY_JAPAN21, MKK7_MKKC },
+
+ { CTRY_JAPAN22, MKK8_MKKB },
+ { CTRY_JAPAN23, MKK8_MKKA2 },
+ { CTRY_JAPAN24, MKK8_MKKC },
+
+ { CTRY_JORDAN, APL4_WORLD },
+ { CTRY_KAZAKHSTAN, NULL1_WORLD },
+ { CTRY_KOREA_NORTH, APL2_WORLD },
+ { CTRY_KOREA_ROC, APL2_WORLD },
+ { CTRY_KOREA_ROC2, APL2_WORLD },
+ { CTRY_KOREA_ROC3, APL9_WORLD },
+ { CTRY_KUWAIT, NULL1_WORLD },
+ { CTRY_LATVIA, ETSI1_WORLD },
+ { CTRY_LEBANON, NULL1_WORLD },
+ { CTRY_LIECHTENSTEIN,ETSI1_WORLD },
+ { CTRY_LITHUANIA, ETSI1_WORLD },
+ { CTRY_LUXEMBOURG, ETSI1_WORLD },
+ { CTRY_MACAU, FCC2_WORLD },
+ { CTRY_MACEDONIA, NULL1_WORLD },
+ { CTRY_MALAYSIA, APL8_WORLD },
+ { CTRY_MALTA, ETSI1_WORLD },
+ { CTRY_MEXICO, FCC1_FCCA },
+ { CTRY_MONACO, ETSI4_WORLD },
+ { CTRY_MOROCCO, NULL1_WORLD },
+ { CTRY_NETHERLANDS, ETSI1_WORLD },
+ { CTRY_NEW_ZEALAND, FCC2_ETSIC },
+ { CTRY_NORWAY, ETSI1_WORLD },
+ { CTRY_OMAN, APL6_WORLD },
+ { CTRY_PAKISTAN, NULL1_WORLD },
+ { CTRY_PANAMA, FCC1_FCCA },
+ { CTRY_PERU, APL1_WORLD },
+ { CTRY_PHILIPPINES, FCC3_WORLD },
+ { CTRY_POLAND, ETSI1_WORLD },
+ { CTRY_PORTUGAL, ETSI1_WORLD },
+ { CTRY_PUERTO_RICO, FCC1_FCCA },
+ { CTRY_QATAR, NULL1_WORLD },
+ { CTRY_ROMANIA, NULL1_WORLD },
+ { CTRY_RUSSIA, NULL1_WORLD },
+ { CTRY_SAUDI_ARABIA,FCC2_WORLD },
+ { CTRY_SINGAPORE, APL6_WORLD },
+ { CTRY_SLOVAKIA, ETSI1_WORLD },
+ { CTRY_SLOVENIA, ETSI1_WORLD },
+ { CTRY_SOUTH_AFRICA,FCC3_WORLD },
+ { CTRY_SPAIN, ETSI1_WORLD },
+ { CTRY_SWEDEN, ETSI1_WORLD },
+ { CTRY_SWITZERLAND, ETSI1_WORLD },
+ { CTRY_SYRIA, NULL1_WORLD },
+ { CTRY_TAIWAN, APL3_FCCA },
+ { CTRY_THAILAND, FCC3_WORLD },
+ { CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD },
+ { CTRY_TUNISIA, ETSI3_WORLD },
+ { CTRY_TURKEY, ETSI3_WORLD },
+ { CTRY_UKRAINE, NULL1_WORLD },
+ { CTRY_UAE, NULL1_WORLD },
+ { CTRY_UNITED_KINGDOM, ETSI1_WORLD },
+ { CTRY_UNITED_STATES, FCC1_FCCA },
+ { CTRY_UNITED_STATES_FCC49,FCC4_FCCA },
+ { CTRY_URUGUAY, FCC1_WORLD },
+ { CTRY_UZBEKISTAN, FCC3_FCCA },
+ { CTRY_VENEZUELA, APL2_ETSIC },
+ { CTRY_VIET_NAM, NULL1_WORLD },
+ { CTRY_ZIMBABWE, NULL1_WORLD }
};

/* Bit masks for DFS per regdomain */
@@ -800,136 +627,134 @@ typedef struct {
if corresponding bit is set */
uint64_t usePassScan; /* Use Passive Scan in the RegDomain
if corresponding bit is set */
- uint8_t regClassId; /* Regulatory class id */
} REG_DMN_FREQ_BAND;

/*
* 5GHz 11A channel tags
*/
static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
- { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16 },
+ { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 },
#define F1_4915_4925 0
- { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16 },
+ { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 },
#define F1_4935_4945 AFTER(F1_4915_4925)
- { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7 },
+ { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 },
#define F1_4920_4980 AFTER(F1_4935_4945)
- { 4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC, 0 },
+ { 4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC },
#define F1_4942_4987 AFTER(F1_4920_4980)
- { 4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC, 0 },
+ { 4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC },
#define F1_4945_4985 AFTER(F1_4942_4987)
- { 4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC, 0 },
+ { 4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC },
#define F1_4950_4980 AFTER(F1_4945_4985)
- { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12 },
+ { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 },
#define F1_5035_5040 AFTER(F1_4950_4980)
- { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2 },
+ { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 },
#define F1_5040_5080 AFTER(F1_5035_5040)
- { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12 },
+ { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 },
#define F1_5055_5055 AFTER(F1_5040_5080)

- { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN },
#define F1_5120_5240 AFTER(F1_5055_5055)
- { 5120, 5240, 5, 6, 10, 10, NO_DFS, NO_PSCAN, 0 },
+ { 5120, 5240, 5, 6, 10, 10, NO_DFS, NO_PSCAN },
#define F2_5120_5240 AFTER(F1_5120_5240)
- { 5120, 5240, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0 },
+ { 5120, 5240, 5, 6, 5, 5, NO_DFS, NO_PSCAN },
#define F3_5120_5240 AFTER(F2_5120_5240)

- { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 },
+ { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 },
#define F1_5170_5230 AFTER(F3_5120_5240)
- { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 },
+ { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 },
#define F2_5170_5230 AFTER(F1_5170_5230)

- { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+ { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
#define F1_5180_5240 AFTER(F2_5170_5230)
- { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1 },
+ { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC },
#define F2_5180_5240 AFTER(F1_5180_5240)
- { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+ { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
#define F3_5180_5240 AFTER(F2_5180_5240)
- { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+ { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
#define F4_5180_5240 AFTER(F3_5180_5240)
- { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+ { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
#define F5_5180_5240 AFTER(F4_5180_5240)
- { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0 },
+ { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC },
#define F6_5180_5240 AFTER(F5_5180_5240)
- { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC, 1 },
+ { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC },
#define F7_5180_5240 AFTER(F6_5180_5240)
- { 5180, 5240, 17, 6, 20, 5, NO_DFS, PSCAN_FCC, 1 },
+ { 5180, 5240, 17, 6, 20, 5, NO_DFS, PSCAN_FCC },
#define F8_5180_5240 AFTER(F7_5180_5240)
+ { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },

- { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
#define F1_5180_5320 AFTER(F8_5180_5240)
+ { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI },

- { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0 },
#define F1_5240_5280 AFTER(F1_5180_5320)
+ { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },

- { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
#define F1_5260_5280 AFTER(F1_5240_5280)
+ { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },

- { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
#define F1_5260_5320 AFTER(F1_5260_5280)
-
- { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0 },
+ { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 },
#define F2_5260_5320 AFTER(F1_5260_5320)

- { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+ { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F3_5260_5320 AFTER(F2_5260_5320)
- { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+ { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F4_5260_5320 AFTER(F3_5260_5320)
- { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },
+ { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F5_5260_5320 AFTER(F4_5260_5320)
- { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
#define F6_5260_5320 AFTER(F5_5260_5320)
- { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+ { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F7_5260_5320 AFTER(F6_5260_5320)
- { 5260, 5320, 23, 6, 20, 5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+ { 5260, 5320, 23, 6, 20, 5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F8_5260_5320 AFTER(F7_5260_5320)

- { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
+ { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN },
#define F1_5260_5700 AFTER(F8_5260_5320)
- { 5260, 5700, 5, 6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
+ { 5260, 5700, 5, 6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN },
#define F2_5260_5700 AFTER(F1_5260_5700)
- { 5260, 5700, 5, 6, 5, 5, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
+ { 5260, 5700, 5, 6, 5, 5, DFS_FCC3 | DFS_ETSI, NO_PSCAN },
#define F3_5260_5700 AFTER(F2_5260_5700)

- { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },
+ { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F1_5280_5320 AFTER(F3_5260_5700)

- { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
+ { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },
#define F1_5500_5620 AFTER(F1_5280_5320)

- { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4 },
+ { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
#define F1_5500_5700 AFTER(F1_5500_5620)
- { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
+ { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
#define F2_5500_5700 AFTER(F1_5500_5700)
- { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
+ { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
#define F3_5500_5700 AFTER(F2_5500_5700)
- { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0 },
+ { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC },
#define F4_5500_5700 AFTER(F3_5500_5700)

- { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN },
#define F1_5745_5805 AFTER(F4_5500_5700)
- { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN },
#define F2_5745_5805 AFTER(F1_5745_5805)
- { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
+ { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },
#define F3_5745_5805 AFTER(F2_5745_5805)
- { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN },
#define F1_5745_5825 AFTER(F3_5745_5805)
- { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN },
#define F2_5745_5825 AFTER(F1_5745_5825)
- { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN },
#define F3_5745_5825 AFTER(F2_5745_5825)
- { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
#define F4_5745_5825 AFTER(F3_5745_5825)
- { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3 },
+ { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN },
#define F5_5745_5825 AFTER(F4_5745_5825)
- { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN },
#define F6_5745_5825 AFTER(F5_5745_5825)
- { 5745, 5825, 5, 6, 10, 10, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 5, 6, 10, 10, NO_DFS, NO_PSCAN },
#define F7_5745_5825 AFTER(F6_5745_5825)
- { 5745, 5825, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0 },
+ { 5745, 5825, 5, 6, 5, 5, NO_DFS, NO_PSCAN },
#define F8_5745_5825 AFTER(F7_5745_5825)
- { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN, 3 },
+ { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN },
#define F9_5745_5825 AFTER(F8_5745_5825)
- { 5745, 5825, 30, 6, 20, 5, NO_DFS, NO_PSCAN, 3 },
+ { 5745, 5825, 30, 6, 20, 5, NO_DFS, NO_PSCAN },
#define F10_5745_5825 AFTER(F9_5745_5825)

/*
@@ -937,25 +762,25 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
* All WWR domains have no power limit, instead use the card's CTL
* or max power settings.
*/
- { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+ { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
#define W1_4920_4980 AFTER(F10_5745_5825)
- { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+ { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
#define W1_5040_5080 AFTER(W1_4920_4980)
- { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+ { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define W1_5170_5230 AFTER(W1_5040_5080)
- { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+ { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define W1_5180_5240 AFTER(W1_5170_5230)
- { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+ { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define W1_5260_5320 AFTER(W1_5180_5240)
- { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+ { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
#define W1_5745_5825 AFTER(W1_5260_5320)
- { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+ { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define W1_5500_5700 AFTER(W1_5745_5825)
- { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
#define W2_5260_5320 AFTER(W1_5500_5700)
- { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+ { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
#define W2_5180_5240 AFTER(W2_5260_5320)
- { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+ { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
#define W2_5825_5825 AFTER(W2_5180_5240)
};

@@ -963,66 +788,66 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
* 5GHz Turbo (dynamic & static) tags
*/
static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {
- { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5130_5210 0
- { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+ { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN },
#define T1_5250_5330 AFTER(T1_5130_5210)
- { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5370_5490 AFTER(T1_5250_5330)
- { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+ { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN },
#define T1_5530_5650 AFTER(T1_5370_5490)

- { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5150_5190 AFTER(T1_5530_5650)
- { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+ { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN },
#define T1_5230_5310 AFTER(T1_5150_5190)
- { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5350_5470 AFTER(T1_5230_5310)
- { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+ { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN },
#define T1_5510_5670 AFTER(T1_5350_5470)

- { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5200_5240 AFTER(T1_5510_5670)
- { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T2_5200_5240 AFTER(T1_5200_5240)
- { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5210_5210 AFTER(T2_5200_5240)
- { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN },
#define T2_5210_5210 AFTER(T1_5210_5210)

- { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T1_5280_5280 AFTER(T2_5210_5210)
- { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T2_5280_5280 AFTER(T1_5280_5280)
- { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T1_5250_5250 AFTER(T2_5280_5280)
- { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T1_5290_5290 AFTER(T1_5250_5250)
- { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T1_5250_5290 AFTER(T1_5290_5290)
- { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T2_5250_5290 AFTER(T1_5250_5290)

- { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+ { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
#define T1_5540_5660 AFTER(T2_5250_5290)
- { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5760_5800 AFTER(T1_5540_5660)
- { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T2_5760_5800 AFTER(T1_5760_5800)

- { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_5765_5805 AFTER(T2_5760_5800)

/*
* Below are the WWR frequencies
*/
- { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
+ { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define WT1_5210_5250 AFTER(T1_5765_5805)
- { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
+ { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define WT1_5290_5290 AFTER(WT1_5210_5250)
- { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
+ { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
#define WT1_5540_5660 AFTER(WT1_5290_5290)
- { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0},
+ { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR },
#define WT1_5760_5800 AFTER(WT1_5540_5660)
};

@@ -1030,67 +855,67 @@ static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {
* 2GHz 11b channel tags
*/
static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {
- { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2312_2372 0
- { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define F2_2312_2372 AFTER(F1_2312_2372)

- { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2412_2472 AFTER(F2_2312_2372)
- { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
+ { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA },
#define F2_2412_2472 AFTER(F1_2412_2472)
- { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN },
#define F3_2412_2472 AFTER(F2_2412_2472)

- { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2412_2462 AFTER(F3_2412_2472)
- { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
+ { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA },
#define F2_2412_2462 AFTER(F1_2412_2462)

- { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2432_2442 AFTER(F2_2412_2462)

- { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2457_2472 AFTER(F1_2432_2442)

- { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0},
+ { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA },
#define F1_2467_2472 AFTER(F1_2457_2472)

- { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2484_2484 AFTER(F1_2467_2472)
- { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0},
+ { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2 },
#define F2_2484_2484 AFTER(F1_2484_2484)

- { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define F1_2512_2732 AFTER(F2_2484_2484)

/*
* WWR have powers opened up to 20dBm.
* Limits should often come from CTL/Max powers
*/
- { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define W1_2312_2372 AFTER(F1_2512_2732)
- { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define W1_2412_2412 AFTER(W1_2312_2372)
- { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define W1_2417_2432 AFTER(W1_2412_2412)
- { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define W1_2437_2442 AFTER(W1_2417_2432)
- { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define W1_2447_2457 AFTER(W1_2437_2442)
- { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define W1_2462_2462 AFTER(W1_2447_2457)
- { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+ { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
#define W1_2467_2467 AFTER(W1_2462_2462)
- { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+ { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
#define W2_2467_2467 AFTER(W1_2467_2467)
- { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+ { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
#define W1_2472_2472 AFTER(W2_2467_2467)
- { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+ { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
#define W2_2472_2472 AFTER(W1_2472_2472)
- { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+ { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
#define W1_2484_2484 AFTER(W2_2472_2472)
- { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+ { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
#define W2_2484_2484 AFTER(W1_2484_2484)
};

@@ -1098,112 +923,89 @@ static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {
* 2GHz 11g channel tags
*/
static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {
- { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define G1_2312_2372 0
- { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define G2_2312_2372 AFTER(G1_2312_2372)
- { 2312, 2372, 5, 6, 10, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 5, 6, 10, 5, NO_DFS, NO_PSCAN },
#define G3_2312_2372 AFTER(G2_2312_2372)
- { 2312, 2372, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 5, 6, 5, 5, NO_DFS, NO_PSCAN },
#define G4_2312_2372 AFTER(G3_2312_2372)

- { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define G1_2412_2472 AFTER(G4_2312_2372)
- { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},
+ { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G },
#define G2_2412_2472 AFTER(G1_2412_2472)
- { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN },
#define G3_2412_2472 AFTER(G2_2412_2472)
- { 2412, 2472, 5, 6, 10, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2472, 5, 6, 10, 5, NO_DFS, NO_PSCAN },
#define G4_2412_2472 AFTER(G3_2412_2472)
- { 2412, 2472, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2472, 5, 6, 5, 5, NO_DFS, NO_PSCAN },
#define G5_2412_2472 AFTER(G4_2412_2472)

- { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN },
#define G1_2412_2462 AFTER(G5_2412_2472)
- { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},
+ { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G },
#define G2_2412_2462 AFTER(G1_2412_2462)
- { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN },
#define G3_2412_2462 AFTER(G2_2412_2462)
- { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN },
#define G4_2412_2462 AFTER(G3_2412_2462)

- { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define G1_2432_2442 AFTER(G4_2412_2462)

- { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define G1_2457_2472 AFTER(G1_2432_2442)

- { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN },
#define G1_2512_2732 AFTER(G1_2457_2472)
- { 2512, 2732, 5, 6, 10, 5, NO_DFS, NO_PSCAN, 0},
+ { 2512, 2732, 5, 6, 10, 5, NO_DFS, NO_PSCAN },
#define G2_2512_2732 AFTER(G1_2512_2732)
- { 2512, 2732, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0},
+ { 2512, 2732, 5, 6, 5, 5, NO_DFS, NO_PSCAN },
#define G3_2512_2732 AFTER(G2_2512_2732)

- { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0 },
+ { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA },
#define G1_2467_2472 AFTER(G3_2512_2732)

/*
* WWR open up the power to 20dBm
*/
- { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define WG1_2312_2372 AFTER(G1_2467_2472)
- { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define WG1_2412_2412 AFTER(WG1_2312_2372)
- { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define WG1_2417_2432 AFTER(WG1_2412_2412)
- { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define WG1_2437_2442 AFTER(WG1_2417_2432)
- { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define WG1_2447_2457 AFTER(WG1_2437_2442)
- { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+ { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
#define WG1_2462_2462 AFTER(WG1_2447_2457)
- { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+ { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
#define WG1_2467_2467 AFTER(WG1_2462_2462)
- { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+ { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
#define WG2_2467_2467 AFTER(WG1_2467_2467)
- { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+ { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
#define WG1_2472_2472 AFTER(WG2_2467_2467)
- { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+ { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
#define WG2_2472_2472 AFTER(WG1_2472_2472)
-
- /*
- * Mapping for 900MHz cards like Ubiquiti SR9 and XR9
- * and ZComax GZ-901.
- */
- { 2422, 2437, 30, 0, 5, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S1_907_922_5 AFTER(WG2_2472_2472)
- { 2422, 2437, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S1_907_922_10 AFTER(S1_907_922_5)
- { 2427, 2432, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S1_912_917 AFTER(S1_907_922_10)
- { 2427, 2442, 30, 0, 5, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S2_907_922_5 AFTER(S1_912_917)
- { 2427, 2442, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S2_907_922_10 AFTER(S2_907_922_5)
- { 2432, 2437, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S2_912_917 AFTER(S2_907_922_10)
- { 2452, 2467, 30, 0, 5, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S1_908_923_5 AFTER(S2_912_917)
- { 2457, 2467, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S1_913_918_10 AFTER(S1_908_923_5)
- { 2457, 2467, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
-#define S1_913_918 AFTER(S1_913_918_10)
};

/*
* 2GHz Dynamic turbo tags
*/
static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = {
- { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_2312_2372 0
- { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_2437_2437 AFTER(T1_2312_2372)
- { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T2_2437_2437 AFTER(T1_2437_2437)
- { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0},
+ { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR },
#define T3_2437_2437 AFTER(T2_2437_2437)
- { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+ { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN },
#define T1_2512_2732 AFTER(T3_2437_2437)
};

@@ -1231,9 +1033,18 @@ static REG_DOMAIN regDomains[] = {
{.regDmnEnum = DEBUG_REG_DMN,
.conformanceTestLimit = FCC,
.dfsMask = DFS_FCC3,
- .chan11a = BM3(F1_5120_5240, F1_5260_5700, F1_5745_5825),
- .chan11a_half = BM3(F2_5120_5240, F2_5260_5700, F7_5745_5825),
- .chan11a_quarter = BM3(F3_5120_5240, F3_5260_5700, F8_5745_5825),
+ .chan11a = BM4(F1_4950_4980,
+ F1_5120_5240,
+ F1_5260_5700,
+ F1_5745_5825),
+ .chan11a_half = BM4(F1_4945_4985,
+ F2_5120_5240,
+ F2_5260_5700,
+ F7_5745_5825),
+ .chan11a_quarter = BM4(F1_4942_4987,
+ F3_5120_5240,
+ F3_5260_5700,
+ F8_5745_5825),
.chan11a_turbo = BM8(T1_5130_5210,
T1_5250_5330,
T1_5370_5490,
@@ -1410,7 +1221,7 @@ static REG_DOMAIN regDomains[] = {
.pscan = PSCAN_MKK2,
.flags = DISALLOW_ADHOC_11A_TURB,
.chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230),
- .chan11a_half = BM4(F1_4915_4925,
+ .chan11a_half = BM4(F1_4915_4925,
F1_4935_4945,
F1_5035_5040,
F1_5055_5055),
@@ -1695,7 +1506,7 @@ static REG_DOMAIN regDomains[] = {
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
- .flags = ADHOC_NO_11A,
+ .flags = DISALLOW_ADHOC_11A,
.chan11a = BM5(W1_5260_5320,
W1_5180_5240,
W1_5170_5230,
@@ -1723,7 +1534,7 @@ static REG_DOMAIN regDomains[] = {
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
- .flags = ADHOC_NO_11A,
+ .flags = DISALLOW_ADHOC_11A,
.chan11a = BM5(W1_5260_5320,
W1_5180_5240,
W1_5170_5230,
@@ -1781,7 +1592,7 @@ static REG_DOMAIN regDomains[] = {
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
- .flags = ADHOC_NO_11A,
+ .flags = DISALLOW_ADHOC_11A,
.chan11a = BM4(W2_5260_5320,
W2_5180_5240,
F2_5745_5805,
@@ -1805,7 +1616,7 @@ static REG_DOMAIN regDomains[] = {
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
- .flags = ADHOC_NO_11A,
+ .flags = DISALLOW_ADHOC_11A,
.chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825),
.chan11b = BM7(W1_2412_2412,
W1_2437_2442,
@@ -1827,7 +1638,7 @@ static REG_DOMAIN regDomains[] = {
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
- .flags = ADHOC_NO_11A,
+ .flags = DISALLOW_ADHOC_11A,
.chan11a = BM4(W1_5260_5320,
W1_5180_5240,
W1_5745_5825,
@@ -1851,7 +1662,7 @@ static REG_DOMAIN regDomains[] = {
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
- .flags = ADHOC_NO_11A,
+ .flags = DISALLOW_ADHOC_11A,
.chan11a = BM4(W1_5260_5320,
W1_5180_5240,
W1_5745_5825,
@@ -1872,29 +1683,30 @@ static REG_DOMAIN regDomains[] = {
WG1_2467_2467),
.chan11g_turbo = BM1(T3_2437_2437)},

- {.regDmnEnum = SR9_WORLD,
- .conformanceTestLimit = NO_CTL,
- .pscan = PSCAN_FCC | PSCAN_FCC_T,
- .chan11g = BM1(S1_912_917),
- .chan11g_half = BM1(S1_907_922_10),
- .chan11g_quarter = BM1(S1_907_922_5),
- },
-
- {.regDmnEnum = XR9_WORLD,
- .conformanceTestLimit = NO_CTL,
- .pscan = PSCAN_FCC | PSCAN_FCC_T,
- .chan11g = BM1(S2_912_917),
- .chan11g_half = BM1(S2_907_922_10),
- .chan11g_quarter = BM1(S2_907_922_5),
- },
-
- {.regDmnEnum = GZ901_WORLD,
+ {.regDmnEnum = WORB_WORLD,
.conformanceTestLimit = NO_CTL,
- .pscan = PSCAN_FCC | PSCAN_FCC_T,
- .chan11g = BM1(S1_913_918),
- .chan11g_half = BM1(S1_913_918_10),
- .chan11g_quarter = BM1(S1_908_923_5),
- },
+ .dfsMask = DFS_FCC3 | DFS_ETSI,
+ .pscan = PSCAN_WWR,
+ .flags = DISALLOW_ADHOC_11A,
+ .chan11a = BM4(W1_5260_5320,
+ W1_5180_5240,
+ W1_5745_5825,
+ W1_5500_5700),
+ .chan11b = BM7(W1_2412_2412,
+ W1_2437_2442,
+ W1_2462_2462,
+ W1_2472_2472,
+ W1_2417_2432,
+ W1_2447_2457,
+ W1_2467_2467),
+ .chan11g = BM7(WG1_2412_2412,
+ WG1_2437_2442,
+ WG1_2462_2462,
+ WG1_2472_2472,
+ WG1_2417_2432,
+ WG1_2447_2457,
+ WG1_2467_2467),
+ .chan11g_turbo = BM1(T3_2437_2437)},

{.regDmnEnum = NULL1,
.conformanceTestLimit = NO_CTL,
@@ -1907,44 +1719,33 @@ struct cmode {
};

static const struct cmode modes[] = {
- { HAL_MODE_TURBO, CHANNEL_ST}, /* NB: 11a Static Turbo */
- { HAL_MODE_11A, CHANNEL_A},
- { HAL_MODE_11B, CHANNEL_B},
- { HAL_MODE_11G, CHANNEL_G},
- { HAL_MODE_11G_TURBO, CHANNEL_108G},
- { HAL_MODE_11A_TURBO, CHANNEL_108A},
- { HAL_MODE_11A_QUARTER_RATE, CHANNEL_A | CHANNEL_QUARTER},
- { HAL_MODE_11A_HALF_RATE, CHANNEL_A | CHANNEL_HALF},
- { HAL_MODE_11G_QUARTER_RATE, CHANNEL_G | CHANNEL_QUARTER},
- { HAL_MODE_11G_HALF_RATE, CHANNEL_G | CHANNEL_HALF},
- { HAL_MODE_11NG_HT20, CHANNEL_G_HT20},
- { HAL_MODE_11NG_HT40PLUS, CHANNEL_G_HT40PLUS},
- { HAL_MODE_11NG_HT40MINUS, CHANNEL_G_HT40MINUS},
- { HAL_MODE_11NA_HT20, CHANNEL_A_HT20},
- { HAL_MODE_11NA_HT40PLUS, CHANNEL_A_HT40PLUS},
- { HAL_MODE_11NA_HT40MINUS, CHANNEL_A_HT40MINUS},
+ { HAL_MODE_TURBO, IEEE80211_CHAN_ST },
+ { HAL_MODE_11A, IEEE80211_CHAN_A },
+ { HAL_MODE_11B, IEEE80211_CHAN_B },
+ { HAL_MODE_11G, IEEE80211_CHAN_G },
+ { HAL_MODE_11G_TURBO, IEEE80211_CHAN_108G },
+ { HAL_MODE_11A_TURBO, IEEE80211_CHAN_108A },
+ { HAL_MODE_11A_QUARTER_RATE,
+ IEEE80211_CHAN_A | IEEE80211_CHAN_QUARTER },
+ { HAL_MODE_11A_HALF_RATE,
+ IEEE80211_CHAN_A | IEEE80211_CHAN_HALF },
+ { HAL_MODE_11G_QUARTER_RATE,
+ IEEE80211_CHAN_G | IEEE80211_CHAN_QUARTER },
+ { HAL_MODE_11G_HALF_RATE,
+ IEEE80211_CHAN_G | IEEE80211_CHAN_HALF },
+ { HAL_MODE_11NG_HT20, IEEE80211_CHAN_G | IEEE80211_CHAN_HT20 },
+ { HAL_MODE_11NG_HT40PLUS,
+ IEEE80211_CHAN_G | IEEE80211_CHAN_HT40U },
+ { HAL_MODE_11NG_HT40MINUS,
+ IEEE80211_CHAN_G | IEEE80211_CHAN_HT40D },
+ { HAL_MODE_11NA_HT20, IEEE80211_CHAN_A | IEEE80211_CHAN_HT20 },
+ { HAL_MODE_11NA_HT40PLUS,
+ IEEE80211_CHAN_A | IEEE80211_CHAN_HT40U },
+ { HAL_MODE_11NA_HT40MINUS,
+ IEEE80211_CHAN_A | IEEE80211_CHAN_HT40D },
};

-static int
-chansort(const void *a, const void *b)
-{
-#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
- const HAL_CHANNEL_INTERNAL *ca = a;
- const HAL_CHANNEL_INTERNAL *cb = b;
-
- return (ca->channel == cb->channel) ?
- (ca->channelFlags & CHAN_FLAGS) -
- (cb->channelFlags & CHAN_FLAGS) :
- ca->channel - cb->channel;
-#undef CHAN_FLAGS
-}
-typedef int ath_hal_cmp_t(const void *, const void *);
-static void ath_hal_sort(void *a, size_t n, size_t es, ath_hal_cmp_t *cmp);
-static COUNTRY_CODE_TO_ENUM_RD* findCountry(HAL_CTRY_CODE countryCode);
-static HAL_BOOL getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country, uint16_t channelFlag, REG_DOMAIN *rd);
-
-
-static uint16_t
+static OS_INLINE uint16_t
getEepromRD(struct ath_hal *ah)
{
return AH_PRIVATE(ah)->ah_currentRD &~ WORLDWIDE_ROAMING_FLAG;
@@ -1992,220 +1793,45 @@ isEepromValid(struct ath_hal *ah)
}

/*
- * Returns whether or not the specified country code
- * is allowed by the EEPROM setting
- */
-static HAL_BOOL
-isCountryCodeValid(struct ath_hal *ah, HAL_CTRY_CODE cc)
-{
- uint16_t rd;
-
- /* Default setting requires no checks */
- if (cc == CTRY_DEFAULT)
- return AH_TRUE;
-#ifdef AH_DEBUG_COUNTRY
- if (cc == CTRY_DEBUG)
- return AH_TRUE;
-#endif
- rd = getEepromRD(ah);
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM regdomain 0x%x\n",
- __func__, rd);
-
- if (rd & COUNTRY_ERD_FLAG) {
- /* EEP setting is a country - config shall match */
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: EEPROM setting is country code %u\n", __func__,
- rd &~ COUNTRY_ERD_FLAG);
- return (cc == (rd & ~COUNTRY_ERD_FLAG));
- } else if (rd == DEBUG_REG_DMN || rd == NO_ENUMRD) {
- /* Set to Debug or AllowAnyCountry mode - allow any setting */
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: rd %d allowed\n",
- __func__, rd);
- return AH_TRUE;
-#ifdef AH_SUPPORT_11D
- } else if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX) {
- int i;
- for (i=0; i < N(allCountries); i++) {
- if (cc == allCountries[i].countryCode)
- return AH_TRUE;
- }
-#endif
- } else {
- int i;
- for (i = 0; i < N(allCountries); i++) {
- if (cc == allCountries[i].countryCode &&
- allCountries[i].regDmnEnum == rd)
- return AH_TRUE;
- }
- }
- return AH_FALSE;
-}
-
-/*
- * Return the mask of available modes based on the hardware
- * capabilities and the specified country code and reg domain.
- */
-static u_int
-ath_hal_getwmodesnreg(struct ath_hal *ah,
- const COUNTRY_CODE_TO_ENUM_RD *country, const REG_DOMAIN *rd5GHz)
-{
-#define HAL_MODE_11G_ALL \
- (HAL_MODE_11G | HAL_MODE_11G_TURBO | HAL_MODE_11G_QUARTER_RATE | \
- HAL_MODE_11G_HALF_RATE)
-#define HAL_MODE_11A_ALL \
- (HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \
- HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE)
- u_int modesAvail;
-
- /* Get modes that HW is capable of */
- modesAvail = ath_hal_getWirelessModes(ah);
-
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: wireless modes 0x%x cc %u rd %u\n",
- __func__, modesAvail, country->countryCode, country->regDmnEnum);
-
- /* Check country regulations for allowed modes */
- if (!country->allow11g && (modesAvail & HAL_MODE_11G_ALL)) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow all 11g\n", __func__);
- modesAvail &= ~HAL_MODE_11G_ALL;
- }
- if (isChanBitMaskZero(rd5GHz->chan11a) &&
- (modesAvail & HAL_MODE_11A_ALL)) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow all 11a\n", __func__);
- modesAvail &= ~HAL_MODE_11A_ALL;
- }
- if ((modesAvail & (HAL_MODE_11A_TURBO | HAL_MODE_TURBO)) &&
- !country->allow11aTurbo) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11aTurbo\n", __func__);
- modesAvail &= ~(HAL_MODE_11A_TURBO | HAL_MODE_TURBO);
- }
- if ((modesAvail & HAL_MODE_11G_TURBO) && !country->allow11gTurbo) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11gTurbo\n", __func__);
- modesAvail &= ~HAL_MODE_11G_TURBO;
- }
-
- /* Check 11n operation */
- if ((modesAvail & HAL_MODE_11NG_HT20) && !country->allow11ng20) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11g HT20\n", __func__);
- modesAvail &= ~HAL_MODE_11NG_HT20;
- }
- if ((modesAvail & HAL_MODE_11NA_HT20) && !country->allow11na20) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11a HT20\n", __func__);
- modesAvail &= ~HAL_MODE_11NA_HT20;
- }
- if ((modesAvail & HAL_MODE_11NG_HT40PLUS) && !country->allow11ng40) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11g HT40+\n", __func__);
- modesAvail &= ~HAL_MODE_11NG_HT40PLUS;
- }
- if ((modesAvail & HAL_MODE_11NG_HT40MINUS) && !country->allow11ng40) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11g HT40-\n", __func__);
- modesAvail &= ~HAL_MODE_11NG_HT40MINUS;
- }
- if ((modesAvail & HAL_MODE_11NA_HT40PLUS) && !country->allow11na40) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11a HT40+\n", __func__);
- modesAvail &= ~HAL_MODE_11NA_HT40PLUS;
- }
- if ((modesAvail & HAL_MODE_11NA_HT40MINUS) && !country->allow11na40) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: disallow 11a HT40-\n", __func__);
- modesAvail &= ~HAL_MODE_11NA_HT40MINUS;
- }
-
- return modesAvail;
-#undef HAL_MODE_11A_ALL
-#undef HAL_MODE_11G_ALL
-}
-
-/*
- * Return the mask of available modes based on the hardware
- * capabilities and the specified country code.
- */
-
-u_int
-ath_hal_getwirelessmodes(struct ath_hal *ah, HAL_CTRY_CODE cc)
-{
- COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
- u_int mode = 0;
- REG_DOMAIN rd;
-
- country = findCountry(cc);
- if (country != AH_NULL) {
- if (getWmRD(ah, country, ~CHANNEL_2GHZ, &rd))
- mode = ath_hal_getwmodesnreg(ah, country, &rd);
- }
- return mode;
-}
-
-/*
- * Return if device is public safety.
+ * Find the pointer to the country element in the country table
+ * corresponding to the country code
*/
-HAL_BOOL
-ath_hal_ispublicsafetysku(struct ath_hal *ah)
+static COUNTRY_CODE_TO_ENUM_RD*
+findCountry(HAL_CTRY_CODE countryCode)
{
- uint16_t rd = getEepromRD(ah);
+ int i;

- switch (rd) {
- case FCC4_FCCA:
- case CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG:
- return AH_TRUE;
- case DEBUG_REG_DMN:
- case NO_ENUMRD:
- if (AH_PRIVATE(ah)->ah_countryCode == CTRY_UNITED_STATES_FCC49)
- return AH_TRUE;
- break;
+ for (i = 0; i < N(allCountries); i++) {
+ if (allCountries[i].countryCode == countryCode)
+ return &allCountries[i];
}
- return AH_FALSE;
+ return AH_NULL;
}

-/*
- * Return if device is actually operating in 900 MHz band.
- */
-HAL_BOOL
-ath_hal_isgsmsku(struct ath_hal *ah)
+static REG_DOMAIN *
+findRegDmn(int regDmn)
{
- uint16_t rd = getEepromRD(ah);
+ int i;

- switch (rd) {
- case SR9_WORLD:
- case XR9_WORLD:
- case GZ901_WORLD:
- case CTRY_SR9 | COUNTRY_ERD_FLAG:
- case CTRY_XR9 | COUNTRY_ERD_FLAG:
- case CTRY_GZ901 | COUNTRY_ERD_FLAG:
- return AH_TRUE;
- case DEBUG_REG_DMN:
- case NO_ENUMRD:
- return AH_PRIVATE(ah)->ah_countryCode == CTRY_SR9
- || AH_PRIVATE(ah)->ah_countryCode == CTRY_XR9
- || AH_PRIVATE(ah)->ah_countryCode == CTRY_GZ901
- ;
+ for (i = 0; i < N(regDomains); i++) {
+ if (regDomains[i].regDmnEnum == regDmn)
+ return &regDomains[i];
}
- return AH_FALSE;
+ return AH_NULL;
}

-/*
- * Find the pointer to the country element in the country table
- * corresponding to the country code
- */
-static COUNTRY_CODE_TO_ENUM_RD*
-findCountry(HAL_CTRY_CODE countryCode)
+static REG_DMN_PAIR_MAPPING *
+findRegDmnPair(int regDmnPair)
{
int i;

- for (i = 0; i < N(allCountries); i++) {
- if (allCountries[i].countryCode == countryCode)
- return &allCountries[i];
+ if (regDmnPair != NO_ENUMRD) {
+ for (i = 0; i < N(regDomainPairs); i++) {
+ if (regDomainPairs[i].regDmnEnum == regDmnPair)
+ return &regDomainPairs[i];
+ }
}
- return AH_NULL; /* Not found */
+ return AH_NULL;
}

/*
@@ -2214,14 +1840,13 @@ findCountry(HAL_CTRY_CODE countryCode)
static HAL_CTRY_CODE
getDefaultCountry(struct ath_hal *ah)
{
+ REG_DMN_PAIR_MAPPING *regpair;
uint16_t rd;
- int i;

rd = getEepromRD(ah);
if (rd & COUNTRY_ERD_FLAG) {
- COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
+ COUNTRY_CODE_TO_ENUM_RD *country;
uint16_t cc = rd & ~COUNTRY_ERD_FLAG;
-
country = findCountry(cc);
if (country != AH_NULL)
return cc;
@@ -2229,247 +1854,174 @@ getDefaultCountry(struct ath_hal *ah)
/*
* Check reg domains that have only one country
*/
- for (i = 0; i < N(regDomainPairs); i++)
- if (regDomainPairs[i].regDmnEnum == rd) {
- if (regDomainPairs[i].singleCC != 0)
- return regDomainPairs[i].singleCC;
- else
- i = N(regDomainPairs);
- }
- return CTRY_DEFAULT;
+ regpair = findRegDmnPair(rd);
+ return (regpair != AH_NULL) ? regpair->singleCC : CTRY_DEFAULT;
}

static HAL_BOOL
-isValidRegDmn(int regDmn, REG_DOMAIN *rd)
-{
- int i;
-
- for (i = 0; i < N(regDomains); i++) {
- if (regDomains[i].regDmnEnum == regDmn) {
- if (rd != AH_NULL) {
- OS_MEMCPY(rd, &regDomains[i],
- sizeof(REG_DOMAIN));
- }
- return AH_TRUE;
- }
- }
- return AH_FALSE;
-}
-
-static HAL_BOOL
-isValidRegDmnPair(int regDmnPair)
+IS_BIT_SET(int bit, const uint64_t bitmask[])
{
- int i;
+ int byteOffset, bitnum;
+ uint64_t val;

- if (regDmnPair == NO_ENUMRD)
- return AH_FALSE;
- for (i = 0; i < N(regDomainPairs); i++) {
- if (regDomainPairs[i].regDmnEnum == regDmnPair)
- return AH_TRUE;
- }
- return AH_FALSE;
+ byteOffset = bit/64;
+ bitnum = bit - byteOffset*64;
+ val = ((uint64_t) 1) << bitnum;
+ return (bitmask[byteOffset] & val) != 0;
}

-/*
- * Return the Wireless Mode Regulatory Domain based
- * on the country code and the wireless mode.
- */
-static HAL_BOOL
-getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country,
- uint16_t channelFlag, REG_DOMAIN *rd)
+static HAL_STATUS
+getregstate(struct ath_hal *ah, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
+ COUNTRY_CODE_TO_ENUM_RD **pcountry,
+ REG_DOMAIN **prd2GHz, REG_DOMAIN **prd5GHz)
{
- int regDmn;
- REG_DMN_PAIR_MAPPING *regPair;
- uint64_t flags;
+ COUNTRY_CODE_TO_ENUM_RD *country;
+ REG_DOMAIN *rd5GHz, *rd2GHz;

- if (country->countryCode == CTRY_DEFAULT) {
- uint16_t rdnum = getEepromRD(ah);
+ if (cc == CTRY_DEFAULT && regDmn == SKU_NONE) {
+ /*
+ * Validate the EEPROM setting and setup defaults
+ */
+ if (!isEepromValid(ah)) {
+ /*
+ * Don't return any channels if the EEPROM has an
+ * invalid regulatory domain/country code setting.
+ */
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: invalid EEPROM contents\n",__func__);
+ return HAL_EEBADREG;
+ }

- if ((rdnum & COUNTRY_ERD_FLAG) == 0) {
- if (isValidRegDmn(rdnum, AH_NULL) ||
- isValidRegDmnPair(rdnum))
- regDmn = rdnum;
- else
- regDmn = country->regDmnEnum;
- } else
- regDmn = country->regDmnEnum;
- } else
+ cc = getDefaultCountry(ah);
+ country = findCountry(cc);
+ if (country == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "NULL Country!, cc %d\n", cc);
+ return HAL_EEBADCC;
+ }
regDmn = country->regDmnEnum;
- regPair = AH_NULL;
- flags = NO_REQ;
- if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
- int i;
-
- for (i = 0; i < N(regDomainPairs); i++) {
- if (regDomainPairs[i].regDmnEnum == regDmn) {
- regPair = &regDomainPairs[i];
- break;
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM cc %u rd 0x%x\n",
+ __func__, cc, regDmn);
+
+ if (country->countryCode == CTRY_DEFAULT) {
+ /*
+ * Check EEPROM; SKU may be for a country, single
+ * domain, or multiple domains (WWR).
+ */
+ uint16_t rdnum = getEepromRD(ah);
+ if ((rdnum & COUNTRY_ERD_FLAG) == 0 &&
+ (findRegDmn(rdnum) != AH_NULL ||
+ findRegDmnPair(rdnum) != AH_NULL)) {
+ regDmn = rdnum;
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: EEPROM rd 0x%x\n", __func__, rdnum);
}
}
- if (regPair == AH_NULL) {
+ } else {
+ country = findCountry(cc);
+ if (country == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: Failed to find reg domain pair %u\n",
- __func__, regDmn);
- return AH_FALSE;
- }
- if (channelFlag & CHANNEL_2GHZ) {
- regDmn = regPair->regDmn2GHz;
- flags = regPair->flags2GHz;
- } else {
- regDmn = regPair->regDmn5GHz;
- flags = regPair->flags5GHz;
+ "unknown country, cc %d\n", cc);
+ return HAL_EINVAL;
}
+ if (regDmn == SKU_NONE)
+ regDmn = country->regDmnEnum;
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u rd 0x%x\n",
+ __func__, cc, regDmn);
}

/*
- * We either started with a unitary reg domain or we've found the
- * unitary reg domain of the pair
+ * Setup per-band state.
*/
- if (isValidRegDmn(regDmn, rd)) {
- if (regPair != AH_NULL)
- rd->pscan &= regPair->pscanMask;
- if ((country->regDmnEnum & MULTI_DOMAIN_MASK) == 0 &&
- flags != NO_REQ)
- rd->flags = flags;
- return AH_TRUE;
+ if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
+ REG_DMN_PAIR_MAPPING *regpair = findRegDmnPair(regDmn);
+ if (regpair == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: no reg domain pair %u for country %u\n",
+ __func__, regDmn, country->countryCode);
+ return HAL_EINVAL;
+ }
+ rd5GHz = findRegDmn(regpair->regDmn5GHz);
+ if (rd5GHz == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: no 5GHz reg domain %u for country %u\n",
+ __func__, regpair->regDmn5GHz, country->countryCode);
+ return HAL_EINVAL;
+ }
+ rd2GHz = findRegDmn(regpair->regDmn2GHz);
+ if (rd2GHz == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: no 2GHz reg domain %u for country %u\n",
+ __func__, regpair->regDmn2GHz, country->countryCode);
+ return HAL_EINVAL;
+ }
} else {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: Failed to find unitary reg domain %u\n", __func__,
- country->regDmnEnum);
- return AH_FALSE;
- }
-}
-
-static HAL_BOOL
-IS_BIT_SET(int bit, const uint64_t bitmask[])
-{
- int byteOffset, bitnum;
- uint64_t val;
-
- byteOffset = bit/64;
- bitnum = bit - byteOffset*64;
- val = ((uint64_t) 1) << bitnum;
- return (bitmask[byteOffset] & val) != 0;
-}
-
-/* Add given regclassid into regclassids array upto max of maxregids */
-static void
-ath_add_regclassid(uint8_t *regclassids, u_int maxregids,
- u_int *nregids, uint8_t regclassid)
-{
- int i;
-
- /* Is regclassid valid? */
- if (regclassid == 0)
- return;
-
- for (i = 0; i < maxregids; i++) {
- if (regclassids[i] == regclassid) /* already present */
- return;
- if (regclassids[i] == 0) { /* free slot */
- regclassids[i] = regclassid;
- (*nregids)++;
- return;
+ rd5GHz = rd2GHz = findRegDmn(regDmn);
+ if (rd2GHz == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: no unitary reg domain %u for country %u\n",
+ __func__, regDmn, country->countryCode);
+ return HAL_EINVAL;
}
}
+ if (pcountry != AH_NULL)
+ *pcountry = country;
+ *prd2GHz = rd2GHz;
+ *prd5GHz = rd5GHz;
+ return HAL_OK;
}

/*
- * Setup the channel list based on the information in the EEPROM and
- * any supplied country code. Note that we also do a bunch of EEPROM
- * verification here and setup certain regulatory-related access
- * control data used later on.
+ * Construct the channel list for the specified regulatory config.
*/
-
-HAL_BOOL
-ath_hal_init_channels(struct ath_hal *ah,
- HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
- uint8_t *regclassids, u_int maxregids, u_int *nregids,
- HAL_CTRY_CODE cc, u_int modeSelect,
- HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels)
+static HAL_STATUS
+getchannels(struct ath_hal *ah,
+ struct ieee80211_channel chans[], u_int maxchans, int *nchans,
+ u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
+ HAL_BOOL enableExtendedChannels,
+ COUNTRY_CODE_TO_ENUM_RD **pcountry,
+ REG_DOMAIN **prd2GHz, REG_DOMAIN **prd5GHz)
{
#define CHANNEL_HALF_BW 10
#define CHANNEL_QUARTER_BW 5
+#define HAL_MODE_11A_ALL \
+ (HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \
+ HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE)
+ REG_DOMAIN *rd5GHz, *rd2GHz;
u_int modesAvail;
- uint16_t maxChan;
- COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
- REG_DOMAIN rd5GHz, rd2GHz;
const struct cmode *cm;
- HAL_CHANNEL_INTERNAL *ichans = &AH_PRIVATE(ah)->ah_channels[0];
+ struct ieee80211_channel *ic;
int next, b;
- uint8_t ctl;
+ HAL_STATUS status;

- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u mode 0x%x%s%s\n",
- __func__, cc, modeSelect, enableOutdoor? " Enable outdoor" : " ",
- enableExtendedChannels ? " Enable ecm" : "");
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u regDmn 0x%x mode 0x%x%s\n",
+ __func__, cc, regDmn, modeSelect,
+ enableExtendedChannels ? " ecm" : "");

- /*
- * Validate the EEPROM setting and setup defaults
- */
- if (!isEepromValid(ah)) {
- /*
- * Don't return any channels if the EEPROM has an
- * invalid regulatory domain/country code setting.
- */
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: invalid EEPROM contents\n",__func__);
- return AH_FALSE;
- }
-
- AH_PRIVATE(ah)->ah_countryCode = getDefaultCountry(ah);
-
-#ifndef AH_SUPPORT_11D
- if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT) {
-#endif
- /*
- * We now have enough state to validate any country code
- * passed in by the caller.
- */
- if (!isCountryCodeValid(ah, cc)) {
- /* NB: Atheros silently ignores invalid country codes */
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: invalid country code %d\n", __func__, cc);
- return AH_FALSE;
- }
- AH_PRIVATE(ah)->ah_countryCode = cc & COUNTRY_CODE_MASK;
-#ifndef AH_SUPPORT_11D
- }
-#endif
-
- /* Get pointers to the country element and the reg domain elements */
- country = findCountry(AH_PRIVATE(ah)->ah_countryCode);
-
- if (country == AH_NULL) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "NULL Country!, cc= %d\n",
- AH_PRIVATE(ah)->ah_countryCode);
- return AH_FALSE;
- }
+ status = getregstate(ah, cc, regDmn, pcountry, &rd2GHz, &rd5GHz);
+ if (status != HAL_OK)
+ return status;

- if (!getWmRD(ah, country, ~CHANNEL_2GHZ, &rd5GHz)) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: no unitary 5GHz regdomain for country %u\n",
- __func__, AH_PRIVATE(ah)->ah_countryCode);
- return AH_FALSE;
- }
- if (!getWmRD(ah, country, CHANNEL_2GHZ, &rd2GHz)) {
+ /* get modes that HW is capable of */
+ modesAvail = ath_hal_getWirelessModes(ah);
+ /* optimize work below if no 11a channels */
+ if (isChanBitMaskZero(rd5GHz->chan11a) &&
+ (modesAvail & HAL_MODE_11A_ALL)) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: no unitary 2GHz regdomain for country %u\n",
- __func__, AH_PRIVATE(ah)->ah_countryCode);
- return AH_FALSE;
+ "%s: disallow all 11a\n", __func__);
+ modesAvail &= ~HAL_MODE_11A_ALL;
}

- modesAvail = ath_hal_getwmodesnreg(ah, country, &rd5GHz);
- maxChan = !enableOutdoor ? country->outdoorChanStart : 7000;
-
- if (maxchans > N(AH_PRIVATE(ah)->ah_channels))
- maxchans = N(AH_PRIVATE(ah)->ah_channels);
next = 0;
+ ic = &chans[0];
for (cm = modes; cm < &modes[N(modes)]; cm++) {
uint16_t c, c_hi, c_lo;
uint64_t *channelBM = AH_NULL;
- REG_DOMAIN *rd = AH_NULL;
REG_DMN_FREQ_BAND *fband = AH_NULL,*freqs;
int low_adj, hi_adj, channelSep, lastc;
+ uint32_t rdflags;
+ uint64_t dfsMask;
+ uint64_t pscan;

if ((cm->mode & modeSelect) == 0) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
@@ -2492,10 +2044,22 @@ ath_hal_init_channels(struct ath_hal *ah,
}
switch (cm->mode) {
case HAL_MODE_TURBO:
- rd = &rd5GHz;
- channelBM = rd->chan11a_turbo;
+ case HAL_MODE_11A_TURBO:
+ rdflags = rd5GHz->flags;
+ dfsMask = rd5GHz->dfsMask;
+ pscan = rd5GHz->pscan;
+ if (cm->mode == HAL_MODE_TURBO)
+ channelBM = rd5GHz->chan11a_turbo;
+ else
+ channelBM = rd5GHz->chan11a_dyn_turbo;
freqs = &regDmn5GhzTurboFreq[0];
- ctl = rd->conformanceTestLimit | CTL_TURBO;
+ break;
+ case HAL_MODE_11G_TURBO:
+ rdflags = rd2GHz->flags;
+ dfsMask = rd2GHz->dfsMask;
+ pscan = rd2GHz->pscan;
+ channelBM = rd2GHz->chan11g_turbo;
+ freqs = &regDmn2Ghz11gTurboFreq[0];
break;
case HAL_MODE_11A:
case HAL_MODE_11A_HALF_RATE:
@@ -2503,49 +2067,39 @@ ath_hal_init_channels(struct ath_hal *ah,
case HAL_MODE_11NA_HT20:
case HAL_MODE_11NA_HT40PLUS:
case HAL_MODE_11NA_HT40MINUS:
- rd = &rd5GHz;
+ rdflags = rd5GHz->flags;
+ dfsMask = rd5GHz->dfsMask;
+ pscan = rd5GHz->pscan;
if (cm->mode == HAL_MODE_11A_HALF_RATE)
- channelBM = rd->chan11a_half;
+ channelBM = rd5GHz->chan11a_half;
else if (cm->mode == HAL_MODE_11A_QUARTER_RATE)
- channelBM = rd->chan11a_quarter;
+ channelBM = rd5GHz->chan11a_quarter;
else
- channelBM = rd->chan11a;
+ channelBM = rd5GHz->chan11a;
freqs = &regDmn5GhzFreq[0];
- ctl = rd->conformanceTestLimit;
break;
case HAL_MODE_11B:
- rd = &rd2GHz;
- channelBM = rd->chan11b;
- freqs = &regDmn2GhzFreq[0];
- ctl = rd->conformanceTestLimit | CTL_11B;
- break;
case HAL_MODE_11G:
case HAL_MODE_11G_HALF_RATE:
case HAL_MODE_11G_QUARTER_RATE:
case HAL_MODE_11NG_HT20:
case HAL_MODE_11NG_HT40PLUS:
case HAL_MODE_11NG_HT40MINUS:
- rd = &rd2GHz;
+ rdflags = rd2GHz->flags;
+ dfsMask = rd2GHz->dfsMask;
+ pscan = rd2GHz->pscan;
if (cm->mode == HAL_MODE_11G_HALF_RATE)
- channelBM = rd->chan11g_half;
+ channelBM = rd2GHz->chan11g_half;
else if (cm->mode == HAL_MODE_11G_QUARTER_RATE)
- channelBM = rd->chan11g_quarter;
+ channelBM = rd2GHz->chan11g_quarter;
+ else if (cm->mode == HAL_MODE_11B)
+ channelBM = rd2GHz->chan11b;
else
- channelBM = rd->chan11g;
- freqs = &regDmn2Ghz11gFreq[0];
- ctl = rd->conformanceTestLimit | CTL_11G;
- break;
- case HAL_MODE_11G_TURBO:
- rd = &rd2GHz;
- channelBM = rd->chan11g_turbo;
- freqs = &regDmn2Ghz11gTurboFreq[0];
- ctl = rd->conformanceTestLimit | CTL_108G;
- break;
- case HAL_MODE_11A_TURBO:
- rd = &rd5GHz;
- channelBM = rd->chan11a_dyn_turbo;
- freqs = &regDmn5GhzTurboFreq[0];
- ctl = rd->conformanceTestLimit | CTL_108G;
+ channelBM = rd2GHz->chan11g;
+ if (cm->mode == HAL_MODE_11B)
+ freqs = &regDmn2GhzFreq[0];
+ else
+ freqs = &regDmn2Ghz11gFreq[0];
break;
default:
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
@@ -2571,26 +2125,15 @@ ath_hal_init_channels(struct ath_hal *ah,
fband = &freqs[b];
lastc = 0;

- ath_add_regclassid(regclassids, maxregids,
- nregids, fband->regClassId);
-
for (c = fband->lowChannel + low_adj;
c <= fband->highChannel + hi_adj;
c += fband->channelSep) {
- HAL_CHANNEL_INTERNAL icv;
-
if (!(c_lo <= c && c <= c_hi)) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: c %u out of range [%u..%u]\n",
__func__, c, c_lo, c_hi);
continue;
}
- if (((c+fband->channelSep)/2) > (maxChan+HALF_MAXCHANBW)) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: c %u > maxChan %u\n",
- __func__, c, maxChan);
- continue;
- }
if (next >= maxchans){
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: too many channels for channel table\n",
@@ -2600,14 +2143,14 @@ ath_hal_init_channels(struct ath_hal *ah,
if ((fband->usePassScan & IS_ECM_CHAN) &&
!enableExtendedChannels) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "Skipping ecm channel\n");
+ "skip ecm channel\n");
continue;
}
- /* XXX needs to be in ath_hal_checkchannel */
- if ((rd->flags & NO_HOSTAP) &&
- (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP)) {
+ if ((fband->useDfs & dfsMask) &&
+ (cm->flags & IEEE80211_CHAN_HT40)) {
+ /* NB: DFS and HT40 don't mix */
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "Skipping HOSTAP channel\n");
+ "skip HT40 chan, DFS required\n");
continue;
}
/*
@@ -2617,245 +2160,288 @@ ath_hal_init_channels(struct ath_hal *ah,
if (lastc && channelSep &&
(c-lastc) < channelSep)
continue;
-
- OS_MEMZERO(&icv, sizeof(icv));
- icv.channel = c;
- icv.channelFlags = cm->flags;
- icv.maxRegTxPower = fband->powerDfs;
- icv.antennaMax = fband->antennaMax;
- icv.regDmnFlags = rd->flags;
- icv.conformanceTestLimit = ctl;
- if (fband->usePassScan & rd->pscan)
- icv.channelFlags |= CHANNEL_PASSIVE;
- else
- icv.channelFlags &= ~CHANNEL_PASSIVE;
lastc = c;
- if (fband->useDfs & rd->dfsMask) {
- /* DFS and HT40 don't mix */
- if (cm->mode == HAL_MODE_11NA_HT40PLUS ||
- cm->mode == HAL_MODE_11NA_HT40MINUS)
- continue;
- icv.privFlags = CHANNEL_DFS;
- } else
- icv.privFlags = 0;
- if (rd->flags & LIMIT_FRAME_4MS)
- icv.privFlags |= CHANNEL_4MS_LIMIT;
-
- ichans[next++] = icv;
+
+ OS_MEMZERO(ic, sizeof(*ic));
+ ic->ic_freq = c;
+ ic->ic_flags = cm->flags;
+ ic->ic_maxregpower = fband->powerDfs;
+ ath_hal_getpowerlimits(ah, ic);
+ ic->ic_maxantgain = fband->antennaMax;
+ if (fband->usePassScan & pscan)
+ ic->ic_flags |= IEEE80211_CHAN_PASSIVE;
+ if (fband->useDfs & dfsMask)
+ ic->ic_flags |= IEEE80211_CHAN_DFS;
+ if (IEEE80211_IS_CHAN_5GHZ(ic) &&
+ (rdflags & DISALLOW_ADHOC_11A))
+ ic->ic_flags |= IEEE80211_CHAN_NOADHOC;
+ if (IEEE80211_IS_CHAN_TURBO(ic) &&
+ (rdflags & DISALLOW_ADHOC_11A_TURB))
+ ic->ic_flags |= IEEE80211_CHAN_NOADHOC;
+ if (rdflags & NO_HOSTAP)
+ ic->ic_flags |= IEEE80211_CHAN_NOHOSTAP;
+ if (rdflags & LIMIT_FRAME_4MS)
+ ic->ic_flags |= IEEE80211_CHAN_4MSXMIT;
+ if (rdflags & NEED_NFC)
+ ic->ic_flags |= CHANNEL_NFCREQUIRED;
+
+ ic++, next++;
}
}
}
done:
- if (next != 0) {
- int i;
-
- /* XXX maxchans set above so this cannot happen? */
- if (next > N(AH_PRIVATE(ah)->ah_channels)) {
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
- "%s: too many channels %u; truncating to %u\n",
- __func__, next,
- (int) N(AH_PRIVATE(ah)->ah_channels));
- next = N(AH_PRIVATE(ah)->ah_channels);
- }
-
- /*
- * Keep a private copy of the channel list so we can
- * constrain future requests to only these channels
- */
- ath_hal_sort(ichans, next, sizeof(HAL_CHANNEL_INTERNAL),
- chansort);
- AH_PRIVATE(ah)->ah_nchan = next;
-
- /*
- * Copy the channel list to the public channel list
- */
- for (i = 0; i < next; i++) {
- chans[i].channel = ichans[i].channel;
- chans[i].channelFlags = ichans[i].channelFlags;
- chans[i].privFlags = ichans[i].privFlags;
- chans[i].maxRegTxPower = ichans[i].maxRegTxPower;
- }
- /*
- * Retrieve power limits.
- */
- ath_hal_getpowerlimits(ah, chans, next);
- for (i = 0; i < next; i++) {
- ichans[i].maxTxPower = chans[i].maxTxPower;
- ichans[i].minTxPower = chans[i].minTxPower;
- }
- }
*nchans = next;
- /* XXX copy private setting to public area */
- ah->ah_countryCode = AH_PRIVATE(ah)->ah_countryCode;
- return (next != 0);
+ /* NB: pcountry set above by getregstate */
+ if (prd2GHz != AH_NULL)
+ *prd2GHz = rd2GHz;
+ if (prd5GHz != AH_NULL)
+ *prd5GHz = rd5GHz;
+ return HAL_OK;
+#undef HAL_MODE_11A_ALL
#undef CHANNEL_HALF_BW
#undef CHANNEL_QUARTER_BW
}

/*
- * Return whether or not the specified channel is ok to use
- * based on the current regulatory domain constraints and
- * DFS interference.
+ * Retrieve a channel list without affecting runtime state.
*/
-HAL_CHANNEL_INTERNAL *
-ath_hal_checkchannel(struct ath_hal *ah, const HAL_CHANNEL *c)
+HAL_STATUS
+ath_hal_getchannels(struct ath_hal *ah,
+ struct ieee80211_channel chans[], u_int maxchans, int *nchans,
+ u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
+ HAL_BOOL enableExtendedChannels)
{
-#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
- HAL_CHANNEL_INTERNAL *base, *cc;
- /* NB: be wary of user-specified channel flags */
- int flags = c->channelFlags & CHAN_FLAGS;
- int n, lim, d;
+ return getchannels(ah, chans, maxchans, nchans, modeSelect,
+ cc, regDmn, enableExtendedChannels, AH_NULL, AH_NULL, AH_NULL);
+}

- /*
- * Check current channel to avoid the lookup.
- */
- cc = AH_PRIVATE(ah)->ah_curchan;
- if (cc != AH_NULL && cc->channel == c->channel &&
- (cc->channelFlags & CHAN_FLAGS) == flags) {
- if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
- (cc->channelFlags & CHANNEL_DFS))
- return AH_NULL;
- else
- return cc;
- }
+/*
+ * Handle frequency mapping from 900Mhz range to 2.4GHz range
+ * for GSM radios. This is done when we need the h/w frequency
+ * and the channel is marked IEEE80211_CHAN_GSM.
+ */
+static int
+ath_hal_mapgsm(int sku, int freq)
+{
+ if (sku == SKU_XR9)
+ return 1520 + freq;
+ if (sku == SKU_GZ901)
+ return 1544 + freq;
+ if (sku == SKU_SR9)
+ return 3344 - freq;
+ HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+ "%s: cannot map freq %u unknown gsm sku %u\n",
+ __func__, freq, sku);
+ return freq;
+}
+
+/*
+ * Setup the internal/private channel state given a table of
+ * net80211 channels. We collapse entries for the same frequency
+ * and record the frequency for doing noise floor processing
+ * where we don't have net80211 channel context.
+ */
+static HAL_BOOL
+assignPrivateChannels(struct ath_hal *ah,
+ struct ieee80211_channel chans[], int nchans, int sku)
+{
+ HAL_CHANNEL_INTERNAL *ic;
+ int i, j, next, freq;

- /* binary search based on known sorting order */
- base = AH_PRIVATE(ah)->ah_channels;
- n = AH_PRIVATE(ah)->ah_nchan;
- /* binary search based on known sorting order */
- for (lim = n; lim != 0; lim >>= 1) {
- cc = &base[lim>>1];
- d = c->channel - cc->channel;
- if (d == 0) {
- if ((cc->channelFlags & CHAN_FLAGS) == flags) {
- if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
- (cc->channelFlags & CHANNEL_DFS))
- return AH_NULL;
- else
- return cc;
+ next = 0;
+ for (i = 0; i < nchans; i++) {
+ struct ieee80211_channel *c = &chans[i];
+ for (j = i-1; j >= 0; j--)
+ if (chans[j].ic_freq == c->ic_freq) {
+ c->ic_devdata = chans[j].ic_devdata;
+ break;
}
- d = flags - (cc->channelFlags & CHAN_FLAGS);
- }
- if (d > 0) {
- base = cc + 1;
- lim--;
+ if (j < 0) {
+ /* new entry, assign a private channel entry */
+ if (next >= N(AH_PRIVATE(ah)->ah_channels)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: too many channels, max %zu\n",
+ __func__, N(AH_PRIVATE(ah)->ah_channels));
+ return AH_FALSE;
+ }
+ /*
+ * Handle frequency mapping for 900MHz devices.
+ * The hardware uses 2.4GHz frequencies that are
+ * down-converted. The 802.11 layer uses the
+ * true frequencies.
+ */
+ freq = IEEE80211_IS_CHAN_GSM(c) ?
+ ath_hal_mapgsm(sku, c->ic_freq) : c->ic_freq;
+
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+ "%s: private[%3u] %u/0x%x -> channel %u\n",
+ __func__, next, c->ic_freq, c->ic_flags, freq);
+
+ ic = &AH_PRIVATE(ah)->ah_channels[next];
+ /*
+ * NB: This clears privFlags which means ancillary
+ * code like ANI and IQ calibration will be
+ * restarted and re-setup any per-channel state.
+ */
+ OS_MEMZERO(ic, sizeof(*ic));
+ ic->channel = freq;
+ c->ic_devdata = next;
+ next++;
}
}
- HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: no match for %u/0x%x\n",
- __func__, c->channel, c->channelFlags);
- return AH_NULL;
-#undef CHAN_FLAGS
+ AH_PRIVATE(ah)->ah_nchan = next;
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: %u public, %u private channels\n",
+ __func__, nchans, next);
+ return AH_TRUE;
}

/*
- * Return the max allowed antenna gain and apply any regulatory
- * domain specific changes.
- *
- * NOTE: a negative reduction is possible in RD's that only
- * measure radiated power (e.g., ETSI) which would increase
- * that actual conducted output power (though never beyond
- * the calibrated target power).
+ * Setup the channel list based on the information in the EEPROM.
*/
-u_int
-ath_hal_getantennareduction(struct ath_hal *ah, HAL_CHANNEL *chan, u_int twiceGain)
+HAL_STATUS
+ath_hal_init_channels(struct ath_hal *ah,
+ struct ieee80211_channel chans[], u_int maxchans, int *nchans,
+ u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
+ HAL_BOOL enableExtendedChannels)
{
- HAL_CHANNEL_INTERNAL *ichan=AH_NULL;
- int8_t antennaMax;
-
- if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) {
- antennaMax = twiceGain - ichan->antennaMax*2;
- return (antennaMax < 0) ? 0 : antennaMax;
- } else {
- /* Failed to find the correct index - may be a debug channel */
- return 0;
- }
+ COUNTRY_CODE_TO_ENUM_RD *country;
+ REG_DOMAIN *rd5GHz, *rd2GHz;
+ HAL_STATUS status;
+
+ status = getchannels(ah, chans, maxchans, nchans, modeSelect,
+ cc, regDmn, enableExtendedChannels, &country, &rd2GHz, &rd5GHz);
+ if (status == HAL_OK &&
+ assignPrivateChannels(ah, chans, *nchans, AH_PRIVATE(ah)->ah_currentRD)) {
+ AH_PRIVATE(ah)->ah_rd2GHz = rd2GHz;
+ AH_PRIVATE(ah)->ah_rd5GHz = rd5GHz;
+
+ ah->ah_countryCode = country->countryCode;
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u\n",
+ __func__, ah->ah_countryCode);
+ } else
+ status = HAL_EINVAL;
+ return status;
}

+/*
+ * Set the channel list.
+ */
+HAL_STATUS
+ath_hal_set_channels(struct ath_hal *ah,
+ struct ieee80211_channel chans[], int nchans,
+ HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd)
+{
+ COUNTRY_CODE_TO_ENUM_RD *country;
+ REG_DOMAIN *rd5GHz, *rd2GHz;
+ HAL_STATUS status;

-/* XXX - maybe move ctl decision into channel set area or
- into the tables so no decision is needed in the code */
-
-#define isWwrSKU(_ah) \
- ((getEepromRD((_ah)) & WORLD_SKU_MASK) == WORLD_SKU_PREFIX || \
- getEepromRD(_ah) == WORLD)
+ switch (rd) {
+ case SKU_SR9:
+ case SKU_XR9:
+ case SKU_GZ901:
+ /*
+ * Map 900MHz sku's. The frequencies will be mapped
+ * according to the sku to compensate for the down-converter.
+ * We use the FCC for these sku's as the mapped channel
+ * list is known compatible (will need to change if/when
+ * vendors do different mapping in different locales).
+ */
+ status = getregstate(ah, CTRY_DEFAULT, SKU_FCC,
+ &country, &rd2GHz, &rd5GHz);
+ break;
+ default:
+ status = getregstate(ah, cc, rd,
+ &country, &rd2GHz, &rd5GHz);
+ rd = AH_PRIVATE(ah)->ah_currentRD;
+ break;
+ }
+ if (status == HAL_OK && assignPrivateChannels(ah, chans, nchans, rd)) {
+ AH_PRIVATE(ah)->ah_rd2GHz = rd2GHz;
+ AH_PRIVATE(ah)->ah_rd5GHz = rd5GHz;

+ ah->ah_countryCode = country->countryCode;
+ HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u\n",
+ __func__, ah->ah_countryCode);
+ } else
+ status = HAL_EINVAL;
+ return status;
+}

+#ifdef AH_DEBUG
/*
- * Return the test group from the specified channel from
- * the regulatory table.
- *
- * TODO: CTL for 11B CommonMode when regulatory domain is unknown
+ * Return the internal channel corresponding to a public channel.
+ * NB: normally this routine is inline'd (see ah_internal.h)
*/
-u_int
-ath_hal_getctl(struct ath_hal *ah, HAL_CHANNEL *chan)
+HAL_CHANNEL_INTERNAL *
+ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
{
- u_int ctl = NO_CTL;
- HAL_CHANNEL_INTERNAL *ichan;
-
- /* Special CTL to signify WWR SKU without a known country */
- if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
- if (IS_CHAN_B(chan)) {
- ctl = SD_NO_CTL | CTL_11B;
- } else if (IS_CHAN_G(chan)) {
- ctl = SD_NO_CTL | CTL_11G;
- } else if (IS_CHAN_108G(chan)) {
- ctl = SD_NO_CTL | CTL_108G;
- } else if (IS_CHAN_T(chan)) {
- ctl = SD_NO_CTL | CTL_TURBO;
- } else {
- ctl = SD_NO_CTL | CTL_11A;
- }
+ HAL_CHANNEL_INTERNAL *cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
+
+ if (c->ic_devdata < AH_PRIVATE(ah)->ah_nchan &&
+ (c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)))
+ return cc;
+ if (c->ic_devdata >= AH_PRIVATE(ah)->ah_nchan) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: bad mapping, devdata %u nchans %u\n",
+ __func__, c->ic_devdata, AH_PRIVATE(ah)->ah_nchan);
+ HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
} else {
- if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) {
- ctl = ichan->conformanceTestLimit;
- /* limit 11G OFDM power */
- if (IS_CHAN_PUREG(chan) &&
- (ctl & CTL_MODE_M) == CTL_11B)
- ctl = (ctl &~ CTL_MODE_M) | CTL_11G;
- }
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: no match for %u/0x%x devdata %u channel %u\n",
+ __func__, c->ic_freq, c->ic_flags, c->ic_devdata,
+ cc->channel);
+ HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
}
- return ctl;
+ return AH_NULL;
}
+#endif /* AH_DEBUG */
+
+#define isWwrSKU(_ah) \
+ ((getEepromRD((_ah)) & WORLD_SKU_MASK) == WORLD_SKU_PREFIX || \
+ getEepromRD(_ah) == WORLD)

/*
- * Return whether or not a noise floor check is required in
- * the current regulatory domain for the specified channel.
+ * Return the test group for the specific channel based on
+ * the current regulatory setup.
*/
-HAL_BOOL
-ath_hal_getnfcheckrequired(struct ath_hal *ah, HAL_CHANNEL *chan)
+u_int
+ath_hal_getctl(struct ath_hal *ah, const struct ieee80211_channel *c)
{
- HAL_CHANNEL_INTERNAL *ichan;
-
- if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL)
- return ((ichan->regDmnFlags & NEED_NFC) ? AH_TRUE : AH_FALSE);
- return AH_FALSE;
+ u_int ctl;
+
+ if (AH_PRIVATE(ah)->ah_rd2GHz == AH_PRIVATE(ah)->ah_rd5GHz ||
+ (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)))
+ ctl = SD_NO_CTL;
+ else if (IEEE80211_IS_CHAN_2GHZ(c))
+ ctl = AH_PRIVATE(ah)->ah_rd2GHz->conformanceTestLimit;
+ else
+ ctl = AH_PRIVATE(ah)->ah_rd5GHz->conformanceTestLimit;
+ if (IEEE80211_IS_CHAN_B(c))
+ return ctl | CTL_11B;
+ if (IEEE80211_IS_CHAN_G(c))
+ return ctl | CTL_11G;
+ if (IEEE80211_IS_CHAN_108G(c))
+ return ctl | CTL_108G;
+ if (IEEE80211_IS_CHAN_TURBO(c))
+ return ctl | CTL_TURBO;
+ if (IEEE80211_IS_CHAN_A(c))
+ return ctl | CTL_11A;
+ return ctl;
}

/*
- * Insertion sort.
+ * Return the max allowed antenna gain and apply any regulatory
+ * domain specific changes.
+ *
+ * NOTE: a negative reduction is possible in RD's that only
+ * measure radiated power (e.g., ETSI) which would increase
+ * that actual conducted output power (though never beyond
+ * the calibrated target power).
*/
-#define swap(_a, _b, _size) { \
- uint8_t *s = _b; \
- int i = _size; \
- do { \
- uint8_t tmp = *_a; \
- *_a++ = *s; \
- *s++ = tmp; \
- } while (--i); \
- _a -= _size; \
-}
-
-static void
-ath_hal_sort(void *a, size_t n, size_t size, ath_hal_cmp_t *cmp)
+u_int
+ath_hal_getantennareduction(struct ath_hal *ah,
+ const struct ieee80211_channel *chan, u_int twiceGain)
{
- uint8_t *aa = a;
- uint8_t *ai, *t;
-
- for (ai = aa+size; --n >= 1; ai += size)
- for (t = ai; t > aa; t -= size) {
- uint8_t *u = t - size;
- if (cmp(u, t) <= 0)
- break;
- swap(u, t, size);
- }
+ int8_t antennaMax = twiceGain - chan->ic_maxantgain*2;
+ return (antennaMax < 0) ? 0 : antennaMax;
}
diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210.h b/sys/external/isc/atheros_hal/dist/ar5210/ar5210.h
index 76d3092..01c1fdc 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210.h
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2004 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5210.h,v 1.2 2009/05/14 09:07:49 reinoud Exp $
+ * $FreeBSD$
*/
#ifndef _ATH_AR5210_H_
#define _ATH_AR5210_H_
@@ -128,20 +128,21 @@ struct ath_hal;

extern void ar5210Detach(struct ath_hal *ah);
extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
- HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *);
+ struct ieee80211_channel *, HAL_BOOL bChannelChange, HAL_STATUS *);
extern void ar5210SetPCUConfig(struct ath_hal *);
extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);
extern HAL_BOOL ar5210Disable(struct ath_hal *);
-extern HAL_BOOL ar5210ChipReset(struct ath_hal *, HAL_CHANNEL *);
-extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *);
-extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+extern HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *);
+extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);
+extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
-extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);
extern int16_t ar5210GetNoiseFloor(struct ath_hal *);
extern int16_t ar5210GetNfAdjust(struct ath_hal *,
const HAL_CHANNEL_INTERNAL *);
extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
-extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *, HAL_CHANNEL *);
+extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *,
+ const struct ieee80211_channel *);
extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);

@@ -206,7 +207,8 @@ extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
extern u_int ar5210GetWirelessModes(struct ath_hal *ah);
extern void ar5210EnableRfKill(struct ath_hal *);
extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
-extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,
+ HAL_GPIO_MUX_TYPE);
extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
@@ -254,7 +256,7 @@ extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
uint16_t, const uint8_t *);

-extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, HAL_POWER_MODE mode,
+extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
int setChip);
extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);

@@ -273,6 +275,7 @@ extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);

extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
-extern void ar5210AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *);
+extern void ar5210AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
+ const struct ieee80211_channel *);
extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
#endif /* _ATH_AR5210_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_attach.c b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_attach.c
index f22e3cd..1e2c4e5 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_attach.c
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_attach.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2004 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -31,12 +31,13 @@
static HAL_BOOL ar5210GetChannelEdges(struct ath_hal *,
uint16_t flags, uint16_t *low, uint16_t *high);
static HAL_BOOL ar5210GetChipPowerLimits(struct ath_hal *ah,
- HAL_CHANNEL *chans, uint32_t nchans);
+ struct ieee80211_channel *chan);
+
+static void ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
+static void ar5210DisablePCIE(struct ath_hal *ah);

static const struct ath_hal_private ar5210hal = {{
.ah_magic = AR5210_MAGIC,
- .ah_abi = HAL_ABI_VERSION,
- .ah_countryCode = CTRY_DEFAULT,

.ah_getRateTable = ar5210GetRateTable,
.ah_detach = ar5210Detach,
@@ -45,6 +46,8 @@ static const struct ath_hal_private ar5210hal = {{
.ah_reset = ar5210Reset,
.ah_phyDisable = ar5210PhyDisable,
.ah_disable = ar5210Disable,
+ .ah_configPCIE = ar5210ConfigPCIE,
+ .ah_disablePCIE = ar5210DisablePCIE,
.ah_setPCUConfig = ar5210SetPCUConfig,
.ah_perCalibration = ar5210PerCalibration,
.ah_perCalibrationN = ar5210PerCalibrationN,
@@ -156,11 +159,6 @@ static const struct ath_hal_private ar5210hal = {{
#ifdef AH_SUPPORT_WRITE_EEPROM
.ah_eepromWrite = ar5210EepromWrite,
#endif
- .ah_gpioCfgInput = ar5210GpioCfgInput,
- .ah_gpioCfgOutput = ar5210GpioCfgOutput,
- .ah_gpioGet = ar5210GpioGet,
- .ah_gpioSet = ar5210GpioSet,
- .ah_gpioSetIntr = ar5210Gpio0SetIntr,
.ah_getChipPowerLimits = ar5210GetChipPowerLimits,
};

@@ -303,7 +301,7 @@ static HAL_BOOL
ar5210GetChannelEdges(struct ath_hal *ah,
uint16_t flags, uint16_t *low, uint16_t *high)
{
- if (flags & CHANNEL_5GHZ) {
+ if (flags & IEEE80211_CHAN_5GHZ) {
*low = 5120;
*high = 5430;
return AH_TRUE;
@@ -313,23 +311,27 @@ ar5210GetChannelEdges(struct ath_hal *ah,
}

static HAL_BOOL
-ar5210GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+ar5210GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)
{
- HAL_CHANNEL *chan;
- int i;
-
/* XXX fill in, this is just a placeholder */
- for (i = 0; i < nchans; i++) {
- chan = &chans[i];
- HALDEBUG(ah, HAL_DEBUG_ATTACH,
- "%s: no min/max power for %u/0x%x\n",
- __func__, chan->channel, chan->channelFlags);
- chan->maxTxPower = AR5210_MAX_RATE_POWER;
- chan->minTxPower = 0;
- }
+ HALDEBUG(ah, HAL_DEBUG_ATTACH,
+ "%s: no min/max power for %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ chan->ic_maxpower = AR5210_MAX_RATE_POWER;
+ chan->ic_minpower = 0;
return AH_TRUE;
}

+static void
+ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
+{
+}
+
+static void
+ar5210DisablePCIE(struct ath_hal *ah)
+{
+}
+
/*
* Fill all software cached or static hardware state information.
*/
@@ -367,6 +369,11 @@ ar5210FillCapabilityInfo(struct ath_hal *ah)
}

pCap->halTstampPrecision = 15; /* NB: s/w extended from 13 */
+ pCap->halIntrMask = (HAL_INT_COMMON - HAL_INT_BNR)
+ | HAL_INT_RX
+ | HAL_INT_TX
+ | HAL_INT_FATAL
+ ;

ahpriv->ah_rxornIsFatal = AH_TRUE;
return AH_TRUE;
diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c
index 8832062..96b1a2c 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5210_interrupts.c,v 1.1.1.1 2008/12/11 04:46:27 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -59,7 +59,7 @@ ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
* status bits leak through that weren't requested
* (e.g. RXNOFRM) and that might confuse the caller.
*/
- *masked = (isr & HAL_INT_COMMON) & ahp->ah_maskReg;
+ *masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;

if (isr & AR_FATAL_INT)
*masked |= HAL_INT_FATAL;
@@ -105,7 +105,7 @@ ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
}

- mask = ints & HAL_INT_COMMON;
+ mask = ints & (HAL_INT_COMMON - HAL_INT_BNR);
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
if (ints & HAL_INT_TX) {
diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_misc.c b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_misc.c
index 4ff6377..7339f91 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_misc.c
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_misc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2004 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5210_misc.c,v 1.1.1.1 2008/12/11 04:46:27 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -158,7 +158,7 @@ ar5210EnableRfKill(struct ath_hal *ah)
* Configure GPIO Output lines
*/
HAL_BOOL
-ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
HALASSERT(gpio < AR_NUM_GPIO);

@@ -561,7 +561,8 @@ ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
}

void
-ar5210AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats, HAL_CHANNEL *chan)
+ar5210AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
+ const struct ieee80211_channel *chan)
{
}

diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_phy.c b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_phy.c
index ef7d8ef..7725181 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_phy.c
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_phy.c
@@ -33,14 +33,14 @@ HAL_RATE_TABLE ar5210_11a_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4, 0, 0 }
+/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 },
+/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 },
+/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }
},
};

@@ -50,14 +50,14 @@ HAL_RATE_TABLE ar5210_turbo_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, TURBO, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, TURBO, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, TURBO, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, TURBO, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, TURBO, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, TURBO, 36000, 0x0d, 0x00, 72, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, TURBO, 48000, 0x08, 0x00, 96, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, TURBO, 54000, 0x0c, 0x00, 108, 4, 0, 0 }
+/* 6 Mb */ { AH_TRUE, TURBO, 12000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, TURBO, 18000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, TURBO, 24000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, TURBO, 36000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, TURBO, 48000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, TURBO, 72000, 0x0d, 0x00, 72, 4 },
+/* 48 Mb */ { AH_TRUE, TURBO, 96000, 0x08, 0x00, 96, 4 },
+/* 54 Mb */ { AH_TRUE, TURBO, 108000, 0x0c, 0x00, 108, 4 }
},
};

diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c
index 5af54aa..e543c08 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2004 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -54,8 +54,8 @@ static const uint8_t ar5k0007_pwrSettings[17] = {
#define AR_RC_SETTLE_TIME 20000

static HAL_BOOL ar5210SetResetReg(struct ath_hal *,
- uint32_t resetMask, u_int waitTime);
-static HAL_BOOL ar5210SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+ uint32_t resetMask, u_int delay);
+static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *);
static void ar5210SetOperatingMode(struct ath_hal *, int opmode);

/*
@@ -68,7 +68,8 @@ static void ar5210SetOperatingMode(struct ath_hal *, int opmode);
*/
HAL_BOOL
ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+ struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
+ HAL_STATUS *status)
{
#define N(a) (sizeof (a) /sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
@@ -81,12 +82,12 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,

HALDEBUG(ah, HAL_DEBUG_RESET,
"%s: opmode %u channel %u/0x%x %s channel\n", __func__,
- opmode, chan->channel, chan->channelFlags,
+ opmode, chan->ic_freq, chan->ic_flags,
bChannelChange ? "change" : "same");

- if ((chan->channelFlags & CHANNEL_5GHZ) == 0) {
+ if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
/* Only 11a mode */
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5Ghz\n", __func__);
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);
FAIL(HAL_EINVAL);
}
/*
@@ -96,7 +97,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
FAIL(HAL_EINVAL);
}
switch (opmode) {
@@ -232,17 +233,13 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) |
(ee->ee_antenna & 0x3));

- if (!ar5210SetChannel(ah, ichan)) {
+ if (!ar5210SetChannel(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
__func__);
FAIL(HAL_EIO);
}
- if (bChannelChange) {
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
- }
+ if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
+ chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;

/* Activate the PHY */
OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE);
@@ -256,7 +253,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,

/* Perform noise floor calibration and set status */
if (!ar5210CalNoiseFloor(ah, ichan)) {
- chan->channelFlags |= CHANNEL_CW_INT;
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: noise floor calibration failed\n", __func__);
FAIL(HAL_EIO);
@@ -296,7 +293,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,

return AH_TRUE;
bad:
- if (*status)
+ if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
@@ -385,19 +382,20 @@ ar5210Disable(struct ath_hal *ah)
* Places the hardware into reset and then pulls it out of reset
*/
HAL_BOOL
-ar5210ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan)
{
#define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)

HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__,
- chan && IS_CHAN_TURBO(chan) ? "enabled" : "disabled");
+ chan && IEEE80211_IS_CHAN_TURBO(chan) ?
+ "enabled" : "disabled");

if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
return AH_FALSE;

/* Place chip in turbo before reset to cleanly reset clocks */
OS_REG_WRITE(ah, AR_PHY_FRCTL,
- chan && IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0);
+ chan && IEEE80211_IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0);

/*
* Reset the HW.
@@ -444,7 +442,8 @@ enum {
* changes.
*/
HAL_BOOL
-ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
+ar5210PerCalibrationN(struct ath_hal *ah,
+ struct ieee80211_channel *chan, u_int chainMask,
HAL_BOOL longCal, HAL_BOOL *isCalDone)
{
uint32_t regBeacon;
@@ -452,12 +451,8 @@ ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
HAL_CHANNEL_INTERNAL *ichan;

ichan = ath_hal_checkchannel(ah, chan);
- if (ichan == AH_NULL) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ if (ichan == AH_NULL)
return AH_FALSE;
- }
/* Disable tx and rx */
OS_REG_WRITE(ah, AR_DIAG_SW,
OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
@@ -475,7 +470,7 @@ ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
OS_DELAY(10);

/* Change Channel to relock synth */
- if (!ar5210SetChannel(ah, ichan))
+ if (!ar5210SetChannel(ah, chan))
return AH_FALSE;

/* wait for the synthesizer lock to stabilize */
@@ -531,10 +526,9 @@ ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
/* AGC calibration (this was added to make the NF threshold check work) */
OS_REG_WRITE(ah, AR_PHY_AGCCTL,
OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
- if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) {
+ if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0))
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n",
__func__);
- }

/* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */
OS_REG_WRITE(ah, 0x9858, reg9858);
@@ -552,7 +546,7 @@ ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
"%s: Performing 2nd Noise Cal\n", __func__);
OS_DELAY(5000);
if (!ar5210CalNoiseFloor(ah, ichan))
- chan->channelFlags |= CHANNEL_CW_INT;
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
}

/* Clear tx and rx disable bit */
@@ -568,13 +562,14 @@ ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
}

HAL_BOOL
-ar5210PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
+ HAL_BOOL *isIQdone)
{
return ar5210PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
}

HAL_BOOL
-ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
return AH_TRUE;
}
@@ -583,14 +578,14 @@ ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
* Writes the given reset bit mask into the reset register
*/
static HAL_BOOL
-ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int waitTime)
+ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
{
uint32_t mask = resetMask ? resetMask : ~0;
HAL_BOOL rt;

OS_REG_WRITE(ah, AR_RC, resetMask);
/* need to wait at least 128 clocks when reseting PCI before read */
- OS_DELAY(waitTime);
+ OS_DELAY(delay);

resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
@@ -730,11 +725,13 @@ ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
* Get TXPower values and set them in the radio
*/
static HAL_BOOL
-setupPowerSettings(struct ath_hal *ah, HAL_CHANNEL *chan, uint8_t cp[17])
+setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan,
+ uint8_t cp[17])
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
uint8_t gainFRD, gainF36, gainF48, gainF54;
- uint8_t dBmRD = 0, dBm36 = 0, dBm48 = 0, dBm54 = 0, dontcare;
+ uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
uint32_t rd, group;
const struct tpcMap *pRD;

@@ -742,9 +739,9 @@ setupPowerSettings(struct ath_hal *ah, HAL_CHANNEL *chan, uint8_t cp[17])
cp[15] = (ee->ee_biasCurrents >> 4) & 0x7;
cp[16] = ee->ee_biasCurrents & 0x7;

- if (chan->channel < 5170 || chan->channel > 5320) {
+ if (freq < 5170 || freq > 5320) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -764,7 +761,7 @@ setupPowerSettings(struct ath_hal *ah, HAL_CHANNEL *chan, uint8_t cp[17])
#endif
return AH_FALSE;
}
- group = ((chan->channel - 5170) / 10);
+ group = ((freq - 5170) / 10);

if (group > 11) {
/* Pull 5.29 into the 5.27 group */
@@ -830,7 +827,7 @@ setupPowerSettings(struct ath_hal *ah, HAL_CHANNEL *chan, uint8_t cp[17])
* vectors (as determined by the mode), and station configuration
*/
HAL_BOOL
-ar5210SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
static const uint32_t pwr_regs_start[17] = {
@@ -918,12 +915,13 @@ ar5210SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
* or by disabling the AGC.
*/
static HAL_BOOL
-ar5210SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t data;

/* Set the Channel */
- data = ath_hal_reverseBits((chan->channel - 5120)/10, 5);
+ data = ath_hal_reverseBits((freq - 5120)/10, 5);
data = (data << 1) | 0x41;
OS_REG_WRITE(ah, AR_PHY(0x27), data);
OS_REG_WRITE(ah, AR_PHY(0x30), 0);
@@ -950,7 +948,7 @@ ar5210GetNoiseFloor(struct ath_hal *ah)
* Returns: TRUE for a successful noise floor calibration; else FALSE
*/
HAL_BOOL
-ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
{
int32_t nf, nfLoops;

@@ -981,10 +979,10 @@ ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
if (nf > NORMAL_NF_THRESH) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n",
__func__, nf);
- chan->rawNoiseFloor = 0;
+ ichan->rawNoiseFloor = 0;
return AH_FALSE;
}
- chan->rawNoiseFloor = nf;
+ ichan->rawNoiseFloor = nf;
return AH_TRUE;
}

diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_xmit.c b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_xmit.c
index 40a8d80..3b880aa 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210_xmit.c
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210_xmit.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2004 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -154,7 +154,7 @@ HAL_BOOL
ar5210ResetTxQueue(struct ath_hal *ah, u_int q)
{
struct ath_hal_5210 *ahp = AH5210(ah);
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_TX_QUEUE_INFO *qi;
uint32_t cwMin;

@@ -177,7 +177,7 @@ ar5210ResetTxQueue(struct ath_hal *ah, u_int q)
return AH_TRUE;

/* Set turbo mode / base mode parameters on or off */
- if (IS_CHAN_TURBO(chan)) {
+ if (IEEE80211_IS_CHAN_TURBO(chan)) {
OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO);
OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO);
OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO);
diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5210phy.h b/sys/external/isc/atheros_hal/dist/ar5210/ar5210phy.h
index d029400..4ab3025 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5210phy.h
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5210phy.h
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5210phy.h,v 1.1.1.1 2008/12/11 04:46:29 alc Exp $
+ * $FreeBSD$
*/
#ifndef _DEV_ATH_AR5210PHY_H
#define _DEV_ATH_AR5210PHY_H
diff --git a/sys/external/isc/atheros_hal/dist/ar5210/ar5k_0007.ini b/sys/external/isc/atheros_hal/dist/ar5210/ar5k_0007.ini
index 353a47d..b536483 100644
--- a/sys/external/isc/atheros_hal/dist/ar5210/ar5k_0007.ini
+++ b/sys/external/isc/atheros_hal/dist/ar5210/ar5k_0007.ini
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5k_0007.ini,v 1.1.1.1 2008/12/11 04:46:30 alc Exp $
+ * $FreeBSD$
*/

/* crete register init */
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211.h b/sys/external/isc/atheros_hal/dist/ar5211/ar5211.h
index 5734795..85d9c5f 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211.h
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2006 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -123,7 +123,6 @@ struct ath_hal_5211 {
HAL_ANT_SETTING ah_diversityControl; /* antenna setting */
uint32_t ah_calibrationTime;
HAL_BOOL ah_bIQCalibration;
- HAL_CHANNEL ah_curchan; /* XXX */
int ah_rfgainState;
uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
@@ -145,24 +144,24 @@ struct ath_hal_5211 {

struct ath_hal;

-extern struct ath_hal *ar5211Attach(uint16_t, HAL_SOFTC,
- HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *);
extern void ar5211Detach(struct ath_hal *);

extern HAL_BOOL ar5211Reset(struct ath_hal *, HAL_OPMODE,
- HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *);
+ struct ieee80211_channel *, HAL_BOOL bChannelChange,
+ HAL_STATUS *);
extern HAL_BOOL ar5211PhyDisable(struct ath_hal *);
extern HAL_BOOL ar5211Disable(struct ath_hal *);
-extern HAL_BOOL ar5211ChipReset(struct ath_hal *, uint16_t);
-extern HAL_BOOL ar5211PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *);
-extern HAL_BOOL ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+extern HAL_BOOL ar5211ChipReset(struct ath_hal *,
+ const struct ieee80211_channel *);
+extern HAL_BOOL ar5211PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);
+extern HAL_BOOL ar5211PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
-extern HAL_BOOL ar5211ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern HAL_BOOL ar5211ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);
extern HAL_BOOL ar5211SetTxPowerLimit(struct ath_hal *, uint32_t limit);
-extern HAL_BOOL ar5211SetTransmitPower(struct ath_hal *, HAL_CHANNEL *);
-extern HAL_BOOL ar5211CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern HAL_BOOL ar5211CalNoiseFloor(struct ath_hal *,
+ const struct ieee80211_channel *);
extern HAL_BOOL ar5211SetAntennaSwitchInternal(struct ath_hal *,
- HAL_ANT_SETTING, const HAL_CHANNEL *);
+ HAL_ANT_SETTING, const struct ieee80211_channel *);
extern int16_t ar5211GetNfAdjust(struct ath_hal *,
const HAL_CHANNEL_INTERNAL *);
extern HAL_BOOL ar5211ResetDma(struct ath_hal *, HAL_OPMODE);
@@ -234,7 +233,8 @@ extern u_int ar5211GetWirelessModes(struct ath_hal *);
extern void ar5211EnableRfKill(struct ath_hal *);
extern uint32_t ar5211GpioGet(struct ath_hal *, uint32_t gpio);
extern void ar5211GpioSetIntr(struct ath_hal *, u_int, uint32_t ilevel);
-extern HAL_BOOL ar5211GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern HAL_BOOL ar5211GpioCfgOutput(struct ath_hal *, uint32_t gpio,
+ HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5211GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5211GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern void ar5211SetLedState(struct ath_hal *, HAL_LED_STATE);
@@ -284,7 +284,7 @@ extern HAL_BOOL ar5211SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
extern HAL_BOOL ar5211SetKeyCacheEntryMac(struct ath_hal *,
uint16_t, const uint8_t *);

-extern HAL_BOOL ar5211SetPowerMode(struct ath_hal *, HAL_POWER_MODE mode,
+extern HAL_BOOL ar5211SetPowerMode(struct ath_hal *, uint32_t powerRequest,
int setChip);
extern HAL_POWER_MODE ar5211GetPowerMode(struct ath_hal *);

@@ -303,6 +303,7 @@ extern HAL_INT ar5211SetInterrupts(struct ath_hal *, HAL_INT ints);
extern const HAL_RATE_TABLE *ar5211GetRateTable(struct ath_hal *, u_int mode);

extern HAL_BOOL ar5211AniControl(struct ath_hal *, HAL_ANI_CMD, int );
-extern void ar5211AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *);
+extern void ar5211AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
+ const struct ieee80211_channel *);
extern void ar5211MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
#endif /* _ATH_AR5211_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_attach.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_attach.c
index fca885a..bf6a87d 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_attach.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_attach.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2006 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -31,12 +31,13 @@
static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah,
uint16_t flags, uint16_t *low, uint16_t *high);
static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah,
- HAL_CHANNEL *chans, uint32_t nchans);
+ struct ieee80211_channel *chan);
+
+static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
+static void ar5211DisablePCIE(struct ath_hal *ah);

static const struct ath_hal_private ar5211hal = {{
.ah_magic = AR5211_MAGIC,
- .ah_abi = HAL_ABI_VERSION,
- .ah_countryCode = CTRY_DEFAULT,

.ah_getRateTable = ar5211GetRateTable,
.ah_detach = ar5211Detach,
@@ -45,6 +46,8 @@ static const struct ath_hal_private ar5211hal = {{
.ah_reset = ar5211Reset,
.ah_phyDisable = ar5211PhyDisable,
.ah_disable = ar5211Disable,
+ .ah_configPCIE = ar5211ConfigPCIE,
+ .ah_disablePCIE = ar5211DisablePCIE,
.ah_setPCUConfig = ar5211SetPCUConfig,
.ah_perCalibration = ar5211PerCalibration,
.ah_perCalibrationN = ar5211PerCalibrationN,
@@ -156,11 +159,6 @@ static const struct ath_hal_private ar5211hal = {{
#ifdef AH_SUPPORT_WRITE_EEPROM
.ah_eepromWrite = ar5211EepromWrite,
#endif
- .ah_gpioCfgInput = ar5211GpioCfgInput,
- .ah_gpioCfgOutput = ar5211GpioCfgOutput,
- .ah_gpioGet = ar5211GpioGet,
- .ah_gpioSet = ar5211GpioSet,
- .ah_gpioSetIntr = ar5211GpioSetIntr,
.ah_getChipPowerLimits = ar5211GetChipPowerLimits,
};

@@ -188,7 +186,7 @@ ar5211GetRadioRev(struct ath_hal *ah)
/*
* Attach for an AR5211 part.
*/
-struct ath_hal *
+static struct ath_hal *
ar5211Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
{
@@ -232,7 +230,7 @@ ar5211Attach(uint16_t devid, HAL_SOFTC sc,
ahp->ah_acktimeout = (u_int) -1;
ahp->ah_ctstimeout = (u_int) -1;

- if (!ar5211ChipReset(ah, AH_FALSE)) { /* reset chip */
+ if (!ar5211ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
goto bad;
@@ -420,12 +418,13 @@ static HAL_BOOL
ar5211GetChannelEdges(struct ath_hal *ah,
uint16_t flags, uint16_t *low, uint16_t *high)
{
- if (flags & CHANNEL_5GHZ) {
+ if (flags & IEEE80211_CHAN_5GHZ) {
*low = 4920;
*high = 6100;
return AH_TRUE;
}
- if (flags & CHANNEL_2GHZ && ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) {
+ if (flags & IEEE80211_CHAN_2GHZ &&
+ ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) {
*low = 2312;
*high = 2732;
return AH_TRUE;
@@ -434,23 +433,27 @@ ar5211GetChannelEdges(struct ath_hal *ah,
}

static HAL_BOOL
-ar5211GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)
{
- HAL_CHANNEL *chan;
- int i;
-
/* XXX fill in, this is just a placeholder */
- for (i = 0; i < nchans; i++) {
- chan = &chans[i];
- HALDEBUG(ah, HAL_DEBUG_ATTACH,
- "%s: no min/max power for %u/0x%x\n",
- __func__, chan->channel, chan->channelFlags);
- chan->maxTxPower = MAX_RATE_POWER;
- chan->minTxPower = 0;
- }
+ HALDEBUG(ah, HAL_DEBUG_ATTACH,
+ "%s: no min/max power for %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ chan->ic_maxpower = MAX_RATE_POWER;
+ chan->ic_minpower = 0;
return AH_TRUE;
}

+static void
+ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
+{
+}
+
+static void
+ar5211DisablePCIE(struct ath_hal *ah)
+{
+}
+
/*
* Fill all software cached or static hardware state information.
*/
@@ -495,6 +498,13 @@ ar5211FillCapabilityInfo(struct ath_hal *ah)
}

pCap->halTstampPrecision = 13;
+ pCap->halIntrMask = HAL_INT_COMMON
+ | HAL_INT_RX
+ | HAL_INT_TX
+ | HAL_INT_FATAL
+ | HAL_INT_BNR
+ | HAL_INT_TIM
+ ;

/* XXX might be ok w/ some chip revs */
ahpriv->ah_rxornIsFatal = AH_TRUE;
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_beacon.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_beacon.c
index 6bdb7d8..7a05e04 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_beacon.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_beacon.c
@@ -55,8 +55,6 @@ ar5211BeaconInit(struct ath_hal *ah,
{
HAL_BEACON_TIMERS bt;

- bt.bt_nextdba = 0;
- bt.bt_nextswba = 0;
bt.bt_nexttbtt = next_beacon;
/*
* TIMER1: in AP/adhoc mode this controls the DMA beacon
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_keycache.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_keycache.c
index 9f39f06..3e0f922 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_keycache.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_keycache.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5211_keycache.c,v 1.1.1.1 2008/12/11 04:46:31 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_misc.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_misc.c
index 04d68a9..cc83c21 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_misc.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_misc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2006 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -192,7 +192,7 @@ ar5211EnableRfKill(struct ath_hal *ah)
* Configure GPIO Output lines
*/
HAL_BOOL
-ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
uint32_t reg;

@@ -564,7 +564,8 @@ ar5211AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
}

void
-ar5211AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats, HAL_CHANNEL *chan)
+ar5211AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
+ const struct ieee80211_channel *chan)
{
}

@@ -603,8 +604,7 @@ ar5211GetAntennaSwitch(struct ath_hal *ah)
HAL_BOOL
ar5211SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
{
- const HAL_CHANNEL *chan =
- (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

if (chan == AH_NULL) {
AH5211(ah)->ah_diversityControl = settings;
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_phy.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_phy.c
index 1883776..d4849bf 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_phy.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_phy.c
@@ -34,14 +34,14 @@ HAL_RATE_TABLE ar5211_11a_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4, 0, 0 }
+/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 },
+/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 },
+/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }
},
};

@@ -51,14 +51,14 @@ HAL_RATE_TABLE ar5211_turbo_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, TURBO, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, TURBO, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, TURBO, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, TURBO, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, TURBO, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, TURBO, 36000, 0x0d, 0x00, 72, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, TURBO, 48000, 0x08, 0x00, 96, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, TURBO, 54000, 0x0c, 0x00, 108, 4, 0, 0 }
+/* 6 Mb */ { AH_TRUE, TURBO, 12000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, TURBO, 18000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, TURBO, 24000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, TURBO, 36000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, TURBO, 48000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, TURBO, 72000, 0x0d, 0x00, 72, 4 },
+/* 48 Mb */ { AH_TRUE, TURBO, 96000, 0x08, 0x00, 96, 4 },
+/* 54 Mb */ { AH_TRUE, TURBO, 108000, 0x0c, 0x00, 108, 4 }
},
};

@@ -68,10 +68,10 @@ HAL_RATE_TABLE ar5211_11b_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x0b, 0x00, (0x80| 2), 0, 0, 0 },
-/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x0a, 0x04, (0x80| 4), 1, 0, 0 },
-/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x09, 0x04, (0x80|11), 1, 0, 0 },
-/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x08, 0x04, (0x80|22), 1, 0, 0 }
+/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x0b, 0x00, (0x80| 2), 0 },
+/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x0a, 0x04, (0x80| 4), 1 },
+/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x09, 0x04, (0x80|11), 1 },
+/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x08, 0x04, (0x80|22), 1 }
},
};

diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_recv.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_recv.c
index 903f95b..733559e 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_recv.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_recv.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5211_recv.c,v 1.1.1.1 2008/12/11 04:46:33 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c
index c2b6472..588e6fa 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2006 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -46,7 +46,7 @@ typedef struct {
} CHAN_INFO_2GHZ;

#define CI_2GHZ_INDEX_CORRECTION 19
-static const CHAN_INFO_2GHZ chan2GHzData[] = {
+const static CHAN_INFO_2GHZ chan2GHzData[] = {
{ 1, 0x46, 96 }, /* 2312 -19 */
{ 1, 0x46, 97 }, /* 2317 -18 */
{ 1, 0x46, 98 }, /* 2322 -17 */
@@ -105,17 +105,23 @@ static const CHAN_INFO_2GHZ chan2GHzData[] = {
#define NUM_RATES 8

static HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask);
-static HAL_BOOL ar5211SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+static HAL_BOOL ar5211SetChannel(struct ath_hal *,
+ const struct ieee80211_channel *);
static int16_t ar5211RunNoiseFloor(struct ath_hal *,
uint8_t runTime, int16_t startingNF);
-static HAL_BOOL ar5211IsNfGood(struct ath_hal *, HAL_CHANNEL_INTERNAL *chan);
-static HAL_BOOL ar5211SetRf6and7(struct ath_hal *, HAL_CHANNEL *chan);
-static HAL_BOOL ar5211SetBoardValues(struct ath_hal *, HAL_CHANNEL *chan);
+static HAL_BOOL ar5211IsNfGood(struct ath_hal *,
+ struct ieee80211_channel *chan);
+static HAL_BOOL ar5211SetRf6and7(struct ath_hal *,
+ const struct ieee80211_channel *chan);
+static HAL_BOOL ar5211SetBoardValues(struct ath_hal *,
+ const struct ieee80211_channel *chan);
static void ar5211SetPowerTable(struct ath_hal *,
PCDACS_EEPROM *pSrcStruct, uint16_t channel);
+static HAL_BOOL ar5211SetTransmitPower(struct ath_hal *,
+ const struct ieee80211_channel *);
static void ar5211SetRateTable(struct ath_hal *,
RD_EDGES_POWER *pRdEdgesPower, TRGT_POWER_INFO *pPowerInfo,
- uint16_t numChannels, HAL_CHANNEL *chan);
+ uint16_t numChannels, const struct ieee80211_channel *chan);
static uint16_t ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue,
const PCDACS_EEPROM *pSrcStruct);
static HAL_BOOL ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
@@ -130,7 +136,7 @@ static void ar5211GetLowerUpperPcdacs(uint16_t pcdac,
uint16_t channel, const PCDACS_EEPROM *pSrcStruct,
uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);

-static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);;
+static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);
static void ar5211RequestRfgain(struct ath_hal *);
static HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *);
static HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *);
@@ -147,7 +153,8 @@ static void ar5211SetOperatingMode(struct ath_hal *, int opmode);
*/
HAL_BOOL
ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+ struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
+ HAL_STATUS *status)
{
uint32_t softLedCfg, softLedState;
#define N(a) (sizeof (a) /sizeof (a[0]))
@@ -167,34 +174,16 @@ uint32_t softLedCfg, softLedState;

HALDEBUG(ah, HAL_DEBUG_RESET,
"%s: opmode %u channel %u/0x%x %s channel\n",
- __func__, opmode, chan->channel, chan->channelFlags,
+ __func__, opmode, chan->ic_freq, chan->ic_flags,
bChannelChange ? "change" : "same");

OS_MARK(ah, AH_MARK_RESET, bChannelChange);
-#define IS(_c,_f) (((_c)->channelFlags & _f) || 0)
- if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan,CHANNEL_5GHZ)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
- if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
-#undef IS
/*
* Map public channel to private.
*/
ichan = ath_hal_checkchannel(ah, chan);
- if (ichan == AH_NULL) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ if (ichan == AH_NULL)
FAIL(HAL_EINVAL);
- }
switch (opmode) {
case HAL_M_STA:
case HAL_M_IBSS:
@@ -236,10 +225,8 @@ uint32_t softLedCfg, softLedState;
for (i = 0; i < AR_NUM_DCU; i++)
saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i));
}
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
+ if (!IEEE80211_IS_CHAN_DFS(chan))
+ chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
}

/*
@@ -259,33 +246,36 @@ uint32_t softLedCfg, softLedState;
softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
softLedState = OS_REG_READ(ah, AR_GPIODO);

- if (!ar5211ChipReset(ah, chan->channelFlags)) {
+ if (!ar5211ChipReset(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
FAIL(HAL_EIO);
}

/* Setup the indices for the next set of register array writes */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- modesIndex = 1;
- freqIndex = 1;
- break;
- case CHANNEL_T:
- modesIndex = 2;
- freqIndex = 1;
- break;
- case CHANNEL_B:
- modesIndex = 3;
- freqIndex = 2;
- break;
- case CHANNEL_PUREG:
- modesIndex = 4;
- freqIndex = 2;
- break;
- default:
- /* Ah, a new wireless mode */
- HALASSERT(0);
- break;
+ if (IEEE80211_IS_CHAN_5GHZ(chan)) {
+ freqIndex = 1;
+ if (IEEE80211_IS_CHAN_TURBO(chan))
+ modesIndex = 2;
+ else if (IEEE80211_IS_CHAN_A(chan))
+ modesIndex = 1;
+ else {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: invalid channel %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ FAIL(HAL_EINVAL);
+ }
+ } else {
+ freqIndex = 2;
+ if (IEEE80211_IS_CHAN_B(chan))
+ modesIndex = 3;
+ else if (IEEE80211_IS_CHAN_PUREG(chan))
+ modesIndex = 4;
+ else {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: invalid channel %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ FAIL(HAL_EINVAL);
+ }
}

/* Set correct Baseband to analog shift setting to access analog chips. */
@@ -297,12 +287,12 @@ uint32_t softLedCfg, softLedState;

/* Write parameters specific to AR5211 */
if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
- if (IS_CHAN_2GHZ(chan) &&
+ if (IEEE80211_IS_CHAN_2GHZ(chan) &&
AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) {
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint32_t ob2GHz, db2GHz;

- if (IS_CHAN_CCK(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
ob2GHz = ee->ee_ob2GHz[0];
db2GHz = ee->ee_db2GHz[0];
} else {
@@ -437,14 +427,15 @@ uint32_t softLedCfg, softLedState;
/* Setup board specific options for EEPROM version 3 */
ar5211SetBoardValues(ah, chan);

- if (!ar5211SetChannel(ah, ichan)) {
+ if (!ar5211SetChannel(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
__func__);
FAIL(HAL_EIO);
}

/* Activate the PHY */
- if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B && IS_CHAN_2GHZ(chan))
+ if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B &&
+ IEEE80211_IS_CHAN_2GHZ(chan))
OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */
OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

@@ -454,7 +445,7 @@ uint32_t softLedCfg, softLedState;
* Value is in 100ns increments.
*/
data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M;
- if (IS_CHAN_CCK(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
synthDelay = (4 * data) / 22;
} else {
synthDelay = data / 10;
@@ -473,9 +464,9 @@ uint32_t softLedCfg, softLedState;
(void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);

/* Perform noise floor and set status */
- if (!ar5211CalNoiseFloor(ah, ichan)) {
- if (!IS_CHAN_CCK(chan))
- chan->channelFlags |= CHANNEL_CW_INT;
+ if (!ar5211CalNoiseFloor(ah, chan)) {
+ if (!IEEE80211_IS_CHAN_CCK(chan))
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: noise floor calibration failed\n", __func__);
FAIL(HAL_EIO);
@@ -552,7 +543,7 @@ uint32_t softLedCfg, softLedState;

return AH_TRUE;
bad:
- if (*status)
+ if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
@@ -599,49 +590,31 @@ ar5211Disable(struct ath_hal *ah)
* us in the correct mode and we cannot check the hwchannel flags.
*/
HAL_BOOL
-ar5211ChipReset(struct ath_hal *ah, uint16_t channelFlags)
+ar5211ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
return AH_FALSE;

- /* Set CCK and Turbo modes correctly */
- switch (channelFlags & CHANNEL_ALL) {
- case CHANNEL_2GHZ|CHANNEL_CCK:
- case CHANNEL_2GHZ|CHANNEL_CCK|CHANNEL_TURBO:
- OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
- OS_REG_WRITE(ah, AR5211_PHY_MODE,
- AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ);
- OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
- /* Wait for the PLL to settle */
- OS_DELAY(DELAY_PLL_SETTLE);
- break;
- case CHANNEL_2GHZ|CHANNEL_OFDM:
- case CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO:
- OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
- if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
- OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
- OS_DELAY(DELAY_PLL_SETTLE);
+ /* NB: called from attach with chan null */
+ if (chan != AH_NULL) {
+ /* Set CCK and Turbo modes correctly */
+ OS_REG_WRITE(ah, AR_PHY_TURBO, IEEE80211_IS_CHAN_TURBO(chan) ?
+ AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT : 0);
+ if (IEEE80211_IS_CHAN_B(chan)) {
OS_REG_WRITE(ah, AR5211_PHY_MODE,
- AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF2GHZ);
- }
- break;
- case CHANNEL_A:
- case CHANNEL_T:
- if (channelFlags & CHANNEL_TURBO) {
- OS_REG_WRITE(ah, AR_PHY_TURBO,
- AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT);
- } else { /* 5 GHZ OFDM Mode */
- OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
- }
- if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
+ AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ);
+ OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
+ /* Wait for the PLL to settle */
+ OS_DELAY(DELAY_PLL_SETTLE);
+ } else if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
OS_DELAY(DELAY_PLL_SETTLE);
OS_REG_WRITE(ah, AR5211_PHY_MODE,
- AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF5GHZ);
+ AR5211_PHY_MODE_OFDM | (IEEE80211_IS_CHAN_2GHZ(chan) ?
+ AR5211_PHY_MODE_RF2GHZ :
+ AR5211_PHY_MODE_RF5GHZ));
}
- break;
}
- /* NB: else no flags set - must be attach calling - do nothing */

/*
* Reset the HW - PCI must be reset after the rest of the
@@ -664,8 +637,8 @@ ar5211ChipReset(struct ath_hal *ah, uint16_t channelFlags)
* changes.
*/
HAL_BOOL
-ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
- HAL_BOOL longCal, HAL_BOOL *isCalDone)
+ar5211PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
+ u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone)
{
struct ath_hal_5211 *ahp = AH5211(ah);
HAL_CHANNEL_INTERNAL *ichan;
@@ -679,7 +652,7 @@ ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
return AH_FALSE;
}
/* IQ calibration in progress. Check to see if it has finished. */
@@ -733,22 +706,21 @@ ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,

if (longCal) {
/* Perform noise floor and set status */
- if (!ar5211IsNfGood(ah, ichan)) {
+ if (!ar5211IsNfGood(ah, chan)) {
/* report up and clear internal state */
- chan->channelFlags |= CHANNEL_CW_INT;
- ichan->channelFlags &= ~CHANNEL_CW_INT;
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
return AH_FALSE;
}
- if (!ar5211CalNoiseFloor(ah, ichan)) {
+ if (!ar5211CalNoiseFloor(ah, chan)) {
/*
* Delay 5ms before retrying the noise floor
* just to make sure, as we are in an error
* condition here.
*/
OS_DELAY(5000);
- if (!ar5211CalNoiseFloor(ah, ichan)) {
- if (!IS_CHAN_CCK(chan))
- chan->channelFlags |= CHANNEL_CW_INT;
+ if (!ar5211CalNoiseFloor(ah, chan)) {
+ if (!IEEE80211_IS_CHAN_CCK(chan))
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
return AH_FALSE;
}
}
@@ -758,13 +730,14 @@ ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
}

HAL_BOOL
-ar5211PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+ar5211PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
+ HAL_BOOL *isIQdone)
{
return ar5211PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
}

HAL_BOOL
-ar5211ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5211ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
/* XXX */
return AH_TRUE;
@@ -810,13 +783,13 @@ ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)
* or by disabling the AGC.
*/
static HAL_BOOL
-ar5211SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5211SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t refClk, reg32, data2111;
int16_t chan5111, chanIEEE;

- chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
- if (IS_CHAN_2GHZ(chan)) {
+ chanIEEE = chan->ic_ieee;
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
const CHAN_INFO_2GHZ* ci =
&chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];

@@ -903,7 +876,7 @@ ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)
if (i >= 60) {
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF with runTime %d failed to end on channel %d\n",
- runTime, AH_PRIVATE(ah)->ah_curchan->channel);
+ runTime, AH_PRIVATE(ah)->ah_curchan->ic_freq);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
" PHY NF Reg state: 0x%x\n",
OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
@@ -917,23 +890,24 @@ ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)
}

static HAL_BOOL
-getNoiseFloorThresh(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int16_t *nft)
+getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan,
+ int16_t *nft)
{
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
*nft = ee->ee_noiseFloorThresh[0];
break;
- case CHANNEL_CCK|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_B:
*nft = ee->ee_noiseFloorThresh[1];
break;
- case CHANNEL_OFDM|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_PUREG:
*nft = ee->ee_noiseFloorThresh[2];
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}
return AH_TRUE;
@@ -945,17 +919,16 @@ getNoiseFloorThresh(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int16_t *nft
* Returns: TRUE if the NF is good
*/
static HAL_BOOL
-ar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5211IsNfGood(struct ath_hal *ah, struct ieee80211_channel *chan)
{
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int16_t nf, nfThresh;

if (!getNoiseFloorThresh(ah, chan, &nfThresh))
return AH_FALSE;
-#ifdef AH_DEBUG
if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: NF did not complete in calibration window\n", __func__);
-#endif
nf = ar5211GetNoiseFloor(ah);
if (nf > nfThresh) {
HALDEBUG(ah, HAL_DEBUG_ANY,
@@ -966,9 +939,9 @@ ar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* happens it indicates a problem regardless
* of the band.
*/
- chan->channelFlags |= CHANNEL_CW_INT;
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
}
- chan->rawNoiseFloor = nf;
+ ichan->rawNoiseFloor = nf;
return (nf <= nfThresh);
}

@@ -982,13 +955,14 @@ ar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* Returns: TRUE for a successful noise floor calibration; else FALSE
*/
HAL_BOOL
-ar5211CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5211CalNoiseFloor(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
/* Check for Carrier Wave interference in MKK regulatory zone */
if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU &&
- ath_hal_getnfcheckrequired(ah, (HAL_CHANNEL *) chan)) {
+ (chan->ic_flags & CHANNEL_NFCREQUIRED)) {
static const uint8_t runtime[3] = { 0, 2, 7 };
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int16_t nf, nfThresh;
int i;

@@ -1005,9 +979,9 @@ ar5211CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
"%s: run failed with %u > threshold %u "
"(runtime %u)\n", __func__,
nf, nfThresh, runtime[i]);
- chan->rawNoiseFloor = 0;
+ ichan->rawNoiseFloor = 0;
} else
- chan->rawNoiseFloor = nf;
+ ichan->rawNoiseFloor = nf;
}
return (i <= N(runtime));
} else {
@@ -1056,9 +1030,10 @@ ar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
* REQUIRES: Access to the analog device
*/
static HAL_BOOL
-ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5211SetRf6and7(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
struct ath_hal_5211 *ahp = AH5211(ah);
uint16_t rfXpdGain, rfPloSel, rfPwdXpd;
@@ -1066,25 +1041,25 @@ ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
uint16_t freqIndex;
int i;

- freqIndex = (chan->channelFlags & CHANNEL_2GHZ) ? 2 : 1;
+ freqIndex = IEEE80211_IS_CHAN_2GHZ(chan) ? 2 : 1;

/*
* TODO: This array mode correspondes with the index used
* during the read.
* For readability, this should be changed to an enum or #define
*/
- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A:
- if (chan->channel > 4000 && chan->channel < 5260) {
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
+ if (freq > 4000 && freq < 5260) {
tempOB = ee->ee_ob1;
tempDB = ee->ee_db1;
- } else if (chan->channel >= 5260 && chan->channel < 5500) {
+ } else if (freq >= 5260 && freq < 5500) {
tempOB = ee->ee_ob2;
tempDB = ee->ee_db2;
- } else if (chan->channel >= 5500 && chan->channel < 5725) {
+ } else if (freq >= 5500 && freq < 5725) {
tempOB = ee->ee_ob3;
tempDB = ee->ee_db3;
- } else if (chan->channel >= 5725) {
+ } else if (freq >= 5725) {
tempOB = ee->ee_ob4;
tempDB = ee->ee_db4;
} else {
@@ -1106,14 +1081,14 @@ ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
(ar5211Rf6n7[21][freqIndex] & ~0x08) |
(ee->ee_cornerCal.gSel << 3);
break;
- case CHANNEL_CCK|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_B:
tempOB = ee->ee_obFor24;
tempDB = ee->ee_dbFor24;
rfXpdGain = ee->ee_xgain[1];
rfPloSel = ee->ee_xpd[1];
rfPwdXpd = !ee->ee_xpd[1];
break;
- case CHANNEL_OFDM|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_PUREG:
tempOB = ee->ee_obFor24g;
tempDB = ee->ee_dbFor24g;
rfXpdGain = ee->ee_xgain[2];
@@ -1122,7 +1097,7 @@ ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -1162,7 +1137,7 @@ ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)

HAL_BOOL
ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
- const HAL_CHANNEL *chan)
+ const struct ieee80211_channel *chan)
{
#define ANT_SWITCH_TABLE1 0x9960
#define ANT_SWITCH_TABLE2 0x9964
@@ -1171,13 +1146,13 @@ ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
uint32_t antSwitchA, antSwitchB;
int ix;

- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A: ix = 0; break;
- case CHANNEL_B: ix = 1; break;
- case CHANNEL_PUREG: ix = 2; break;
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A: ix = 0; break;
+ case IEEE80211_CHAN_B: ix = 1; break;
+ case IEEE80211_CHAN_PUREG: ix = 2; break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -1225,27 +1200,27 @@ ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
* given the channel value
*/
static HAL_BOOL
-ar5211SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5211SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
struct ath_hal_5211 *ahp = AH5211(ah);
int arrayMode, falseDectectBackoff;

- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
arrayMode = 0;
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
AR_PHY_FRAME_CTL_TX_CLIP, ee->ee_cornerCal.clip);
break;
- case CHANNEL_CCK|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_B:
arrayMode = 1;
break;
- case CHANNEL_OFDM|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_PUREG:
arrayMode = 2;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -1297,10 +1272,11 @@ ar5211SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *chan)
falseDectectBackoff = NO_FALSE_DETECT_BACKOFF;
if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) {
if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
- IS_CHAN_OFDM(chan))
+ IEEE80211_IS_CHAN_OFDM(chan))
falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
} else {
- uint32_t remainder = chan->channel % 32;
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
+ uint32_t remainder = freq % 32;

if (remainder && (remainder < 10 || remainder > 22))
falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
@@ -1333,9 +1309,10 @@ ar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
* Sets the transmit power in the baseband for the given
* operating channel and mode.
*/
-HAL_BOOL
-ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
+static HAL_BOOL
+ar5211SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
TRGT_POWER_INFO *pi;
RD_EDGES_POWER *rep;
@@ -1344,22 +1321,22 @@ ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
int i;

/* setup the pcdac struct to point to the correct info, based on mode */
- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
eepromPcdacs.numChannels = ee->ee_numChannels11a;
eepromPcdacs.pChannelList= ee->ee_channels11a;
eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
nchan = ee->ee_numTargetPwr_11a;
pi = ee->ee_trgtPwr_11a;
break;
- case CHANNEL_OFDM|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_PUREG:
eepromPcdacs.numChannels = ee->ee_numChannels2_4;
eepromPcdacs.pChannelList= ee->ee_channels11g;
eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
nchan = ee->ee_numTargetPwr_11g;
pi = ee->ee_trgtPwr_11g;
break;
- case CHANNEL_CCK|CHANNEL_2GHZ:
+ case IEEE80211_CHAN_B:
eepromPcdacs.numChannels = ee->ee_numChannels2_4;
eepromPcdacs.pChannelList= ee->ee_channels11b;
eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
@@ -1368,11 +1345,11 @@ ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

- ar5211SetPowerTable(ah, &eepromPcdacs, chan->channel);
+ ar5211SetPowerTable(ah, &eepromPcdacs, freq);

rep = AH_NULL;
/* Match CTL to EEPROM value */
@@ -1394,7 +1371,8 @@ ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
* table for writing into the hardware.
*/
void
-ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, uint16_t channel)
+ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct,
+ uint16_t channel)
{
static FULL_PCDAC_STRUCT pcdacStruct;
static uint16_t pcdacTable[PWR_TABLE_SIZE];
@@ -1511,11 +1489,12 @@ ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, uint16_t chan
* Set the transmit power in the baseband for the given
* operating channel and mode.
*/
-void
+static void
ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels,
- HAL_CHANNEL *chan)
+ const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
struct ath_hal_5211 *ahp = AH5211(ah);
static uint16_t ratesArray[NUM_RATES];
@@ -1523,8 +1502,8 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
{ 0, 3, 6, 9, MAX_RATE_POWER };

uint16_t *pRatesPower;
- uint16_t lowerChannel = 0, lowerIndex=0, lowerPower=0;
- uint16_t upperChannel = 0, upperIndex=0, upperPower=0;
+ uint16_t lowerChannel, lowerIndex=0, lowerPower=0;
+ uint16_t upperChannel, upperIndex=0, upperPower=0;
uint16_t twiceMaxEdgePower=63;
uint16_t twicePower = 0;
uint16_t i, numEdges;
@@ -1536,9 +1515,9 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
int8_t twiceAntennaGain, twiceAntennaReduction = 0;

pRatesPower = ratesArray;
- twiceMaxRDPower = chan->maxRegTxPower * 2;
+ twiceMaxRDPower = chan->ic_maxregpower * 2;

- if (IS_CHAN_5GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_5GHZ(chan)) {
twiceAntennaGain = ee->ee_antennaGainMax[0];
} else {
twiceAntennaGain = ee->ee_antennaGainMax[1];
@@ -1555,7 +1534,7 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
}
numEdges = i;

- ar5211GetLowerUpperValues(chan->channel, tempChannelList,
+ ar5211GetLowerUpperValues(freq, tempChannelList,
numEdges, &lowerChannel, &upperChannel);
/* Get the index for this channel */
for (i = 0; i < numEdges; i++)
@@ -1564,7 +1543,7 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
HALASSERT(i != numEdges);

if ((lowerChannel == upperChannel &&
- lowerChannel == chan->channel) ||
+ lowerChannel == freq) ||
pRdEdgesPower[i].flag) {
twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower;
HALASSERT(twiceMaxEdgePower > 0);
@@ -1575,7 +1554,7 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
for (i = 0; i < numChannels; i++)
tempChannelList[i] = pPowerInfo[i].testChannel;

- ar5211GetLowerUpperValues(chan->channel, tempChannelList,
+ ar5211GetLowerUpperValues(freq, tempChannelList,
numChannels, &lowerChannel, &upperChannel);

/* get the index for the channel */
@@ -1589,7 +1568,7 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
}

for (i = 0; i < NUM_RATES; i++) {
- if (IS_CHAN_OFDM(chan)) {
+ if (IEEE80211_IS_CHAN_OFDM(chan)) {
/* power for rates 6,9,12,18,24 is all the same */
if (i < 5) {
lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
@@ -1629,7 +1608,7 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
}
}

- twicePower = ar5211GetInterpolatedValue(chan->channel,
+ twicePower = ar5211GetInterpolatedValue(freq,
lowerChannel, upperChannel, lowerPower, upperPower, 0);

/* Reduce power by band edge restrictions */
@@ -1641,7 +1620,7 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
* this unless specially configured. Then we limit
* power only for non-AP operation.
*/
- if (IS_CHAN_TURBO(chan) &&
+ if (IEEE80211_IS_CHAN_TURBO(chan) &&
AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1
#ifdef AH_ENABLE_AP_SUPPORT
&& AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
@@ -1671,14 +1650,14 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_RESET,
"%s: final output power setting %d MHz:\n",
- __func__, chan->channel);
+ __func__, chan->ic_freq);
HALDEBUG(ah, HAL_DEBUG_RESET,
"6 Mb %d dBm, MaxRD: %d dBm, MaxEdge %d dBm\n",
scaledPower / 2, twiceMaxRDPower / 2, twiceMaxEdgePower / 2);
HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n",
tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2,
twiceAntennaReduction / 2);
- if (IS_CHAN_TURBO(chan) &&
+ if (IEEE80211_IS_CHAN_TURBO(chan) &&
AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1)
HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n",
ee->ee_turbo2WMaxPower5);
@@ -1711,13 +1690,14 @@ ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
* Get or interpolate the pcdac value from the calibrated data
*/
uint16_t
-ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, const PCDACS_EEPROM *pSrcStruct)
+ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue,
+ const PCDACS_EEPROM *pSrcStruct)
{
uint16_t powerValue;
- uint16_t lFreq = 0, rFreq = 0; /* left and right frequency values */
- uint16_t llPcdac = 0, ulPcdac = 0; /* lower and upper left pcdac values */
- uint16_t lrPcdac = 0, urPcdac = 0; /* lower and upper right pcdac values */
- uint16_t lPwr = 0, uPwr = 0; /* lower and upper temp pwr values */
+ uint16_t lFreq, rFreq; /* left and right frequency values */
+ uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */
+ uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */
+ uint16_t lPwr, uPwr; /* lower and upper temp pwr values */
uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */

if (ar5211FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue))
@@ -1942,11 +1922,11 @@ ar5211InitializeGainValues(struct ath_hal *ah)
static HAL_BOOL
ar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)
{
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
uint32_t gStep, g;
uint32_t L1, L2, L3, L4;

- if (IS_CHAN_CCK(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
gStep = 0x18;
L1 = 0;
L2 = gStep + 4;
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_xmit.c b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_xmit.c
index dd7d639..449db0b 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211_xmit.c
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211_xmit.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2006 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -233,7 +233,7 @@ HAL_BOOL
ar5211ResetTxQueue(struct ath_hal *ah, u_int q)
{
struct ath_hal_5211 *ahp = AH5211(ah);
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_TX_QUEUE_INFO *qi;
uint32_t cwMin, chanCwMin, value;

@@ -254,7 +254,7 @@ ar5211ResetTxQueue(struct ath_hal *ah, u_int q)
* Select cwmin according to channel type.
* NB: chan can be NULL during attach
*/
- if (chan && IS_CHAN_B(chan))
+ if (chan && IEEE80211_IS_CHAN_B(chan))
chanCwMin = INIT_CWMIN_11B;
else
chanCwMin = INIT_CWMIN;
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/ar5211phy.h b/sys/external/isc/atheros_hal/dist/ar5211/ar5211phy.h
index fb39429..bf5b67e 100644
--- a/sys/external/isc/atheros_hal/dist/ar5211/ar5211phy.h
+++ b/sys/external/isc/atheros_hal/dist/ar5211/ar5211phy.h
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5211phy.h,v 1.1.1.1 2008/12/11 04:46:34 alc Exp $
+ * $FreeBSD$
*/
#ifndef _DEV_ATH_AR5211PHY_H
#define _DEV_ATH_AR5211PHY_H
diff --git a/sys/external/isc/atheros_hal/dist/ar5211/boss.ini b/sys/external/isc/atheros_hal/dist/ar5211/boss.ini
index b1b5797..e054436 100755
--- a/sys/external/isc/atheros_hal/dist/ar5211/boss.ini
+++ b/sys/external/isc/atheros_hal/dist/ar5211/boss.ini
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: boss.ini,v 1.1.1.1 2008/12/11 04:46:35 alc Exp $
+ * $FreeBSD$
*/
/* Auto Generated PCI Register Writes. Created: 09/12/02 */

diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar2316.c b/sys/external/isc/atheros_hal/dist/ar5212/ar2316.c
index 4d526d5..318e629 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar2316.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar2316.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -88,28 +88,29 @@ ar2316WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar2316SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar2316SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- if (chan->channel < 4800) {
+ if (freq < 4800) {
uint32_t txctl;

- if (((chan->channel - 2192) % 5) == 0) {
- channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+ if (((freq - 2192) % 5) == 0) {
+ channelSel = ((freq - 672) * 2 - 3040)/10;
bModeSynth = 0;
- } else if (((chan->channel - 2224) % 5) == 0) {
- channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+ } else if (((freq - 2224) % 5) == 0) {
+ channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -117,7 +118,7 @@ ar2316SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
channelSel = ath_hal_reverseBits(channelSel, 8);

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -125,21 +126,21 @@ ar2316SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
- } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+ } else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 20 << 2), 8);
+ ((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(3, 2);
- } else if ((chan->channel % 10) == 0) {
+ } else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 10 << 1), 8);
+ ((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(2, 2);
- } else if ((chan->channel % 5) == 0) {
+ } else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
- (chan->channel - 4800) / 5, 8);
+ (freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -161,7 +162,8 @@ ar2316SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+ar2316SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
+ uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
@@ -174,27 +176,18 @@ ar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
struct ar2316State *priv = AR2316(ah);
int regWrites = 0;

- HALDEBUG(ah, HAL_DEBUG_RFPARAM,
- "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
- __func__, chan->channel, chan->channelFlags, modesIndex);
+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);

HALASSERT(priv != AH_NULL);

/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_B:
+ if (IEEE80211_IS_CHAN_B(chan)) {
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
- break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ } else {
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- return AH_FALSE;
}

/* Bank 1 Write */
@@ -308,7 +301,7 @@ ar2316FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
uint16_t ii, jj, kk;
int16_t currPwr = (int16_t)(2*Pmin);
/* since Pmin is pwr*2 and pwrList is 4*pwr */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;

ii = 0;
jj = 0;
@@ -373,7 +366,7 @@ ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
#define VpdTable_I priv->vpdTable_I
uint32_t ii, jj, kk;
int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;
uint32_t numPdGainsUsed = 0;
/*
* If desired to support -ve power levels in future, just
@@ -507,7 +500,8 @@ ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

static HAL_BOOL
ar2316SetPowerTable(struct ath_hal *ah,
- int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *minPower, int16_t *maxPower,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
struct ath_hal_5212 *ahp = AH5212(ah);
@@ -524,11 +518,11 @@ ar2316SetPowerTable(struct ath_hal *ah,
#endif

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
- __func__, chan->channel,chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
@@ -646,9 +640,11 @@ ar2316GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)
}

static HAL_BOOL
-ar2316GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar2316GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
+ uint16_t freq = chan->ic_freq; /* NB: never mapped */
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;
const RAW_DATA_PER_CHANNEL_2316 *data=AH_NULL;
@@ -657,9 +653,9 @@ ar2316GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,

*maxPow = 0;

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else
return(AH_FALSE);
@@ -673,9 +669,9 @@ ar2316GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
if (numChannels < 1)
return(AH_FALSE);

- if ((chan->channel < data[0].channelValue) ||
- (chan->channel > data[numChannels-1].channelValue)) {
- if (chan->channel < data[0].channelValue) {
+ if ((freq < data[0].channelValue) ||
+ (freq > data[numChannels-1].channelValue)) {
+ if (freq < data[0].channelValue) {
*maxPow = ar2316GetMaxPower(ah, &data[0]);
*minPow = ar2316GetMinPower(ah, &data[0]);
return(AH_TRUE);
@@ -687,19 +683,19 @@ ar2316GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
}

/* Linearly interpolate the power value now */
- for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+ for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
last = i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = ar2316GetMaxPower(ah, &data[i]) - ar2316GetMaxPower(ah, &data[last]);
- *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) +
+ *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
ar2316GetMaxPower(ah, &data[last])*totalD)/totalD);
totalMin = ar2316GetMinPower(ah, &data[i]) - ar2316GetMinPower(ah, &data[last]);
- *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+ *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
ar2316GetMinPower(ah, &data[last])*totalD)/totalD);
return(AH_TRUE);
} else {
- if (chan->channel == data[i].channelValue) {
+ if (freq == data[i].channelValue) {
*maxPow = ar2316GetMaxPower(ah, &data[i]);
*minPow = ar2316GetMinPower(ah, &data[i]);
return(AH_TRUE);
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar2317.c b/sys/external/isc/atheros_hal/dist/ar5212/ar2317.c
index c0b988c..5418fdc 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar2317.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar2317.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -19,7 +19,6 @@
#include "opt_ah.h"

#include "ah.h"
-#include "ah_devid.h"
#include "ah_internal.h"

#include "ar5212/ar5212.h"
@@ -80,22 +79,23 @@ ar2317WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar2317SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar2317SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- if (chan->channel < 4800) {
+ if (freq < 4800) {
uint32_t txctl;
- channelSel = chan->channel - 2272 ;
+ channelSel = freq - 2272 ;
channelSel = ath_hal_reverseBits(channelSel, 8);

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -103,21 +103,21 @@ ar2317SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
- } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+ } else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 20 << 2), 8);
+ ((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(3, 2);
- } else if ((chan->channel % 10) == 0) {
+ } else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 10 << 1), 8);
+ ((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(2, 2);
- } else if ((chan->channel % 5) == 0) {
+ } else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
- (chan->channel - 4800) / 5, 8);
+ (freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -139,7 +139,9 @@ ar2317SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar2317SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+ar2317SetRfRegs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
@@ -152,27 +154,18 @@ ar2317SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
struct ar2317State *priv = AR2317(ah);
int regWrites = 0;

- HALDEBUG(ah, HAL_DEBUG_RFPARAM,
- "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
- __func__, chan->channel, chan->channelFlags, modesIndex);
+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);

HALASSERT(priv);

/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_B:
+ if (IEEE80211_IS_CHAN_B(chan)) {
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
- break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ } else {
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- return AH_FALSE;
}

/* Bank 1 Write */
@@ -285,7 +278,7 @@ ar2317FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
uint16_t ii, jj, kk;
int16_t currPwr = (int16_t)(2*Pmin);
/* since Pmin is pwr*2 and pwrList is 4*pwr */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;

ii = 0;
jj = 0;
@@ -351,7 +344,7 @@ ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
/* XXX excessive stack usage? */
uint32_t ii, jj, kk;
int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;
uint32_t numPdGainsUsed = 0;
/*
* If desired to support -ve power levels in future, just
@@ -485,7 +478,8 @@ ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

static HAL_BOOL
ar2317SetPowerTable(struct ath_hal *ah,
- int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *minPower, int16_t *maxPower,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
struct ath_hal_5212 *ahp = AH5212(ah);
@@ -502,11 +496,11 @@ ar2317SetPowerTable(struct ath_hal *ah,
#endif

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
- __func__, chan->channel,chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
@@ -626,9 +620,11 @@ ar2317GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)
}

static HAL_BOOL
-ar2317GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar2317GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
+ uint16_t freq = chan->ic_freq; /* NB: never mapped */
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2317 *pRawDataset = AH_NULL;
const RAW_DATA_PER_CHANNEL_2317 *data=AH_NULL;
@@ -637,9 +633,9 @@ ar2317GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,

*maxPow = 0;

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else
return(AH_FALSE);
@@ -653,9 +649,9 @@ ar2317GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
if (numChannels < 1)
return(AH_FALSE);

- if ((chan->channel < data[0].channelValue) ||
- (chan->channel > data[numChannels-1].channelValue)) {
- if (chan->channel < data[0].channelValue) {
+ if ((freq < data[0].channelValue) ||
+ (freq > data[numChannels-1].channelValue)) {
+ if (freq < data[0].channelValue) {
*maxPow = ar2317GetMaxPower(ah, &data[0]);
*minPow = ar2317GetMinPower(ah, &data[0]);
return(AH_TRUE);
@@ -667,19 +663,19 @@ ar2317GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
}

/* Linearly interpolate the power value now */
- for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+ for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
last = i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = ar2317GetMaxPower(ah, &data[i]) - ar2317GetMaxPower(ah, &data[last]);
- *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) +
+ *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
ar2317GetMaxPower(ah, &data[last])*totalD)/totalD);
totalMin = ar2317GetMinPower(ah, &data[i]) - ar2317GetMinPower(ah, &data[last]);
- *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+ *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
ar2317GetMinPower(ah, &data[last])*totalD)/totalD);
return(AH_TRUE);
} else {
- if (chan->channel == data[i].channelValue) {
+ if (freq == data[i].channelValue) {
*maxPow = ar2317GetMaxPower(ah, &data[i]);
*minPow = ar2317GetMinPower(ah, &data[i]);
return(AH_TRUE);
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar2413.c b/sys/external/isc/atheros_hal/dist/ar5212/ar2413.c
index 8b739f2..4874db7 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar2413.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar2413.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -75,29 +75,29 @@ ar2413WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar2413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar2413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;
- uint16_t freq;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- if (chan->channel < 4800) {
+ if (freq < 4800) {
uint32_t txctl;

- if (((chan->channel - 2192) % 5) == 0) {
- channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+ if (((freq - 2192) % 5) == 0) {
+ channelSel = ((freq - 672) * 2 - 3040)/10;
bModeSynth = 0;
- } else if (((chan->channel - 2224) % 5) == 0) {
- channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+ } else if (((freq - 2224) % 5) == 0) {
+ channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -105,7 +105,7 @@ ar2413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
channelSel = ath_hal_reverseBits(channelSel, 8);

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -113,26 +113,26 @@ ar2413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
- } else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
- freq = chan->channel - 2; /* Align to even 5MHz raster */
+ } else if (((freq % 5) == 2) && (freq <= 5435)) {
+ freq = freq - 2; /* Align to even 5MHz raster */
channelSel = ath_hal_reverseBits(
(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
aModeRefSel = ath_hal_reverseBits(0, 2);
- } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+ } else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 20 << 2), 8);
+ ((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(3, 2);
- } else if ((chan->channel % 10) == 0) {
+ } else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 10 << 1), 8);
+ ((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(2, 2);
- } else if ((chan->channel % 5) == 0) {
+ } else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
- (chan->channel - 4800) / 5, 8);
+ (freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -155,7 +155,9 @@ ar2413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar2413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+ar2413SetRfRegs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
@@ -168,27 +170,18 @@ ar2413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
struct ar2413State *priv = AR2413(ah);
int regWrites = 0;

- HALDEBUG(ah, HAL_DEBUG_RFPARAM,
- "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
- __func__, chan->channel, chan->channelFlags, modesIndex);
+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);

HALASSERT(priv);

/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_B:
+ if (IEEE80211_IS_CHAN_B(chan)) {
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
- break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ } else {
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- return AH_FALSE;
}

/* Bank 1 Write */
@@ -302,7 +295,7 @@ ar2413FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
uint16_t ii, jj, kk;
int16_t currPwr = (int16_t)(2*Pmin);
/* since Pmin is pwr*2 and pwrList is 4*pwr */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;

ii = 0;
jj = 0;
@@ -367,7 +360,7 @@ ar2413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
#define VpdTable_I priv->vpdTable_I
uint32_t ii, jj, kk;
int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;
uint32_t numPdGainsUsed = 0;
/*
* If desired to support -ve power levels in future, just
@@ -501,9 +494,11 @@ ar2413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

static HAL_BOOL
ar2413SetPowerTable(struct ath_hal *ah,
- int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *minPower, int16_t *maxPower,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
@@ -518,11 +513,11 @@ ar2413SetPowerTable(struct ath_hal *ah,
#endif

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
- __func__, chan->channel,chan->channelFlags);
+ __func__, freq, chan->ic_flags);

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
@@ -533,7 +528,7 @@ ar2413SetPowerTable(struct ath_hal *ah,
AR_PHY_TPCRG5_PD_GAIN_OVERLAP);

numPdGainsUsed = ar2413getGainBoundariesAndPdadcsForPowers(ah,
- chan->channel, pRawDataset, pdGainOverlap_t2,
+ freq, pRawDataset, pdGainOverlap_t2,
&minCalPower2413_t2,gainBoundaries, rfXpdGain, pdadcValues);
HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);

@@ -640,9 +635,11 @@ ar2413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
}

static HAL_BOOL
-ar2413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar2413GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
+ uint16_t freq = chan->ic_freq; /* NB: never mapped */
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
const RAW_DATA_PER_CHANNEL_2413 *data = AH_NULL;
@@ -651,9 +648,9 @@ ar2413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,

*maxPow = 0;

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else
return(AH_FALSE);
@@ -667,9 +664,9 @@ ar2413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
if (numChannels < 1)
return(AH_FALSE);

- if ((chan->channel < data[0].channelValue) ||
- (chan->channel > data[numChannels-1].channelValue)) {
- if (chan->channel < data[0].channelValue) {
+ if ((freq < data[0].channelValue) ||
+ (freq > data[numChannels-1].channelValue)) {
+ if (freq < data[0].channelValue) {
*maxPow = ar2413GetMaxPower(ah, &data[0]);
*minPow = ar2413GetMinPower(ah, &data[0]);
return(AH_TRUE);
@@ -681,19 +678,19 @@ ar2413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
}

/* Linearly interpolate the power value now */
- for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+ for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
last = i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = ar2413GetMaxPower(ah, &data[i]) - ar2413GetMaxPower(ah, &data[last]);
- *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) +
+ *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
ar2413GetMaxPower(ah, &data[last])*totalD)/totalD);
totalMin = ar2413GetMinPower(ah, &data[i]) - ar2413GetMinPower(ah, &data[last]);
- *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+ *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
ar2413GetMinPower(ah, &data[last])*totalD)/totalD);
return(AH_TRUE);
} else {
- if (chan->channel == data[i].channelValue) {
+ if (freq == data[i].channelValue) {
*maxPow = ar2413GetMaxPower(ah, &data[i]);
*minPow = ar2413GetMinPower(ah, &data[i]);
return(AH_TRUE);
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar2425.c b/sys/external/isc/atheros_hal/dist/ar5212/ar2425.c
index 6f418ba..a75307a 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar2425.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar2425.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -61,7 +61,7 @@ ar2425WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* Bit 0 enables link to go to L1 when MAC goes to sleep.
* Bit 3 enables the loop back the link down to reset.
*/
- if (IS_PCIE(ah) && ath_hal_pcieL1SKPEnable) {
+ if (AH_PRIVATE(ah)->ah_ispcie && && ath_hal_pcieL1SKPEnable) {
OS_REG_WRITE(ah, AR_PCIE_PMC,
AR_PCIE_PMC_ENA_L1 | AR_PCIE_PMC_ENA_RESET);
}
@@ -82,24 +82,24 @@ ar2425WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar2425SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar2425SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;
- uint16_t freq;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- if (chan->channel < 4800) {
+ if (freq < 4800) {
uint32_t txctl;

- channelSel = chan->channel - 2272;
+ channelSel = freq - 2272;
channelSel = ath_hal_reverseBits(channelSel, 8);

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
// Enable channel spreading for channel 14
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -108,26 +108,26 @@ ar2425SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}

- } else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
- freq = chan->channel - 2; /* Align to even 5MHz raster */
+ } else if (((freq % 5) == 2) && (freq <= 5435)) {
+ freq = freq - 2; /* Align to even 5MHz raster */
channelSel = ath_hal_reverseBits(
(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
aModeRefSel = ath_hal_reverseBits(0, 2);
- } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+ } else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 20 << 2), 8);
+ ((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
- } else if ((chan->channel % 10) == 0) {
+ } else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 10 << 1), 8);
+ ((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
- } else if ((chan->channel % 5) == 0) {
+ } else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
- (chan->channel - 4800) / 5, 8);
+ (freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -149,7 +149,9 @@ ar2425SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar2425SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+ar2425SetRfRegs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
@@ -162,27 +164,18 @@ ar2425SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
uint16_t ob2GHz = 0, db2GHz = 0;
int regWrites = 0;

- HALDEBUG(ah, HAL_DEBUG_RFPARAM,
- "==>%s:chan 0x%x flag 0x%x modesIndex 0x%x\n",
- __func__, chan->channel, chan->channelFlags, modesIndex);
+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);

HALASSERT(priv);

/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_B:
+ if (IEEE80211_IS_CHAN_B(chan)) {
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
- break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ } else {
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- return AH_FALSE;
}

/* Bank 1 Write */
@@ -304,7 +297,7 @@ ar2425FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
uint16_t ii, jj, kk;
int16_t currPwr = (int16_t)(2*Pmin);
/* since Pmin is pwr*2 and pwrList is 4*pwr */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;

ii = 0;
jj = 0;
@@ -366,7 +359,7 @@ ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
/* Note the items statically allocated below are to reduce stack usage */
uint32_t ii, jj, kk;
int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;
uint32_t numPdGainsUsed = 0;
static uint16_t VpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL][MAX_PWR_RANGE_IN_HALF_DB];
/* filled out Vpd table for all pdGains (chanL) */
@@ -501,9 +494,11 @@ ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
/* Same as 2413 set power table */
static HAL_BOOL
ar2425SetPowerTable(struct ath_hal *ah,
- int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *minPower, int16_t *maxPower,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
@@ -514,11 +509,11 @@ ar2425SetPowerTable(struct ath_hal *ah,
uint32_t i, reg32, regoffset;

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s:chan 0x%x flag 0x%x\n",
- __func__, chan->channel,chan->channelFlags);
+ __func__, freq, chan->ic_flags);

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s:illegal mode\n", __func__);
@@ -528,7 +523,7 @@ ar2425SetPowerTable(struct ath_hal *ah,
pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
AR_PHY_TPCRG5_PD_GAIN_OVERLAP);

- ar2425getGainBoundariesAndPdadcsForPowers(ah, chan->channel,
+ ar2425getGainBoundariesAndPdadcsForPowers(ah, freq,
pRawDataset, pdGainOverlap_t2,&minCalPower2413_t2,gainBoundaries,
rfXpdGain, pdadcValues);

@@ -603,9 +598,11 @@ ar2425GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)

static
HAL_BOOL
-ar2425GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
- int16_t *maxPow, int16_t *minPow)
+ar2425GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ int16_t *maxPow, int16_t *minPow)
{
+ uint16_t freq = chan->ic_freq; /* NB: never mapped */
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
const RAW_DATA_PER_CHANNEL_2413 *data = AH_NULL;
@@ -614,9 +611,9 @@ ar2425GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,

*maxPow = 0;

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else
return(AH_FALSE);
@@ -630,9 +627,9 @@ ar2425GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
if (numChannels < 1)
return(AH_FALSE);

- if ((chan->channel < data[0].channelValue) ||
- (chan->channel > data[numChannels-1].channelValue)) {
- if (chan->channel < data[0].channelValue) {
+ if ((freq < data[0].channelValue) ||
+ (freq > data[numChannels-1].channelValue)) {
+ if (freq < data[0].channelValue) {
*maxPow = ar2425GetMaxPower(ah, &data[0]);
*minPow = ar2425GetMinPower(ah, &data[0]);
return(AH_TRUE);
@@ -644,19 +641,19 @@ ar2425GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
}

/* Linearly interpolate the power value now */
- for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+ for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
last = i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = ar2425GetMaxPower(ah, &data[i]) - ar2425GetMaxPower(ah, &data[last]);
- *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) +
+ *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
ar2425GetMaxPower(ah, &data[last])*totalD)/totalD);
totalMin = ar2425GetMinPower(ah, &data[i]) - ar2425GetMinPower(ah, &data[last]);
- *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+ *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
ar2425GetMinPower(ah, &data[last])*totalD)/totalD);
return(AH_TRUE);
} else {
- if (chan->channel == data[i].channelValue) {
+ if (freq == data[i].channelValue) {
*maxPow = ar2425GetMaxPower(ah, &data[i]);
*minPow = ar2425GetMinPower(ah, &data[i]);
return(AH_TRUE);
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5111.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5111.c
index 6877eac..dd5dffb 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5111.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5111.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -74,9 +74,10 @@ ar5111WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar5111SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5111SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define CI_2GHZ_INDEX_CORRECTION 19
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t refClk, reg32, data2111;
int16_t chan5111, chanIEEE;

@@ -140,10 +141,10 @@ ar5111SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
{ 1, 0x46, 180 } /* 2732 26 */
};

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
- if (IS_CHAN_2GHZ(chan)) {
+ chanIEEE = chan->ic_ieee;
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
const CHAN_INFO_2GHZ* ci =
&chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
uint32_t txctl;
@@ -153,7 +154,7 @@ ar5111SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
| (ci->refClkSel << 4);
chan5111 = ci->channel5111;
txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -214,9 +215,10 @@ ar5111GetRfBank(struct ath_hal *ah, int bank)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+ar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
uint16_t modesIndex, uint16_t *rfXpdGain)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
@@ -224,20 +226,22 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
uint32_t ob2GHz, db2GHz, rfReg[N(ar5212Bank6_5111)];
int i, regWrites = 0;

+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);
+
/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_T:
- if (4000 < chan->channel && chan->channel < 5260) {
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
+ if (4000 < freq && freq < 5260) {
tempOB = ee->ee_ob1;
tempDB = ee->ee_db1;
- } else if (5260 <= chan->channel && chan->channel < 5500) {
+ } else if (5260 <= freq && freq < 5500) {
tempOB = ee->ee_ob2;
tempDB = ee->ee_db2;
- } else if (5500 <= chan->channel && chan->channel < 5725) {
+ } else if (5500 <= freq && freq < 5725) {
tempOB = ee->ee_ob3;
tempDB = ee->ee_db3;
- } else if (chan->channel >= 5725) {
+ } else if (freq >= 5725) {
tempOB = ee->ee_ob4;
tempDB = ee->ee_db4;
} else {
@@ -251,7 +255,7 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
rfPwdXpd = !ee->ee_xpd[headerInfo11A];
gainI = ee->ee_gainI[headerInfo11A];
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
tempOB = ee->ee_obFor24;
tempDB = ee->ee_dbFor24;
ob2GHz = ee->ee_ob2GHz[0];
@@ -262,7 +266,8 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
rfPwdXpd = !ee->ee_xpd[headerInfo11B];
gainI = ee->ee_gainI[headerInfo11B];
break;
- case CHANNEL_G:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_PUREG: /* NB: really 108G */
tempOB = ee->ee_obFor24g;
tempDB = ee->ee_dbFor24g;
ob2GHz = ee->ee_ob2GHz[1];
@@ -275,7 +280,7 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -285,7 +290,7 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
/* Bank 0 Write */
for (i = 0; i < N(ar5212Bank0_5111); i++)
rfReg[i] = ar5212Bank0_5111[i][modesIndex];
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
}
@@ -303,7 +308,7 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
/* Bank 6 Write */
for (i = 0; i < N(ar5212Bank6_5111); i++)
rfReg[i] = ar5212Bank6_5111[i][modesIndex];
- if (IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
+ if (IEEE80211_IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd84, 1, 51, 3);
ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd90, 1, 45, 3);
}
@@ -320,11 +325,11 @@ ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);
ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);

- if (IS_CHAN_QUARTER_RATE(chan) || IS_CHAN_HALF_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_QUARTER(chan) || IEEE80211_IS_CHAN_HALF(chan)) {
uint32_t rfWaitI, rfWaitS, rfMaxTime;

rfWaitS = 0x1f;
- rfWaitI = (IS_CHAN_HALF_RATE(chan)) ? 0x10 : 0x1f;
+ rfWaitI = (IEEE80211_IS_CHAN_HALF(chan)) ? 0x10 : 0x1f;
rfMaxTime = 3;
ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
@@ -383,9 +388,11 @@ interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
*/
static HAL_BOOL
ar5111SetPowerTable(struct ath_hal *ah,
- int16_t *pMinPower, int16_t *pMaxPower, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *pMinPower, int16_t *pMaxPower,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
FULL_PCDAC_STRUCT pcdacStruct;
@@ -404,27 +411,27 @@ ar5111SetPowerTable(struct ath_hal *ah,
PCDACS_EEPROM eepromPcdacs;

/* setup the pcdac struct to point to the correct info, based on mode */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_T:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) {
+ case IEEE80211_CHAN_A:
+ case IEEE80211_CHAN_ST:
eepromPcdacs.numChannels = ee->ee_numChannels11a;
eepromPcdacs.pChannelList = ee->ee_channels11a;
eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
eepromPcdacs.numChannels = ee->ee_numChannels2_4;
eepromPcdacs.pChannelList = ee->ee_channels11b;
eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_108G:
eepromPcdacs.numChannels = ee->ee_numChannels2_4;
eepromPcdacs.pChannelList = ee->ee_channels11g;
eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -444,7 +451,7 @@ ar5111SetPowerTable(struct ath_hal *ah,

/* Fill out the power values for this channel */
for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
- pScaledUpDbm[j] = ar5212GetScaledPower(chan->channel,
+ pScaledUpDbm[j] = ar5212GetScaledPower(freq,
pPcdacValues[j], pSrcStruct);

/* Now scale the pcdac values to fit in the 64 entry power table */
@@ -537,7 +544,7 @@ ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
uint16_t lFreq, rFreq; /* left and right frequency values */
uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */
uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */
- uint16_t lPwr = 0, uPwr = 0; /* lower and upper temp pwr values */
+ uint16_t lPwr, uPwr; /* lower and upper temp pwr values */
uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */

if (ar5212FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue)) {
@@ -617,7 +624,8 @@ ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
}

static HAL_BOOL
-ar5111GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar5111GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
/* XXX - Get 5111 power limits! */
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5112.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5112.c
index 1fadeee..89f1a25 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5112.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5112.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -75,29 +75,29 @@ ar5112WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar5112SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5112SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;
- uint16_t freq;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- if (chan->channel < 4800) {
+ if (freq < 4800) {
uint32_t txctl;

- if (((chan->channel - 2192) % 5) == 0) {
- channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+ if (((freq - 2192) % 5) == 0) {
+ channelSel = ((freq - 672) * 2 - 3040)/10;
bModeSynth = 0;
- } else if (((chan->channel - 2224) % 5) == 0) {
- channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+ } else if (((freq - 2224) % 5) == 0) {
+ channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -105,7 +105,7 @@ ar5112SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
channelSel = ath_hal_reverseBits(channelSel, 8);

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -113,26 +113,26 @@ ar5112SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
- } else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
- freq = chan->channel - 2; /* Align to even 5MHz raster */
+ } else if (((freq % 5) == 2) && (freq <= 5435)) {
+ freq = freq - 2; /* Align to even 5MHz raster */
channelSel = ath_hal_reverseBits(
(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
aModeRefSel = ath_hal_reverseBits(0, 2);
- } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+ } else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 20 << 2), 8);
+ ((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(3, 2);
- } else if ((chan->channel % 10) == 0) {
+ } else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 10 << 1), 8);
+ ((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(2, 2);
- } else if ((chan->channel % 5) == 0) {
+ } else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
- (chan->channel - 4800) / 5, 8);
+ (freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -175,7 +175,8 @@ ar5112GetRfBank(struct ath_hal *ah, int bank)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+ar5112SetRfRegs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
@@ -183,6 +184,7 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
for (i = 0; i < N(ar5212Bank##_ix##_5112); i++) \
(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5112[i][_col];\
} while (0)
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t rfXpdSel, gainI;
@@ -194,20 +196,22 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,

HALASSERT(priv);

+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);
+
/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_T:
- if (chan->channel > 4000 && chan->channel < 5260) {
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
+ if (freq > 4000 && freq < 5260) {
ob5GHz = ee->ee_ob1;
db5GHz = ee->ee_db1;
- } else if (chan->channel >= 5260 && chan->channel < 5500) {
+ } else if (freq >= 5260 && freq < 5500) {
ob5GHz = ee->ee_ob2;
db5GHz = ee->ee_db2;
- } else if (chan->channel >= 5500 && chan->channel < 5725) {
+ } else if (freq >= 5500 && freq < 5725) {
ob5GHz = ee->ee_ob3;
db5GHz = ee->ee_db3;
- } else if (chan->channel >= 5725) {
+ } else if (freq >= 5725) {
ob5GHz = ee->ee_ob4;
db5GHz = ee->ee_db4;
} else {
@@ -216,14 +220,14 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
rfXpdSel = ee->ee_xpd[headerInfo11A];
gainI = ee->ee_gainI[headerInfo11A];
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
ob2GHz = ee->ee_ob2GHz[0];
db2GHz = ee->ee_db2GHz[0];
rfXpdSel = ee->ee_xpd[headerInfo11B];
gainI = ee->ee_gainI[headerInfo11B];
break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_PUREG: /* NB: really 108G */
ob2GHz = ee->ee_ob2GHz[1];
db2GHz = ee->ee_ob2GHz[1];
rfXpdSel = ee->ee_xpd[headerInfo11G];
@@ -231,7 +235,7 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -252,7 +256,7 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdGain[0], 2, 270, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdGain[1], 2, 257, 0);

- if (IS_CHAN_OFDM(chan)) {
+ if (IEEE80211_IS_CHAN_OFDM(chan)) {
ar5212ModifyRfBuffer(priv->Bank6Data,
gv->currStep->paramVal[GP_PWD_138], 1, 168, 3);
ar5212ModifyRfBuffer(priv->Bank6Data,
@@ -268,7 +272,7 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
}

/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 287, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 290, 0);
} else {
@@ -296,18 +300,18 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,

/* Setup Bank 7 Setup */
RF_BANK_SETUP(priv, 7, modesIndex);
- if (IS_CHAN_OFDM(chan))
+ if (IEEE80211_IS_CHAN_OFDM(chan))
ar5212ModifyRfBuffer(priv->Bank7Data,
gv->currStep->paramVal[GP_MIXGAIN_OVR], 2, 37, 0);

ar5212ModifyRfBuffer(priv->Bank7Data, gainI, 6, 14, 0);

/* Adjust params for Derby TX power control */
- if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) {
uint32_t rfDelay, rfPeriod;

rfDelay = 0xf;
- rfPeriod = (IS_CHAN_HALF_RATE(chan)) ? 0x8 : 0xf;
+ rfPeriod = (IEEE80211_IS_CHAN_HALF(chan)) ? 0x8 : 0xf;
ar5212ModifyRfBuffer(priv->Bank7Data, rfDelay, 4, 58, 0);
ar5212ModifyRfBuffer(priv->Bank7Data, rfPeriod, 4, 70, 0);
}
@@ -338,9 +342,11 @@ ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
*/
static HAL_BOOL
ar5112SetPowerTable(struct ath_hal *ah,
- int16_t *pPowerMin, int16_t *pPowerMax, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *pPowerMin, int16_t *pPowerMax,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint32_t numXpdGain = IS_RADX112_REV2(ah) ? 2 : 1;
@@ -367,24 +373,24 @@ ar5112SetPowerTable(struct ath_hal *ah,
uint16_t xgainList[2];
uint16_t xpdMask;

- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_T:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) {
+ case IEEE80211_CHAN_A:
+ case IEEE80211_CHAN_ST:
pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11A];
xpdGainMask = ee->ee_xgain[headerInfo11A];
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11B];
xpdGainMask = ee->ee_xgain[headerInfo11B];
break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_108G:
pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11G];
xpdGainMask = ee->ee_xgain[headerInfo11G];
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown channel flags 0x%x\n",
- __func__, chan->channelFlags & CHANNEL_ALL);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -416,7 +422,7 @@ ar5112SetPowerTable(struct ath_hal *ah,
}
}

- ar5212GetLowerUpperIndex(chan->channel, &pPowerExpn->pChannels[0],
+ ar5212GetLowerUpperIndex(freq, &pPowerExpn->pChannels[0],
pPowerExpn->numChannels, &chan_idx_L, &chan_idx_R);

kk = 0;
@@ -474,7 +480,7 @@ ar5112SetPowerTable(struct ath_hal *ah,
if (xgainList[1] == 0xDEAD) {
for (jj = 0; jj < 64; jj++) {
pwr_table0[jj] = interpolate_signed(
- chan->channel, chan_L, chan_R,
+ freq, chan_L, chan_R,
powTableLXPD[0][jj], powTableLXPD[kk][jj]);
}
Pmin = getPminAndPcdacTableFromPowerTable(&pwr_table0[0],
@@ -487,10 +493,10 @@ ar5112SetPowerTable(struct ath_hal *ah,
} else {
for (jj = 0; jj < 64; jj++) {
pwr_table0[jj] = interpolate_signed(
- chan->channel, chan_L, chan_R,
+ freq, chan_L, chan_R,
powTableLXPD[0][jj], powTableLXPD[kk][jj]);
pwr_table1[jj] = interpolate_signed(
- chan->channel, chan_L, chan_R,
+ freq, chan_L, chan_R,
powTableHXPD[0][jj], powTableHXPD[kk][jj]);
}
if (numXpdGain == 2) {
@@ -757,9 +763,11 @@ ar5112GetMinPower(struct ath_hal *ah, const EXPN_DATA_PER_CHANNEL_5112 *data)
}

static HAL_BOOL
-ar5112GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar5112GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
+ uint16_t freq = chan->ic_freq; /* NB: never mapped */
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
int numChannels=0,i,last;
int totalD, totalF,totalMin;
@@ -767,16 +775,16 @@ ar5112GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
const EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;

*maxPow = 0;
- if (IS_CHAN_A(chan)) {
+ if (IEEE80211_IS_CHAN_A(chan)) {
powerArray = ee->ee_modePowerArray5112;
data = powerArray[headerInfo11A].pDataPerChannel;
numChannels = powerArray[headerInfo11A].numChannels;
- } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
+ } else if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan)) {
/* XXX - is this correct? Should we also use the same power for turbo G? */
powerArray = ee->ee_modePowerArray5112;
data = powerArray[headerInfo11G].pDataPerChannel;
numChannels = powerArray[headerInfo11G].numChannels;
- } else if (IS_CHAN_B(chan)) {
+ } else if (IEEE80211_IS_CHAN_B(chan)) {
powerArray = ee->ee_modePowerArray5112;
data = powerArray[headerInfo11B].pDataPerChannel;
numChannels = powerArray[headerInfo11B].numChannels;
@@ -789,9 +797,9 @@ ar5112GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
if (numChannels < 1)
return(AH_FALSE);

- if ((chan->channel < data[0].channelValue) ||
- (chan->channel > data[numChannels-1].channelValue)) {
- if (chan->channel < data[0].channelValue) {
+ if ((freq < data[0].channelValue) ||
+ (freq > data[numChannels-1].channelValue)) {
+ if (freq < data[0].channelValue) {
*maxPow = data[0].maxPower_t4;
*minPow = ar5112GetMinPower(ah, &data[0]);
return(AH_TRUE);
@@ -804,18 +812,18 @@ ar5112GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,

/* Linearly interpolate the power value now */
for (last=0,i=0;
- (i<numChannels) && (chan->channel > data[i].channelValue);
+ (i<numChannels) && (freq > data[i].channelValue);
last=i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
- *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
+ *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);

totalMin = ar5112GetMinPower(ah,&data[i]) - ar5112GetMinPower(ah, &data[last]);
- *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar5112GetMinPower(ah, &data[last])*totalD)/totalD);
+ *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) + ar5112GetMinPower(ah, &data[last])*totalD)/totalD);
return (AH_TRUE);
} else {
- if (chan->channel == data[i].channelValue) {
+ if (freq == data[i].channelValue) {
*maxPow = data[i].maxPower_t4;
*minPow = ar5112GetMinPower(ah, &data[i]);
return(AH_TRUE);
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212.h b/sys/external/isc/atheros_hal/dist/ar5212/ar5212.h
index 2d63eb2..65dde38 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212.h
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -122,7 +122,6 @@ typedef struct {
uint32_t targetGain;
uint32_t loTrig;
uint32_t hiTrig;
- uint32_t gainFCorrection;
uint32_t active;
const GAIN_OPTIMIZATION_STEP *currStep;
} GAIN_VALUES;
@@ -133,16 +132,18 @@ typedef struct RfHalFuncs {

void (*rfDetach)(struct ath_hal *ah);
void (*writeRegs)(struct ath_hal *,
- u_int modeIndex, u_int freqIndex, int regWrites);
+ u_int modeIndex, u_int freqIndex, int regWrites);
uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
- HAL_BOOL (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+ HAL_BOOL (*setChannel)(struct ath_hal *,
+ const struct ieee80211_channel *);
HAL_BOOL (*setRfRegs)(struct ath_hal *,
- HAL_CHANNEL_INTERNAL *, uint16_t modesIndex,
+ const struct ieee80211_channel *, uint16_t modesIndex,
uint16_t *rfXpdGain);
HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
int16_t *minPower, int16_t *maxPower,
- HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain);
- HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *,
+ const struct ieee80211_channel *, uint16_t *rfXpdGain);
+ HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah,
+ const const struct ieee80211_channel *,
int16_t *maxPow, int16_t *minPow);
int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
} RF_HAL_FUNCS;
@@ -186,8 +187,6 @@ struct ar5212AniState {
uint32_t listenTime;

/* NB: intentionally ordered so data exported to user space is first */
- HAL_CHANNEL c;
- HAL_BOOL isSetup; /* has state to do a restore */
uint32_t txFrameCount; /* Last txFrameCount */
uint32_t rxFrameCount; /* Last rx Frame count */
uint32_t cycleCount; /* Last cycleCount
@@ -319,7 +318,7 @@ struct ath_hal_5212 {
struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
struct ar5212AniState *ah_curani; /* cached last reference */
- struct ar5212AniState ah_ani[64]; /* per-channel state */
+ struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */

/*
* Transmit power state. Note these are maintained
@@ -328,6 +327,9 @@ struct ath_hal_5212 {
uint16_t *ah_pcdacTable;
u_int ah_pcdacTableSize;
uint16_t ah_ratesArray[16];
+
+ uint8_t ah_txTrigLev; /* current Tx trigger level */
+ uint8_t ah_maxTxTrigLev; /* max tx trigger level */
};
#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))

@@ -357,8 +359,6 @@ struct ath_hal_5212 {
((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)

-#define IS_PCIE(ah) (IS_5424(ah) || IS_2425(ah))
-
#define AH_RADIO_MAJOR(ah) \
(AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
#define AH_RADIO_MINOR(ah) \
@@ -395,16 +395,17 @@ struct ath_hal_5212 {
*/
#define SAVE_CCK(_ah, _chan, _flag) do { \
if ((IS_2425(_ah) || IS_2417(_ah)) && \
- (((_chan)->channelFlags) & CHANNEL_CCK)) { \
- (_chan)->channelFlags &= ~CHANNEL_CCK; \
- (_chan)->channelFlags |= CHANNEL_OFDM; \
+ (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \
+ (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \
+ (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \
(_flag) = AH_TRUE; \
- } \
+ } else \
+ (_flag) = AH_FALSE; \
} while (0)
#define RESTORE_CCK(_ah, _chan, _flag) do { \
- if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\
- (_chan)->channelFlags &= ~CHANNEL_OFDM; \
- (_chan)->channelFlags |= CHANNEL_CCK; \
+ if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \
+ (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \
+ (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \
} \
} while (0)

@@ -450,7 +451,8 @@ extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
uint16_t regDomain, HAL_STATUS *stats);
extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
extern void ar5212EnableRfKill(struct ath_hal *);
-extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio,
+ HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
@@ -525,26 +527,32 @@ extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
struct ath_rx_status *);

extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
-extern HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+ struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
+ HAL_STATUS *status);
+extern HAL_BOOL ar5212SetChannel(struct ath_hal *,
+ const struct ieee80211_channel *);
extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
-extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *);
-extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan,
- HAL_BOOL *isIQdone);
-extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
- u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
-extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah,
+ const struct ieee80211_channel *);
+extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah,
+ struct ieee80211_channel *chan, HAL_BOOL *isIQdone);
+extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah,
+ struct ieee80211_channel *chan, u_int chainMask,
+ HAL_BOOL longCal, HAL_BOOL *isCalDone);
+extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah,
+ const struct ieee80211_channel *);
extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
-extern void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern void ar5212SetSpurMitigation(struct ath_hal *,
+ const struct ieee80211_channel *);
extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
- HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan);
+ HAL_ANT_SETTING settings, const struct ieee80211_channel *);
extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
- HAL_CHANNEL *chans, uint32_t nchans);
+ struct ieee80211_channel *chan);
extern void ar5212InitializeGainValues(struct ath_hal *);
extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
extern void ar5212RequestRfgain(struct ath_hal *);
@@ -597,7 +605,7 @@ extern void ar5212AniPhyErrReport(struct ath_hal *ah,
const struct ath_rx_status *rs);
extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
- HAL_CHANNEL *);
-extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
+ const struct ieee80211_channel *);
+extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *,
HAL_OPMODE, int);
#endif /* _ATH_AR5212_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_ani.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_ani.c
index 38b0a91..40b4879 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_ani.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_ani.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5212_ani.c,v 1.1.1.1 2008/12/11 04:46:39 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -99,43 +99,6 @@ disableAniMIBCounters(struct ath_hal *ah)
}

/*
- * This routine returns the index into the aniState array that
- * corresponds to the channel in *chan. If no match is found and the
- * array is still not fully utilized, a new entry is created for the
- * channel. We assume the attach function has already initialized the
- * ah_ani values and only the channel field needs to be set.
- */
-static int
-ar5212GetAniChannelIndex(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
-{
-#define N(a) (sizeof(a) / sizeof(a[0]))
- struct ath_hal_5212 *ahp = AH5212(ah);
- int i;
-
- for (i = 0; i < N(ahp->ah_ani); i++) {
- struct ar5212AniState *asp = &ahp->ah_ani[i];
- if (asp->c.channel == chan->channel)
- return i;
- if (asp->c.channel == 0) {
- asp->c.channel = chan->channel;
- asp->c.channelFlags = chan->channelFlags;
- asp->c.privFlags = chan->privFlags;
- asp->isSetup = AH_FALSE;
- if (IS_CHAN_2GHZ(chan))
- asp->params = &ahp->ah_aniParams24;
- else
- asp->params = &ahp->ah_aniParams5;
- return i;
- }
- }
- /* XXX statistic */
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "No more channel states left. Using channel 0\n");
- return 0; /* XXX gotta return something valid */
-#undef N
-}
-
-/*
* Return the current ANI state of the channel we're on
*/
struct ar5212AniState *
@@ -267,7 +230,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
u_int level = param;

- if (level >= params->maxNoiseImmunityLevel) {
+ if (level > params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
__func__, level, params->maxNoiseImmunityLevel);
@@ -315,14 +278,12 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (on) {
OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ ahp->ah_stats.ast_ani_ofdmon++;
} else {
OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
- }
- if (on)
- ahp->ah_stats.ast_ani_ofdmon++;
- else
ahp->ah_stats.ast_ani_ofdmoff++;
+ }
aniState->ofdmWeakSigDetectOff = !on;
break;
}
@@ -342,7 +303,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
case HAL_ANI_FIRSTEP_LEVEL: {
u_int level = param;

- if (level >= params->maxFirstepLevel) {
+ if (level > params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
__func__, level, params->maxFirstepLevel);
@@ -360,7 +321,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
u_int level = param;

- if (level >= params->maxSpurImmunityLevel) {
+ if (level > params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
__func__, level, params->maxSpurImmunityLevel);
@@ -421,7 +382,7 @@ static void
ar5212AniOfdmErrTrigger(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
struct ar5212AniState *aniState;
const struct ar5212AniParams *params;

@@ -433,7 +394,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
aniState = ahp->ah_curani;
params = aniState->params;
/* First, raise noise immunity level, up to max */
- if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
+ if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
aniState->noiseImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
@@ -441,7 +402,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
return;
}
/* then, raise spur immunity level, up to max */
- if (aniState->spurImmunityLevel+1 < params->maxSpurImmunityLevel) {
+ if (aniState->spurImmunityLevel+1 <= params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u\n", __func__,
aniState->spurImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
@@ -470,7 +431,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
* If weak sig detect is already off, as last resort,
* raise firstep level
*/
- if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
+ if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
@@ -490,7 +451,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_TRUE);
}
- if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
+ if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
@@ -504,8 +465,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
* weak signal detection and zero firstepLevel to
* maximize CCK sensitivity
*/
- /* XXX can optimize */
- if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
if (!aniState->ofdmWeakSigDetectOff) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d OWSD off\n",
@@ -532,7 +492,7 @@ static void
ar5212AniCckErrTrigger(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
struct ar5212AniState *aniState;
const struct ar5212AniParams *params;

@@ -544,7 +504,7 @@ ar5212AniCckErrTrigger(struct ath_hal *ah)
/* first, raise noise immunity level, up to max */
aniState = ahp->ah_curani;
params = aniState->params;
- if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
+ if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
aniState->noiseImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
@@ -559,7 +519,7 @@ ar5212AniCckErrTrigger(struct ath_hal *ah)
* Beacon signal in mid and high range,
* raise firstep level.
*/
- if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
+ if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
@@ -572,7 +532,8 @@ ar5212AniCckErrTrigger(struct ath_hal *ah)
* CCK sensitivity in 11b/g mode.
*/
/* XXX can optimize */
- if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_B(chan) ||
+ IEEE80211_IS_CHAN_G(chan)) {
if (aniState->firstepLevel > 0) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d zero ST (was %u)\n",
@@ -613,31 +574,35 @@ ar5212AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
/*
* Restore/reset the ANI parameters and reset the statistics.
* This routine must be called for every channel change.
- *
- * NOTE: This is where ah_curani is set; other ani code assumes
- * it is setup to reflect the current channel.
*/
void
-ar5212AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+ar5212AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
HAL_OPMODE opmode, int restore)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- struct ar5212AniState *aniState;
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
+ /* XXX bounds check ic_devdata */
+ struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];
uint32_t rxfilter;
- int index;

- index = ar5212GetAniChannelIndex(ah, chan);
- aniState = &ahp->ah_ani[index];
+ if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {
+ OS_MEMZERO(aniState, sizeof(*aniState));
+ if (IEEE80211_IS_CHAN_2GHZ(chan))
+ aniState->params = &ahp->ah_aniParams24;
+ else
+ aniState->params = &ahp->ah_aniParams5;
+ ichan->privFlags |= CHANNEL_ANI_INIT;
+ HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);
+ }
ahp->ah_curani = aniState;
#if 0
- ath_hal_printf(ah,"%s: chan %u/0x%x restore %d setup %d opmode %u\n",
- __func__, chan->channel, chan->channelFlags, restore,
- aniState->isSetup, opmode);
+ ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
+ __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
+ ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
#else
- HALDEBUG(ah, HAL_DEBUG_ANI,
- "%s: chan %u/0x%x restore %d setup %d opmode %u\n",
- __func__, chan->channel, chan->channelFlags, restore,
- aniState->isSetup, opmode);
+ HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
+ __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
+ ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
#endif
OS_MARK(ah, AH_MARK_ANI_RESET, opmode);

@@ -659,7 +624,7 @@ ar5212AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* XXX if ANI follows hardware, we don't care what mode we're
* XXX in, we should keep the ani parameters
*/
- if (restore && aniState->isSetup) {
+ if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel);
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
@@ -677,7 +642,7 @@ ar5212AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
AH_TRUE);
ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
- aniState->isSetup = AH_TRUE;
+ ichan->privFlags |= CHANNEL_ANI_SETUP;
}
ar5212AniRestart(ah, aniState);

@@ -953,7 +918,7 @@ updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
*/
void
ar5212AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
- HAL_CHANNEL *chan)
+ const struct ieee80211_channel *chan)
{
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState = ahp->ah_curani;
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_attach.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_attach.c
index 205d8e6..d46b62f 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_attach.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_attach.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -29,10 +29,11 @@
#define AH_5212_COMMON
#include "ar5212/ar5212.ini"

+static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
+static void ar5212DisablePCIE(struct ath_hal *ah);
+
static const struct ath_hal_private ar5212hal = {{
.ah_magic = AR5212_MAGIC,
- .ah_abi = HAL_ABI_VERSION,
- .ah_countryCode = CTRY_DEFAULT,

.ah_getRateTable = ar5212GetRateTable,
.ah_detach = ar5212Detach,
@@ -41,6 +42,8 @@ static const struct ath_hal_private ar5212hal = {{
.ah_reset = ar5212Reset,
.ah_phyDisable = ar5212PhyDisable,
.ah_disable = ar5212Disable,
+ .ah_configPCIE = ar5212ConfigPCIE,
+ .ah_disablePCIE = ar5212DisablePCIE,
.ah_setPCUConfig = ar5212SetPCUConfig,
.ah_perCalibration = ar5212PerCalibration,
.ah_perCalibrationN = ar5212PerCalibrationN,
@@ -152,44 +155,9 @@ static const struct ath_hal_private ar5212hal = {{
#ifdef AH_SUPPORT_WRITE_EEPROM
.ah_eepromWrite = ar5212EepromWrite,
#endif
- .ah_gpioCfgOutput = ar5212GpioCfgOutput,
- .ah_gpioCfgInput = ar5212GpioCfgInput,
- .ah_gpioGet = ar5212GpioGet,
- .ah_gpioSet = ar5212GpioSet,
- .ah_gpioSetIntr = ar5212GpioSetIntr,
.ah_getChipPowerLimits = ar5212GetChipPowerLimits,
};

-/*
- * Disable PLL when in L0s as well as receiver clock when in L1.
- * This power saving option must be enabled through the Serdes.
- *
- * Programming the Serdes must go through the same 288 bit serial shift
- * register as the other analog registers. Hence the 9 writes.
- *
- * XXX Clean up the magic numbers.
- */
-static void
-configurePciePowerSave(struct ath_hal *ah)
-{
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
-
- /* RX shut off when elecidle is asserted */
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
-
- /* Shut off PLL and CLKREQ active in L1 */
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
- OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
-
- /* Load the new settings */
- OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
-}
-
uint32_t
ar5212GetRadioRev(struct ath_hal *ah)
{
@@ -280,6 +248,9 @@ ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
ahp->ah_acktimeout = (u_int) -1;
ahp->ah_ctstimeout = (u_int) -1;
ahp->ah_sifstime = (u_int) -1;
+ ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD,
+ ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD,
+
OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
#undef N
}
@@ -326,7 +297,7 @@ ar5212Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
{
#define AH_EEPROM_PROTECT(ah) \
- (IS_PCIE(ah) ? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
+ (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
struct ath_hal_5212 *ahp;
struct ath_hal *ah;
struct ath_hal_rf *rf;
@@ -358,6 +329,7 @@ ar5212Attach(uint16_t devid, HAL_SOFTC sc,
val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
+ AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);

if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
@@ -380,9 +352,9 @@ ar5212Attach(uint16_t devid, HAL_SOFTC sc,

AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);

- if (IS_PCIE(ah)) {
+ if (AH_PRIVATE(ah)->ah_ispcie) {
/* XXX: build flag to disable this? */
- configurePciePowerSave(ah);
+ ath_hal_configPCIE(ah, AH_FALSE);
}

if (!ar5212ChipTest(ah)) {
@@ -472,7 +444,7 @@ ar5212Attach(uint16_t devid, HAL_SOFTC sc,
val = OS_REG_READ(ah, AR_PCICFG);
val = MS(val, AR_PCICFG_EEPROM_SIZE);
if (val == 0) {
- if (!IS_PCIE(ah)) {
+ if (!AH_PRIVATE(ah)->ah_ispcie) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: unsupported EEPROM size %u (0x%x) found\n",
__func__, val, val);
@@ -653,12 +625,12 @@ HAL_BOOL
ar5212GetChannelEdges(struct ath_hal *ah,
uint16_t flags, uint16_t *low, uint16_t *high)
{
- if (flags & CHANNEL_5GHZ) {
+ if (flags & IEEE80211_CHAN_5GHZ) {
*low = 4915;
*high = 6100;
return AH_TRUE;
}
- if ((flags & CHANNEL_2GHZ) &&
+ if ((flags & IEEE80211_CHAN_2GHZ) &&
(ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
*low = 2312;
@@ -669,6 +641,42 @@ ar5212GetChannelEdges(struct ath_hal *ah,
}

/*
+ * Disable PLL when in L0s as well as receiver clock when in L1.
+ * This power saving option must be enabled through the Serdes.
+ *
+ * Programming the Serdes must go through the same 288 bit serial shift
+ * register as the other analog registers. Hence the 9 writes.
+ *
+ * XXX Clean up the magic numbers.
+ */
+static void
+ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
+{
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+
+ /* RX shut off when elecidle is asserted */
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
+
+ /* Shut off PLL and CLKREQ active in L1 */
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
+ OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
+
+ /* Load the new settings */
+ OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
+}
+
+static void
+ar5212DisablePCIE(struct ath_hal *ah)
+{
+ /* NB: fill in for 9100 */
+}
+
+/*
* Fill all software cached or static hardware state information.
* Return failure if capabilities are to come from EEPROM and
* cannot be read.
@@ -828,13 +836,26 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
ahpriv->ah_rxornIsFatal =
(AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);

- /* h/w phy counters first appeared in Hainan */
- pCap->halHwPhyCounterSupport =
- (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
+ /* enable features that first appeared in Hainan */
+ if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
- AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE;
+ AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
+ /* h/w phy counters */
+ pCap->halHwPhyCounterSupport = AH_TRUE;
+ /* bssid match disable */
+ pCap->halBssidMatchSupport = AH_TRUE;
+ }

pCap->halTstampPrecision = 15;
+ pCap->halIntrMask = HAL_INT_COMMON
+ | HAL_INT_RX
+ | HAL_INT_TX
+ | HAL_INT_FATAL
+ | HAL_INT_BNR
+ | HAL_INT_BMISC
+ ;
+ if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
+ pCap->halIntrMask &= ~HAL_INT_TBTT;

return AH_TRUE;
#undef IS_COBRA
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_eeprom.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_eeprom.c
index 82362c9..f4b6771 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_eeprom.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_eeprom.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5212_eeprom.c,v 1.1.1.1 2008/12/11 04:46:40 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_gpio.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_gpio.c
index 03a7946..5763dcb 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_gpio.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_gpio.c
@@ -36,7 +36,7 @@
* Configure GPIO Output lines
*/
HAL_BOOL
-ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
HALASSERT(gpio < AR_NUM_GPIO);

diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c
index 3ba9141..a0e9dfa 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c
@@ -55,26 +55,28 @@ HAL_BOOL
ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
{
uint32_t isr, isr0, isr1;
- uint32_t mask2=0;
+ uint32_t mask2;
struct ath_hal_5212 *ahp = AH5212(ah);

isr = OS_REG_READ(ah, AR_ISR);
+ mask2 = 0;
if (isr & AR_ISR_BCNMISC) {
- uint32_t isr2;
- isr2 = OS_REG_READ(ah, AR_ISR_S2);
+ uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
if (isr2 & AR_ISR_S2_TIM)
mask2 |= HAL_INT_TIM;
if (isr2 & AR_ISR_S2_DTIM)
mask2 |= HAL_INT_DTIM;
if (isr2 & AR_ISR_S2_DTIMSYNC)
mask2 |= HAL_INT_DTIMSYNC;
- if (isr2 & (AR_ISR_S2_CABEND ))
+ if (isr2 & AR_ISR_S2_CABEND)
mask2 |= HAL_INT_CABEND;
+ if (isr2 & AR_ISR_S2_TBTT)
+ mask2 |= HAL_INT_TBTT;
}
isr = OS_REG_READ(ah, AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
- return AH_FALSE;;
+ return AH_FALSE;
}

*masked = isr & HAL_INT_COMMON;
@@ -137,7 +139,7 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
{
struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t omask = ahp->ah_maskReg;
- uint32_t mask,mask2;
+ uint32_t mask, mask2;

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
__func__, omask, ints);
@@ -171,7 +173,9 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
if (ints & HAL_INT_DTIMSYNC)
mask2 |= AR_IMR_S2_DTIMSYNC;
if (ints & HAL_INT_CABEND)
- mask2 |= (AR_IMR_S2_CABEND );
+ mask2 |= AR_IMR_S2_CABEND;
+ if (ints & HAL_INT_TBTT)
+ mask2 |= AR_IMR_S2_TBTT;
}
if (ints & HAL_INT_FATAL) {
/*
@@ -184,15 +188,8 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
/* Write the new IMR and store off our SW copy. */
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
OS_REG_WRITE(ah, AR_IMR, mask);
- OS_REG_WRITE(ah, AR_IMR_S2,
- (OS_REG_READ(ah, AR_IMR_S2) &
- ~(AR_IMR_S2_TIM |
- AR_IMR_S2_DTIM |
- AR_IMR_S2_DTIMSYNC |
- AR_IMR_S2_CABEND |
- AR_IMR_S2_CABTO |
- AR_IMR_S2_TSFOOR ) )
- | mask2);
+ OS_REG_WRITE(ah, AR_IMR_S2,
+ (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2);
ahp->ah_maskReg = ints;

/* Re-enable interrupts if they were enabled before. */
@@ -200,7 +197,5 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
}
-
-
return omask;
}
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_misc.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_misc.c
index 9cc0322..af9be75 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_misc.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_misc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5212_misc.c,v 1.1.1.1 2008/12/11 04:46:41 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -34,8 +34,6 @@
#define AR_NUM_GPIO 6 /* 6 GPIO pins */
#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */

-extern void ar5212SetRateDurationTable(struct ath_hal *, HAL_CHANNEL *);
-
void
ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
{
@@ -294,12 +292,12 @@ ar5212ResetTsf(struct ath_hal *ah)
void
ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
{
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
uint32_t reg;
uint8_t xset;
int i;

- if (chan == AH_NULL || !IS_CHAN_CCK(chan))
+ if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan))
return;
xset = 0;
for (i = 0; i < rs->rs_count; i++) {
@@ -423,15 +421,15 @@ HAL_BOOL
ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- const HAL_CHANNEL_INTERNAL *ichan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;

- if (!ahp->ah_phyPowerOn || ichan == AH_NULL) {
+ if (!ahp->ah_phyPowerOn || chan == AH_NULL) {
/* PHY powered off, just stash settings */
ahp->ah_antControl = setting;
ahp->ah_diversity = (setting == HAL_ANT_VARIABLE);
return AH_TRUE;
}
- return ar5212SetAntennaSwitchInternal(ah, setting, ichan);
+ return ar5212SetAntennaSwitchInternal(ah, setting, chan);
}

HAL_BOOL
@@ -452,7 +450,7 @@ ar5212SetSifsTime(struct ath_hal *ah, u_int us)
return AH_FALSE;
} else {
/* convert to system clocks */
- OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
+ OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
ahp->ah_slottime = us;
return AH_TRUE;
}
@@ -462,7 +460,7 @@ u_int
ar5212GetSifsTime(struct ath_hal *ah)
{
u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
- return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
+ return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
}

HAL_BOOL
@@ -592,7 +590,7 @@ ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
return;

/* Don't apply coverage class to non A channels */
- if (!IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
+ if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
return;

/* Get core clock rate */
@@ -601,10 +599,10 @@ ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
/* Compute EIFS */
slot = coverageclass * 3 * clkRate;
eifs = coverageclass * 6 * clkRate;
- if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
slot += IFS_SLOT_HALF_RATE;
eifs += IFS_EIFS_HALF_RATE;
- } else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
slot += IFS_SLOT_QUARTER_RATE;
eifs += IFS_EIFS_QUARTER_RATE;
} else { /* full rate */
@@ -803,6 +801,7 @@ ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return (ahp->ah_staId1Defaults &
AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
}
+ return HAL_EINVAL;
case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
switch (capability) {
case 0: /* hardware capability */
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_phy.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_phy.c
index 8d6b596..7927818 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_phy.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_phy.c
@@ -27,6 +27,8 @@
#define OFDM IEEE80211_T_OFDM
#define CCK IEEE80211_T_CCK
#define TURBO IEEE80211_T_TURBO
+#define HALF IEEE80211_T_OFDM_HALF
+#define QUART IEEE80211_T_OFDM_QUARTER

HAL_RATE_TABLE ar5212_11a_table = {
8, /* number of rates */
@@ -34,14 +36,14 @@ HAL_RATE_TABLE ar5212_11a_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4, 0, 0 }
+/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 },
+/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 },
+/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }
},
};

@@ -51,14 +53,14 @@ HAL_RATE_TABLE ar5212_half_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, OFDM, 3000, 0x0b, 0x00, (0x80|6), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, OFDM, 4500, 0x0f, 0x00, 9, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 6000, 0x0a, 0x00, (0x80|12), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 9000, 0x0e, 0x00, 18, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 12000, 0x09, 0x00, (0x80|24), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 18000, 0x0d, 0x00, 36, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 24000, 0x08, 0x00, 48, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 27000, 0x0c, 0x00, 54, 4, 0, 0 }
+/* 3 Mb */ { AH_TRUE, HALF, 3000, 0x0b, 0x00, (0x80|6), 0 },
+/* 4.5 Mb */ { AH_TRUE, HALF, 4500, 0x0f, 0x00, 9, 0 },
+/* 6 Mb */ { AH_TRUE, HALF, 6000, 0x0a, 0x00, (0x80|12), 2 },
+/* 9 Mb */ { AH_TRUE, HALF, 9000, 0x0e, 0x00, 18, 2 },
+/* 12 Mb */ { AH_TRUE, HALF, 12000, 0x09, 0x00, (0x80|24), 4 },
+/* 18 Mb */ { AH_TRUE, HALF, 18000, 0x0d, 0x00, 36, 4 },
+/* 24 Mb */ { AH_TRUE, HALF, 24000, 0x08, 0x00, 48, 4 },
+/* 27 Mb */ { AH_TRUE, HALF, 27000, 0x0c, 0x00, 54, 4 }
},
};

@@ -68,14 +70,14 @@ HAL_RATE_TABLE ar5212_quarter_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, OFDM, 1500, 0x0b, 0x00, (0x80|3), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, OFDM, 2250, 0x0f, 0x00, 4, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 3000, 0x0a, 0x00, (0x80|6), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 4500, 0x0e, 0x00, 9, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 6000, 0x09, 0x00, (0x80|12), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 9000, 0x0d, 0x00, 18, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 12000, 0x08, 0x00, 24, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 13500, 0x0c, 0x00, 27, 4, 0, 0 }
+/* 1.5 Mb */ { AH_TRUE, QUART, 1500, 0x0b, 0x00, (0x80|3), 0 },
+/* 2 Mb */ { AH_TRUE, QUART, 2250, 0x0f, 0x00, 4, 0 },
+/* 3 Mb */ { AH_TRUE, QUART, 3000, 0x0a, 0x00, (0x80|6), 2 },
+/* 4.5 Mb */ { AH_TRUE, QUART, 4500, 0x0e, 0x00, 9, 2 },
+/* 6 Mb */ { AH_TRUE, QUART, 6000, 0x09, 0x00, (0x80|12), 4 },
+/* 9 Mb */ { AH_TRUE, QUART, 9000, 0x0d, 0x00, 18, 4 },
+/* 12 Mb */ { AH_TRUE, QUART, 12000, 0x08, 0x00, 24, 4 },
+/*13.5 Mb */ { AH_TRUE, QUART, 13500, 0x0c, 0x00, 27, 4 }
},
};

@@ -85,13 +87,13 @@ HAL_RATE_TABLE ar5212_turbog_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, TURBO, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, TURBO, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, TURBO, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, TURBO, 24000, 0x09, 0x00, (0x80|48), 3, 0, 0 },
-/* 36 Mb */ { AH_TRUE, TURBO, 36000, 0x0d, 0x00, 72, 3, 0, 0 },
-/* 48 Mb */ { AH_TRUE, TURBO, 48000, 0x08, 0x00, 96, 3, 0, 0 },
-/* 54 Mb */ { AH_TRUE, TURBO, 54000, 0x0c, 0x00, 108, 3, 0, 0 }
+/* 6 Mb */ { AH_TRUE, TURBO, 12000, 0x0b, 0x00, (0x80|12), 0 },
+/* 12 Mb */ { AH_TRUE, TURBO, 24000, 0x0a, 0x00, (0x80|24), 1 },
+/* 18 Mb */ { AH_TRUE, TURBO, 36000, 0x0e, 0x00, 36, 1 },
+/* 24 Mb */ { AH_TRUE, TURBO, 48000, 0x09, 0x00, (0x80|48), 2 },
+/* 36 Mb */ { AH_TRUE, TURBO, 72000, 0x0d, 0x00, 72, 2 },
+/* 48 Mb */ { AH_TRUE, TURBO, 96000, 0x08, 0x00, 96, 2 },
+/* 54 Mb */ { AH_TRUE, TURBO, 108000, 0x0c, 0x00, 108, 2 }
},
};

@@ -101,14 +103,14 @@ HAL_RATE_TABLE ar5212_turboa_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, TURBO, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, TURBO, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, TURBO, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, TURBO, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, TURBO, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, TURBO, 36000, 0x0d, 0x00, 72, 4, 0, 0 },
-/* 48 Mb */ { AH_TRUE, TURBO, 48000, 0x08, 0x00, 96, 4, 0, 0 },
-/* 54 Mb */ { AH_TRUE, TURBO, 54000, 0x0c, 0x00, 108, 4, 0, 0 }
+/* 6 Mb */ { AH_TRUE, TURBO, 12000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, TURBO, 18000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, TURBO, 24000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, TURBO, 36000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, TURBO, 48000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, TURBO, 72000, 0x0d, 0x00, 72, 4 },
+/* 48 Mb */ { AH_TRUE, TURBO, 96000, 0x08, 0x00, 96, 4 },
+/* 54 Mb */ { AH_TRUE, TURBO, 108000, 0x0c, 0x00, 108, 4 }
},
};

@@ -118,10 +120,10 @@ HAL_RATE_TABLE ar5212_11b_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0, 0, 0 },
-/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1, 0, 0 },
-/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 1, 0, 0 },
-/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 1, 0, 0 }
+/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0 },
+/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1 },
+/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 1 },
+/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 1 }
},
};

@@ -136,19 +138,19 @@ HAL_RATE_TABLE ar5212_11g_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0, 0, 0 },
-/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1, 0, 0 },
-/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 2, 0, 0 },
-/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 3, 0, 0 },
+/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0 },
+/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1 },
+/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 2 },
+/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 3 },
/* remove rates 6, 9 from rate ctrl */
-/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4, 0, 0 },
-/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8, 0, 0 }
+/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 },
+/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 },
+/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 },
+/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 },
+/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 },
+/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 },
+/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 },
+/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 }
},
};

diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_power.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_power.c
index dd79c3c..d0d8116 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_power.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_power.c
@@ -38,8 +38,8 @@ static HAL_BOOL
ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
{
#define AR_SCR_MASK \
- (AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
- AR_SCR_SLEPOL|AR_SCR_MIBIE)
+ (AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
+ AR_SCR_SLEPOL|AR_SCR_MIBIE|AR_SCR_UNKNOWN)
#define POWER_UP_TIME 2000
uint32_t scr, val;
int i;
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_recv.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_recv.c
index b69a2fc..ed631d5 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_recv.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_recv.c
@@ -163,6 +163,9 @@ ar5212GetRxFilter(struct ath_hal *ah)
bits |= HAL_RX_FILTER_PHYRADAR;
if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
bits |= HAL_RX_FILTER_PHYERR;
+ if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
+ (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
+ bits |= HAL_RX_FILTER_BSSID;
return bits;
}

@@ -172,10 +175,12 @@ ar5212GetRxFilter(struct ath_hal *ah)
void
ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
{
+ struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t phybits;

OS_REG_WRITE(ah, AR_RX_FILTER,
- bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR));
+ bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
+ HAL_RX_FILTER_BSSID));
phybits = 0;
if (bits & HAL_RX_FILTER_PHYRADAR)
phybits |= AR_PHY_ERR_RADAR;
@@ -189,6 +194,13 @@ ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
OS_REG_WRITE(ah, AR_RXCFG,
OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
}
+ if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
+ if (bits & HAL_RX_FILTER_BSSID)
+ ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
+ else
+ ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
+ OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+ }
}

/*
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_reset.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_reset.c
index 8200782..313e9cc 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_reset.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_reset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -34,24 +34,32 @@

static HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask);
/* NB: public for 5312 use */
-HAL_BOOL ar5212IsSpurChannel(struct ath_hal *, HAL_CHANNEL *);
-HAL_BOOL ar5212ChannelChange(struct ath_hal *, HAL_CHANNEL *);
-int16_t ar5212GetNf(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
-HAL_BOOL ar5212SetBoardValues(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
-void ar5212SetDeltaSlope(struct ath_hal *, HAL_CHANNEL *);
+HAL_BOOL ar5212IsSpurChannel(struct ath_hal *,
+ const struct ieee80211_channel *);
+HAL_BOOL ar5212ChannelChange(struct ath_hal *,
+ const struct ieee80211_channel *);
+int16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *);
+HAL_BOOL ar5212SetBoardValues(struct ath_hal *,
+ const struct ieee80211_channel *);
+void ar5212SetDeltaSlope(struct ath_hal *,
+ const struct ieee80211_channel *);
HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain);
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain);
static HAL_BOOL ar5212SetRateTable(struct ath_hal *,
- HAL_CHANNEL *, int16_t tpcScaleReduction, int16_t powerLimit,
+ const struct ieee80211_channel *, int16_t tpcScaleReduction,
+ int16_t powerLimit,
HAL_BOOL commit, int16_t *minPower, int16_t *maxPower);
static void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta);
-static void ar5212GetTargetPowers(struct ath_hal *, HAL_CHANNEL *,
+static void ar5212GetTargetPowers(struct ath_hal *,
+ const struct ieee80211_channel *,
const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels,
TRGT_POWER_INFO *pNewPower);
static uint16_t ar5212GetMaxEdgePower(uint16_t channel,
const RD_EDGES_POWER *pRdEdgesPower);
-void ar5212SetRateDurationTable(struct ath_hal *, HAL_CHANNEL *);
-void ar5212SetIFSTiming(struct ath_hal *, HAL_CHANNEL *);
+void ar5212SetRateDurationTable(struct ath_hal *,
+ const struct ieee80211_channel *);
+void ar5212SetIFSTiming(struct ath_hal *,
+ const struct ieee80211_channel *);

/* NB: public for RF backend use */
void ar5212GetLowerUpperValues(uint16_t value,
@@ -97,7 +105,8 @@ write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
*/
HAL_BOOL
ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+ struct ieee80211_channel *chan,
+ HAL_BOOL bChannelChange, HAL_STATUS *status)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
@@ -116,26 +125,11 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
int8_t twiceAntennaGain, twiceAntennaReduction;
uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow;
HAL_BOOL isBmode = AH_FALSE;
- HAL_BOOL ichan_isBmode = AH_FALSE;

HALASSERT(ah->ah_magic == AR5212_MAGIC);
ee = AH_PRIVATE(ah)->ah_eeprom;

OS_MARK(ah, AH_MARK_RESET, bChannelChange);
-#define IS(_c,_f) (((_c)->channelFlags & _f) || 0)
- if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
- if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
-#undef IS

/* Bring out of sleep mode */
if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
@@ -148,12 +142,8 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* Map public channel to private.
*/
ichan = ath_hal_checkchannel(ah, chan);
- if (ichan == AH_NULL) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ if (ichan == AH_NULL)
FAIL(HAL_EINVAL);
- }
switch (opmode) {
case HAL_M_STA:
case HAL_M_IBSS:
@@ -168,7 +158,6 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
}
HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);

- SAVE_CCK(ah, ichan, ichan_isBmode);
SAVE_CCK(ah, chan, isBmode);

/* Preserve certain DMA hardware registers on a channel change */
@@ -215,13 +204,13 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
*/
if (bChannelChange &&
(AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
- (chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
- ((chan->channelFlags & CHANNEL_ALL) ==
- (AH_PRIVATE(ah)->ah_curchan->channelFlags & CHANNEL_ALL))) {
+ (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&
+ ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) ==
+ (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {
if (ar5212ChannelChange(ah, chan)) {
/* If ChannelChange completed - skip the rest of reset */
/* XXX ani? */
- return AH_TRUE;
+ goto done;
}
}
}
@@ -258,31 +247,32 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
}

/* Setup the indices for the next set of register array writes */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- modesIndex = 1;
- freqIndex = 1;
- break;
- case CHANNEL_T:
- modesIndex = 2;
- freqIndex = 1;
- break;
- case CHANNEL_B:
- modesIndex = 3;
- freqIndex = 2;
- break;
- case CHANNEL_PUREG:
- modesIndex = 4;
- freqIndex = 2;
- break;
- case CHANNEL_108G:
- modesIndex = 5;
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
freqIndex = 2;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- FAIL(HAL_EINVAL);
+ if (IEEE80211_IS_CHAN_108G(chan))
+ modesIndex = 5;
+ else if (IEEE80211_IS_CHAN_G(chan))
+ modesIndex = 4;
+ else if (IEEE80211_IS_CHAN_B(chan))
+ modesIndex = 3;
+ else {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: invalid channel %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ FAIL(HAL_EINVAL);
+ }
+ } else {
+ freqIndex = 1;
+ if (IEEE80211_IS_CHAN_TURBO(chan))
+ modesIndex = 2;
+ else if (IEEE80211_IS_CHAN_A(chan))
+ modesIndex = 1;
+ else {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: invalid channel %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ FAIL(HAL_EINVAL);
+ }
}

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
@@ -293,11 +283,19 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
regWrites);
+#ifdef AH_RXCFG_SDMAMW_4BYTES
+ /*
+ * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx),
+ * use 4 instead. Enabling it on all platforms would hurt performance,
+ * so we only enable it on the ones that are affected by it.
+ */
+ OS_REG_WRITE(ah, AR_RXCFG, 0);
+#endif
ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

- if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) {
ar5212SetIFSTiming(ah, chan);
if (IS_5413(ah)) {
/*
@@ -319,7 +317,7 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
AR_PHY_ADC_CTL_OFF_PWDADC);

/* TX_PWR_ADJ */
- if (chan->channel == 2484) {
+ if (ichan->channel == 2484) {
cckOfdmPwrDelta = SCALE_OC_DELTA(
ee->ee_cckOfdmPwrDelta -
ee->ee_scaledCh14FilterCckDelta);
@@ -328,7 +326,7 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
ee->ee_cckOfdmPwrDelta);
}

- if (IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_G(chan)) {
OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
SM((ee->ee_cckOfdmPwrDelta*-1),
AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
@@ -365,8 +363,8 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);

if (IS_5413(ah) || IS_2417(ah)) {
- uint32_t newReg=1;
- if (IS_DISABLE_FAST_ADC_CHAN(chan->channel))
+ uint32_t newReg = 1;
+ if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel))
newReg = 0;
/* As it's a clock changing register, only write when the value needs to be changed */
if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg)
@@ -374,29 +372,29 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
}

/* Setup the transmit power values. */
- if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
+ if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error init'ing transmit power\n", __func__);
FAIL(HAL_EIO);
}

/* Write the analog registers */
- if (!ahp->ah_rfHal->setRfRegs(ah, ichan, modesIndex, rfXpdGain)) {
+ if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
__func__);
FAIL(HAL_EIO);
}

/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
- if (IS_CHAN_OFDM(chan)) {
- if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
- (!IS_CHAN_B(chan)))
- ar5212SetSpurMitigation(ah, ichan);
+ if (IEEE80211_IS_CHAN_OFDM(chan)) {
+ if (IS_5413(ah) ||
+ AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)
+ ar5212SetSpurMitigation(ah, chan);
ar5212SetDeltaSlope(ah, chan);
}

/* Setup board specific options for EEPROM version 3 */
- if (!ar5212SetBoardValues(ah, ichan)) {
+ if (!ar5212SetBoardValues(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error setting board options\n", __func__);
FAIL(HAL_EIO);
@@ -439,7 +437,7 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

- if (!ar5212SetChannel(ah, ichan))
+ if (!ar5212SetChannel(ah, chan))
FAIL(HAL_EIO);

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
@@ -450,10 +448,9 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,

/* Set Tx frame start to tx data start delay */
if (IS_RAD5112_ANY(ah) &&
- (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan) ||
- IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan))) {
+ (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) {
txFrm2TxDStart =
- (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) ?
+ IEEE80211_IS_CHAN_HALF(chan) ?
TX_FRAME_D_START_HALF_RATE:
TX_FRAME_D_START_QUARTER_RATE;
OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
@@ -482,7 +479,7 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* Value is in 100ns increments.
*/
synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
- if (IS_CHAN_CCK(chan)) {
+ if (IEEE80211_IS_CHAN_B(chan)) {
synthDelay = (4 * synthDelay) / 22;
} else {
synthDelay /= 10;
@@ -498,9 +495,9 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* extra BASE_ACTIVATE_DELAY usecs to ensure this condition
* does not happen.
*/
- if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
- } else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
} else {
OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
@@ -524,7 +521,7 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
| AR_PHY_AGC_CONTROL_CAL
| AR_PHY_AGC_CONTROL_NF);

- if (!IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
+ if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
@@ -605,7 +602,7 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
SM(0, AR_NOACK_BYTE_OFFSET));

/* Get Antenna Gain reduction */
- if (IS_CHAN_5GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_5GHZ(chan)) {
ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain);
} else {
ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain);
@@ -616,27 +613,27 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
/* TPC for self-generated frames */

ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK);
- if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > ichan->maxTxPower)
- ackTpcPow = ichan->maxTxPower+ahp->ah_txPowerIndexOffset;
+ if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower)
+ ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset;

- if (ackTpcPow > (2*ichan->maxRegTxPower - twiceAntennaReduction))
- ackTpcPow = (2*ichan->maxRegTxPower - twiceAntennaReduction)
+ if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction))
+ ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction)
+ ahp->ah_txPowerIndexOffset;

ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS);
- if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > ichan->maxTxPower)
- ctsTpcPow = ichan->maxTxPower+ahp->ah_txPowerIndexOffset;
+ if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower)
+ ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset;

- if (ctsTpcPow > (2*ichan->maxRegTxPower - twiceAntennaReduction))
- ctsTpcPow = (2*ichan->maxRegTxPower - twiceAntennaReduction)
+ if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction))
+ ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction)
+ ahp->ah_txPowerIndexOffset;

chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP);
- if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > ichan->maxTxPower)
- chirpTpcPow = ichan->maxTxPower+ahp->ah_txPowerIndexOffset;
+ if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower)
+ chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset;

- if (chirpTpcPow > (2*ichan->maxRegTxPower - twiceAntennaReduction))
- chirpTpcPow = (2*ichan->maxRegTxPower - twiceAntennaReduction)
+ if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction))
+ chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction)
+ ahp->ah_txPowerIndexOffset;

if (ackTpcPow > 63)
@@ -667,32 +664,24 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
-
- if (bChannelChange) {
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
- chan->maxRegTxPower = ichan->maxRegTxPower;
- chan->maxTxPower = ichan->maxTxPower;
- chan->minTxPower = ichan->minTxPower;
- }
+#if 0
+done:
+#endif
+ if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
+ chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

- RESTORE_CCK(ah, ichan, ichan_isBmode);
RESTORE_CCK(ah, chan, isBmode);

OS_MARK(ah, AH_MARK_RESET_DONE, 0);

return AH_TRUE;
bad:
- if (ichan != AH_NULL)
- RESTORE_CCK(ah, ichan, ichan_isBmode);
RESTORE_CCK(ah, chan, isBmode);

OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
- if (*status)
+ if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
@@ -703,7 +692,7 @@ bad:
* Call the rf backend to change the channel.
*/
HAL_BOOL
-ar5212SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
struct ath_hal_5212 *ahp = AH5212(ah);

@@ -720,7 +709,7 @@ ar5212SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* time, the function returns false as a reset is necessary
*/
HAL_BOOL
-ar5212ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t ulCount;
uint32_t data, synthDelay, qnum;
@@ -754,7 +743,7 @@ ar5212ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
return AH_FALSE;

/* Change the synth */
- if (!ar5212SetChannel(ah, ichan))
+ if (!ar5212SetChannel(ah, chan))
return AH_FALSE;

/*
@@ -762,7 +751,7 @@ ar5212ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
* Read the phy active delay register. Value is in 100ns increments.
*/
data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
- if (IS_CHAN_CCK(ichan)) {
+ if (IEEE80211_IS_CHAN_B(chan)) {
synthDelay = (4 * data) / 22;
} else {
synthDelay = data / 10;
@@ -770,17 +759,17 @@ ar5212ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);

/* Setup the transmit power values. */
- if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
+ if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error init'ing transmit power\n", __func__);
return AH_FALSE;
}

/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
- if (IS_CHAN_OFDM(ichan)) {
- if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
- (!IS_CHAN_B(chan)))
- ar5212SetSpurMitigation(ah, ichan);
+ if (IEEE80211_IS_CHAN_OFDM(chan)) {
+ if (IS_5413(ah) ||
+ AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)
+ ar5212SetSpurMitigation(ah, chan);
ar5212SetDeltaSlope(ah, chan);
}

@@ -789,14 +778,6 @@ ar5212ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)

/* Start Noise Floor Cal */
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
-
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
- chan->maxRegTxPower = ichan->maxRegTxPower;
- chan->maxTxPower = ichan->maxTxPower;
- chan->minTxPower = ichan->minTxPower;
return AH_TRUE;
}

@@ -860,10 +841,10 @@ ar5212Disable(struct ath_hal *ah)
* WARNING: The order of the PLL and mode registers must be correct.
*/
HAL_BOOL
-ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
{

- OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
+ OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);

/*
* Reset the HW - PCI must be reset after the rest of the
@@ -895,48 +876,47 @@ ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)

if (IS_5413(ah)) { /* NB: =>'s 5424 also */
rfMode = AR_PHY_MODE_AR5112;
- if (IS_CHAN_HALF_RATE(chan))
+ if (IEEE80211_IS_CHAN_HALF(chan))
rfMode |= AR_PHY_MODE_HALF;
- else if (IS_CHAN_QUARTER_RATE(chan))
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
rfMode |= AR_PHY_MODE_QUARTER;

- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+ if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44_5112;
else
phyPLL = AR_PHY_PLL_CTL_40_5413;
} else if (IS_RAD5111(ah)) {
rfMode = AR_PHY_MODE_AR5111;
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+ if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44;
else
phyPLL = AR_PHY_PLL_CTL_40;
- if (IS_CHAN_HALF_RATE(chan))
+ if (IEEE80211_IS_CHAN_HALF(chan))
phyPLL = AR_PHY_PLL_CTL_HALF;
- else if (IS_CHAN_QUARTER_RATE(chan))
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
phyPLL = AR_PHY_PLL_CTL_QUARTER;
} else { /* 5112, 2413, 2316, 2317 */
rfMode = AR_PHY_MODE_AR5112;
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+ if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44_5112;
else
phyPLL = AR_PHY_PLL_CTL_40_5112;
- if (IS_CHAN_HALF_RATE(chan))
+ if (IEEE80211_IS_CHAN_HALF(chan))
phyPLL |= AR_PHY_PLL_CTL_HALF;
- else if (IS_CHAN_QUARTER_RATE(chan))
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
phyPLL |= AR_PHY_PLL_CTL_QUARTER;
}
- if (IS_CHAN_OFDM(chan) && (IS_CHAN_CCK(chan) ||
- IS_CHAN_G(chan)))
+ if (IEEE80211_IS_CHAN_G(chan))
rfMode |= AR_PHY_MODE_DYNAMIC;
- else if (IS_CHAN_OFDM(chan))
+ else if (IEEE80211_IS_CHAN_OFDM(chan))
rfMode |= AR_PHY_MODE_OFDM;
else
rfMode |= AR_PHY_MODE_CCK;
- if (IS_CHAN_5GHZ(chan))
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
rfMode |= AR_PHY_MODE_RF5GHZ;
else
rfMode |= AR_PHY_MODE_RF2GHZ;
- turbo = IS_CHAN_TURBO(chan) ?
+ turbo = IEEE80211_IS_CHAN_TURBO(chan) ?
(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;
curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
/*
@@ -946,7 +926,7 @@ ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
* mode bit is set
* - Turbo cannot be set at the same time as CCK or DYNAMIC
*/
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
if (curPhyPLL != phyPLL) {
@@ -972,8 +952,9 @@ ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
* changes.
*/
HAL_BOOL
-ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
- HAL_BOOL longCal, HAL_BOOL *isCalDone)
+ar5212PerCalibrationN(struct ath_hal *ah,
+ struct ieee80211_channel *chan,
+ u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone)
{
#define IQ_CAL_TRIES 10
struct ath_hal_5212 *ahp = AH5212(ah);
@@ -981,19 +962,17 @@ ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
int32_t qCoff, qCoffDenom;
int32_t iqCorrMeas, iCoff, iCoffDenom;
uint32_t powerMeasQ, powerMeasI;
- HAL_BOOL ichan_isBmode = AH_FALSE;
HAL_BOOL isBmode = AH_FALSE;

- OS_MARK(ah, AH_MARK_PERCAL, chan->channel);
+ OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);
*isCalDone = AH_FALSE;
ichan = ath_hal_checkchannel(ah, chan);
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
return AH_FALSE;
}
- SAVE_CCK(ah, ichan, ichan_isBmode);
SAVE_CCK(ah, chan, isBmode);

if (ahp->ah_bIQCalibration == IQ_CAL_DONE ||
@@ -1019,11 +998,16 @@ ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
if (powerMeasI && powerMeasQ)
break;
/* Do we really need this??? */
- OS_REG_WRITE (ah, AR_PHY_TIMING_CTRL4,
- OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
- AR_PHY_TIMING_CTRL4_DO_IQCAL);
+ OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
+ AR_PHY_TIMING_CTRL4_DO_IQCAL);
} while (++i < IQ_CAL_TRIES);

+ HALDEBUG(ah, HAL_DEBUG_PERCAL,
+ "%s: IQ cal finished: %d tries\n", __func__, i);
+ HALDEBUG(ah, HAL_DEBUG_PERCAL,
+ "%s: powerMeasI %u powerMeasQ %u iqCorrMeas %d\n",
+ __func__, powerMeasI, powerMeasQ, iqCorrMeas);
+
/*
* Prescale these values to remove 64-bit operation
* requirement at the loss of a little precision.
@@ -1050,19 +1034,7 @@ ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
}

HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "****************** MISGATED IQ CAL! *******************\n");
- HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "time = %d, i = %d, \n", OS_GETUPTIME(ah), i);
- HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "powerMeasI = 0x%08x\n", powerMeasI);
- HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "powerMeasQ = 0x%08x\n", powerMeasQ);
- HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "iqCorrMeas = 0x%08x\n", iqCorrMeas);
- HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "iCoff = %d\n", iCoff);
- HALDEBUG(ah, HAL_DEBUG_PERCAL,
- "qCoff = %d\n", qCoff);
+ "%s: iCoff %d qCoff %d\n", __func__, iCoff, qCoff);

/* Write values and enable correction */
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
@@ -1073,12 +1045,13 @@ ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);

ahp->ah_bIQCalibration = IQ_CAL_DONE;
- ichan->iqCalValid = AH_TRUE;
+ ichan->privFlags |= CHANNEL_IQVALID;
ichan->iCoff = iCoff;
ichan->qCoff = qCoff;
}
- } else if (!IS_CHAN_B(chan) && ahp->ah_bIQCalibration == IQ_CAL_DONE &&
- !ichan->iqCalValid) {
+ } else if (!IEEE80211_IS_CHAN_B(chan) &&
+ ahp->ah_bIQCalibration == IQ_CAL_DONE &&
+ (ichan->privFlags & CHANNEL_IQVALID) == 0) {
/*
* Start IQ calibration if configured channel has changed.
* Use a magic number of 15 based on default value.
@@ -1094,20 +1067,14 @@ ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,

if (longCal) {
/* Check noise floor results */
- ar5212GetNf(ah, ichan);
-
- if ((ichan->channelFlags & CHANNEL_CW_INT) == 0) {
+ ar5212GetNf(ah, chan);
+ if (!IEEE80211_IS_CHAN_CWINT(chan)) {
/* Perform cal for 5Ghz channels and any OFDM on 5112 */
- if (IS_CHAN_5GHZ(chan) ||
- (IS_RAD5112(ah) && IS_CHAN_OFDM(chan)))
+ if (IEEE80211_IS_CHAN_5GHZ(chan) ||
+ (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan)))
ar5212RequestRfgain(ah);
- } else {
- /* report up and clear internal state */
- chan->channelFlags |= CHANNEL_CW_INT;
- ichan->channelFlags &= ~CHANNEL_CW_INT;
}
}
- RESTORE_CCK(ah, ichan, ichan_isBmode);
RESTORE_CCK(ah, chan, isBmode);

return AH_TRUE;
@@ -1115,15 +1082,25 @@ ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
}

HAL_BOOL
-ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+ar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
+ HAL_BOOL *isIQdone)
{
return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
}

HAL_BOOL
-ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
- /* XXX */
+ HAL_CHANNEL_INTERNAL *ichan;
+
+ ichan = ath_hal_checkchannel(ah, chan);
+ if (ichan == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: invalid channel %u/0x%x; no mapping\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ return AH_FALSE;
+ }
+ ichan->privFlags &= ~CHANNEL_IQVALID;
return AH_TRUE;
}

@@ -1138,7 +1115,7 @@ ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask)

/* XXX ar5212MacStop & co. */

- if (IS_PCIE(ah)) {
+ if (AH_PRIVATE(ah)->ah_ispcie) {
resetMask &= ~AR_RC_PCI;
}

@@ -1181,26 +1158,28 @@ ar5212GetNoiseFloor(struct ath_hal *ah)
}

static HAL_BOOL
-getNoiseFloorThresh(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *chan,
+getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan,
int16_t *nft)
{
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;

HALASSERT(ah->ah_magic == AR5212_MAGIC);

- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
*nft = ee->ee_noiseFloorThresh[headerInfo11A];
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
*nft = ee->ee_noiseFloorThresh[headerInfo11B];
break;
- case CHANNEL_PUREG:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_PUREG: /* NB: really 108G */
*nft = ee->ee_noiseFloorThresh[headerInfo11G];
break;
default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: invalid channel flags %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
return AH_FALSE;
}
return AH_TRUE;
@@ -1260,18 +1239,19 @@ ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX])
* Read the NF and check it against the noise floor threshhold
*/
int16_t
-ar5212GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan)
{
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212NfCalHist *h = &ahp->ah_nfCalHist;
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int16_t nf, nfThresh;
int32_t val;

if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: NF did not complete in calibration window\n", __func__);
- chan->rawNoiseFloor = h->privNF; /* most recent value */
- return chan->rawNoiseFloor;
+ ichan->rawNoiseFloor = h->privNF; /* most recent value */
+ return ichan->rawNoiseFloor;
}

/*
@@ -1288,7 +1268,7 @@ ar5212GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* happens it indicates a problem regardless
* of the band.
*/
- chan->channelFlags |= CHANNEL_CW_INT;
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
nf = 0;
}
} else
@@ -1342,7 +1322,7 @@ ar5212GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

- return (chan->rawNoiseFloor = nf);
+ return (ichan->rawNoiseFloor = nf);
}

/*
@@ -1379,7 +1359,7 @@ ar5212SetCompRegs(struct ath_hal *ah)

HAL_BOOL
ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
- const HAL_CHANNEL_INTERNAL *chan)
+ const struct ieee80211_channel *chan)
{
#define ANT_SWITCH_TABLE1 AR_PHY(88)
#define ANT_SWITCH_TABLE2 AR_PHY(89)
@@ -1387,25 +1367,30 @@ ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint32_t antSwitchA, antSwitchB;
int ix;
- HAL_BOOL isBmode = AH_FALSE;
- /* NB: need local copy for SAVE/RESTORE 'cuz chan is const */
- HAL_CHANNEL_INTERNAL ichan = *chan;

HALASSERT(ah->ah_magic == AR5212_MAGIC);
HALASSERT(ahp->ah_phyPowerOn);

- SAVE_CCK(ah, &ichan, isBmode);
- switch (ichan.channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A: ix = 0; break;
- case CHANNEL_B: ix = 1; break;
- case CHANNEL_PUREG: ix = 2; break;
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
+ ix = 0;
+ break;
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_PUREG: /* NB: 108G */
+ ix = 2;
+ break;
+ case IEEE80211_CHAN_B:
+ if (IS_2425(ah) || IS_2417(ah)) {
+ /* NB: Nala/Swan: 11b is handled using 11g */
+ ix = 2;
+ } else
+ ix = 1;
+ break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, ichan.channelFlags);
- RESTORE_CCK(ah, &ichan, isBmode);
+ __func__, chan->ic_flags);
return AH_FALSE;
}
- RESTORE_CCK(ah, &ichan, isBmode);

antSwitchA = ee->ee_antennaControl[1][ix]
| (ee->ee_antennaControl[2][ix] << 6)
@@ -1460,13 +1445,14 @@ ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
}

HAL_BOOL
-ar5212IsSpurChannel(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
- uint32_t clockFreq =
- ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32);
- return ( ((chan->channel % clockFreq) != 0)
- && (((chan->channel % clockFreq) < 10)
- || (((chan->channel) % clockFreq) > 22)) );
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
+ uint32_t clockFreq =
+ ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32);
+ return ( ((freq % clockFreq) != 0)
+ && (((freq % clockFreq) < 10)
+ || (((freq) % clockFreq) > 22)) );
}

/*
@@ -1474,7 +1460,7 @@ ar5212IsSpurChannel(struct ath_hal *ah, HAL_CHANNEL *chan)
* given the channel value.
*/
HAL_BOOL
-ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define NO_FALSE_DETECT_BACKOFF 2
#define CB22_FALSE_DETECT_BACKOFF 6
@@ -1484,32 +1470,33 @@ ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
int arrayMode, falseDectectBackoff;
- int is2GHz = IS_CHAN_2GHZ(chan);
+ int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int8_t adcDesiredSize, pgaDesiredSize;
uint16_t switchSettling, txrxAtten, rxtxMargin;
int iCoff, qCoff;

HALASSERT(ah->ah_magic == AR5212_MAGIC);

- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_T:
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) {
+ case IEEE80211_CHAN_A:
+ case IEEE80211_CHAN_ST:
arrayMode = headerInfo11A;
if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah))
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
AR_PHY_FRAME_CTL_TX_CLIP,
ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]);
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
arrayMode = headerInfo11B;
break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_108G:
arrayMode = headerInfo11G;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -1524,7 +1511,7 @@ ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
(ee->ee_noiseFloorThresh[arrayMode] & 0x1FF)
| (1 << 9));

- if (ee->ee_version >= AR_EEPROM_VER5_0 && IS_CHAN_TURBO(chan)) {
+ if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) {
switchSettling = ee->ee_switchSettlingTurbo[is2GHz];
adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz];
pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz];
@@ -1565,18 +1552,17 @@ ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
if (ee->ee_version < AR_EEPROM_VER3_3) {
/* XXX magic number */
if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
- IS_CHAN_OFDM(chan))
+ IEEE80211_IS_CHAN_OFDM(chan))
falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
} else {
- if (ar5212IsSpurChannel(ah, (HAL_CHANNEL *)chan)) {
+ if (ar5212IsSpurChannel(ah, chan))
falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
- }
}
AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE);

- if (chan->iqCalValid) {
- iCoff = chan->iCoff;
- qCoff = chan->qCoff;
+ if (ichan->privFlags & CHANNEL_IQVALID) {
+ iCoff = ichan->iCoff;
+ qCoff = ichan->qCoff;
} else {
iCoff = ee->ee_iqCalI[is2GHz];
qCoff = ee->ee_iqCalQ[is2GHz];
@@ -1591,7 +1577,7 @@ ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);

if (ee->ee_version >= AR_EEPROM_VER4_1) {
- if (!IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0)
+ if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0)
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin);
}
@@ -1612,7 +1598,8 @@ ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
*/

void
-ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
+ar5212SetSpurMitigation(struct ath_hal *ah,
+ const struct ieee80211_channel *chan)
{
uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0};
uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan;
@@ -1621,7 +1608,8 @@ ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
static const uint16_t magMapFor4[4] = {1, 2, 2, 1};
static const uint16_t magMapFor3[3] = {1, 2, 1};
const uint16_t *pMagMap;
- HAL_BOOL is2GHz = IS_CHAN_2GHZ(ichan);
+ HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
uint32_t val;

#define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 )
@@ -1643,7 +1631,7 @@ ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
*/
finalSpur = AR_NO_SPUR;
spurDetectWidth = HAL_SPUR_CHAN_WIDTH;
- if (IS_CHAN_TURBO(ichan))
+ if (IEEE80211_IS_CHAN_TURBO(chan))
spurDetectWidth *= 2;

/* Decide if any spur affects the current channel */
@@ -1698,23 +1686,22 @@ ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
* spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21
* spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11
*/
- switch (ichan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A: /* Chip Frequency & sampleFrequency are 40 MHz */
- spurDeltaPhase = (spurOffset << 17) / 25;
+ if (IEEE80211_IS_CHAN_TURBO(chan)) {
+ /* Chip Frequency & sampleFrequency are 80 MHz */
+ spurDeltaPhase = (spurOffset << 16) / 25;
spurFreqSd = spurDeltaPhase >> 10;
- binWidth = HAL_BIN_WIDTH_BASE_100HZ;
- break;
- case CHANNEL_G: /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */
+ binWidth = HAL_BIN_WIDTH_TURBO_100HZ;
+ } else if (IEEE80211_IS_CHAN_G(chan)) {
+ /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */
spurFreqSd = (spurOffset << 8) / 55;
spurDeltaPhase = (spurOffset << 17) / 25;
binWidth = HAL_BIN_WIDTH_BASE_100HZ;
- break;
- case CHANNEL_T: /* Chip Frequency & sampleFrequency are 80 MHz */
- case CHANNEL_108G:
- spurDeltaPhase = (spurOffset << 16) / 25;
+ } else {
+ HALASSERT(!IEEE80211_IS_CHAN_B(chan));
+ /* Chip Frequency & sampleFrequency are 40 MHz */
+ spurDeltaPhase = (spurOffset << 17) / 25;
spurFreqSd = spurDeltaPhase >> 10;
- binWidth = HAL_BIN_WIDTH_TURBO_100HZ;
- break;
+ binWidth = HAL_BIN_WIDTH_BASE_100HZ;
}

/* Compute Pilot Mask */
@@ -1791,20 +1778,21 @@ ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
* Required for OFDM operation.
*/
void
-ar5212SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define COEF_SCALE_S 24
#define INIT_CLOCKMHZSCALED 0x64000000
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man;
unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED;

- if (IS_CHAN_TURBO(chan))
+ if (IEEE80211_IS_CHAN_TURBO(chan))
clockMhzScaled *= 2;
/* half and quarter rate can divide the scaled clock by 2 or 4 respectively */
/* scale for selected channel bandwidth */
- if (IS_CHAN_HALF_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
clockMhzScaled = clockMhzScaled >> 1;
- } else if (IS_CHAN_QUARTER_RATE(chan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
clockMhzScaled = clockMhzScaled >> 2;
}

@@ -1812,7 +1800,7 @@ ar5212SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL *chan)
* ALGO -> coef = 1e8/fcarrier*fclock/40;
* scaled coef to provide precision for this floating calculation
*/
- coef_scaled = clockMhzScaled / chan->channel;
+ coef_scaled = clockMhzScaled / freq;

/*
* ALGO -> coef_exp = 14-floor(log2(coef));
@@ -1850,15 +1838,14 @@ ar5212SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL *chan)
HAL_BOOL
ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
{
+ /* XXX blech, construct local writable copy */
+ struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan;
uint16_t dummyXpdGains[2];
- HAL_BOOL ret, isBmode = AH_FALSE;
+ HAL_BOOL isBmode;

- SAVE_CCK(ah, AH_PRIVATE(ah)->ah_curchan, isBmode);
+ SAVE_CCK(ah, &dummy, isBmode);
AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
- ret = ar5212SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan,
- dummyXpdGains);
- RESTORE_CCK(ah, AH_PRIVATE(ah)->ah_curchan, isBmode);
- return ret;
+ return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains);
}

/*
@@ -1866,8 +1853,8 @@ ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
* operating channel and mode.
*/
HAL_BOOL
-ar5212SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
- uint16_t *rfXpdGain)
+ar5212SetTransmitPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
{
#define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s)))
#define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s))
@@ -1875,6 +1862,7 @@ ar5212SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
static const uint16_t tpcScaleReductionTable[5] =
{ 0, 3, 6, 9, MAX_RATE_POWER };
struct ath_hal_5212 *ahp = AH5212(ah);
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
int16_t minPower, maxPower, tpcInDb, powerLimit;
int i;
@@ -1889,7 +1877,7 @@ ar5212SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
else
tpcInDb = 0;
- if (!ar5212SetRateTable(ah, (HAL_CHANNEL *) chan, tpcInDb, powerLimit,
+ if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit,
AH_TRUE, &minPower, &maxPower)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n",
__func__);
@@ -1924,10 +1912,10 @@ ar5212SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* Removed with revised chipset
*/
if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 &&
- IS_CHAN_G(chan)) {
+ IEEE80211_IS_CHAN_G(chan)) {
uint16_t cckOfdmPwrDelta;

- if (chan->channel == 2484)
+ if (freq == 2484)
cckOfdmPwrDelta = SCALE_OC_DELTA(
ee->ee_cckOfdmPwrDelta -
ee->ee_scaledCh14FilterCckDelta);
@@ -1994,11 +1982,12 @@ ar5212SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* operating channel and mode.
*/
static HAL_BOOL
-ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
- int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit,
- int16_t *pMinPower, int16_t *pMaxPower)
+ar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan,
+ int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit,
+ int16_t *pMinPower, int16_t *pMaxPower)
{
struct ath_hal_5212 *ahp = AH5212(ah);
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t *rpow = ahp->ah_ratesArray;
uint16_t twiceMaxEdgePower = MAX_RATE_POWER;
@@ -2014,7 +2003,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,

HALASSERT(ah->ah_magic == AR5212_MAGIC);

- twiceMaxRDPower = chan->maxRegTxPower * 2;
+ twiceMaxRDPower = chan->ic_maxregpower * 2;
*pMaxPower = -MAX_RATE_POWER;
*pMinPower = MAX_RATE_POWER;

@@ -2028,7 +2017,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
if (ee->ee_ctl[i] == cfgCtl ||
cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) {
rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
- twiceMinEdgePower = ar5212GetMaxEdgePower(chan->channel, rep);
+ twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep);
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
/* Find the minimum of all CTL edge powers that apply to this channel */
twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
@@ -2039,7 +2028,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
}
}

- if (IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_G(chan)) {
/* Check for a CCK CTL for 11G CCK powers */
cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B;
for (i = 0; i < ee->ee_numCtls; i++) {
@@ -2050,7 +2039,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
if (ee->ee_ctl[i] == cfgCtl ||
cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) {
rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
- twiceMinEdgePowerCck = ar5212GetMaxEdgePower(chan->channel, rep);
+ twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep);
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
/* Find the minimum of all CTL edge powers that apply to this channel */
twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck);
@@ -2066,7 +2055,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
}

/* Get Antenna Gain reduction */
- if (IS_CHAN_5GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_5GHZ(chan)) {
ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain);
} else {
ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain);
@@ -2074,9 +2063,9 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
twiceAntennaReduction =
ath_hal_getantennareduction(ah, chan, twiceAntennaGain);

- if (IS_CHAN_OFDM(chan)) {
+ if (IEEE80211_IS_CHAN_OFDM(chan)) {
/* Get final OFDM target powers */
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g,
ee->ee_numTargetPwr_11g, &targetPowerOfdm);
} else {
@@ -2095,7 +2084,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
* this unless specially configured. Then we limit
* power only for non-AP operation.
*/
- if (IS_CHAN_TURBO(chan)
+ if (IEEE80211_IS_CHAN_TURBO(chan)
#ifdef AH_ENABLE_AP_SUPPORT
&& AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
#endif
@@ -2112,7 +2101,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
* constraint on 2.4GHz channels.
*/
if (ee->ee_version >= AR_EEPROM_VER4_0 &&
- IS_CHAN_2GHZ(chan))
+ IEEE80211_IS_CHAN_2GHZ(chan))
scaledPower = AH_MIN(scaledPower,
ee->ee_turbo2WMaxPower2);
}
@@ -2136,7 +2125,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,

if (ee->ee_version >= AR_EEPROM_VER4_0) {
/* Setup XR target power from EEPROM */
- rpow[15] = AH_MIN(scaledPower, IS_CHAN_2GHZ(chan) ?
+ rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ?
ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5);
} else {
/* XR uses 6mb power */
@@ -2156,11 +2145,11 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
"TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n",
__func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5,
twiceMaxEdgePower, tpcScaleReduction * 2,
- chan->channel, chan->channelFlags,
+ chan->ic_freq, chan->ic_flags,
maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower);
}

- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
/* Get final CCK target powers */
ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b,
ee->ee_numTargetPwr_11b, &targetPowerCck);
@@ -2200,7 +2189,7 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
"%s: cck: MaxRD: %d MaxCTL: %d "
"TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n",
__func__, twiceMaxRDPower, twiceMaxEdgePowerCck,
- tpcScaleReduction * 2, chan->channel, chan->channelFlags,
+ tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags,
maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower);
}
if (commit) {
@@ -2211,32 +2200,31 @@ ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
}

HAL_BOOL
-ar5212GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+ar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)
{
struct ath_hal_5212 *ahp = AH5212(ah);
+#if 0
static const uint16_t tpcScaleReductionTable[5] =
{ 0, 3, 6, 9, MAX_RATE_POWER };
- int16_t minPower, maxPower, tpcInDb, powerLimit;
- HAL_CHANNEL *chan;
- int i;
+ int16_t tpcInDb, powerLimit;
+#endif
+ int16_t minPower, maxPower;

/*
* Get Pier table max and min powers.
*/
- for (i = 0; i < nchans; i++) {
- chan = &chans[i];
- if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
- /* NB: rf code returns 1/4 dBm units, convert */
- chan->maxTxPower = maxPower / 2;
- chan->minTxPower = minPower / 2;
- } else {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: no min/max power for %u/0x%x\n",
- __func__, chan->channel, chan->channelFlags);
- chan->maxTxPower = MAX_RATE_POWER;
- chan->minTxPower = 0;
- }
+ if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
+ /* NB: rf code returns 1/4 dBm units, convert */
+ chan->ic_maxpower = maxPower / 2;
+ chan->ic_minpower = minPower / 2;
+ } else {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: no min/max power for %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ chan->ic_maxpower = MAX_RATE_POWER;
+ chan->ic_minpower = 0;
}
+#if 0
/*
* Now adjust to reflect any global scale and/or CTL's.
* (XXX is that correct?)
@@ -2246,25 +2234,19 @@ ar5212GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans
tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
else
tpcInDb = 0;
- for (i=0; i<nchans; i++) {
- chan = &chans[i];
- if (!ar5212SetRateTable(ah, (HAL_CHANNEL *) chan, tpcInDb, powerLimit,
- AH_FALSE, &minPower, &maxPower)) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: unable to find max/min power\n",__func__);
- return AH_FALSE;
- }
- if (maxPower < chan->maxTxPower)
- chan->maxTxPower = maxPower;
- if (minPower < chan->minTxPower)
- chan->minTxPower = minPower;
- }
-#ifdef AH_DEBUG
- for (i=0; i<nchans; i++) {
- HALDEBUG(ah, HAL_DEBUG_RESET,
- "Chan %d: MaxPow = %d MinPow = %d\n",
- chans[i].channel,chans[i].maxTxPower, chans[i].minTxPower);
+ if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit,
+ AH_FALSE, &minPower, &maxPower)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: unable to find max/min power\n",__func__);
+ return AH_FALSE;
}
+ if (maxPower < chan->ic_maxpower)
+ chan->ic_maxpower = maxPower;
+ if (minPower < chan->ic_minpower)
+ chan->ic_minpower = minPower;
+ HALDEBUG(ah, HAL_DEBUG_RESET,
+ "Chan %d: MaxPow = %d MinPow = %d\n",
+ chan->ic_freq, chan->ic_maxpower, chans->ic_minpower);
#endif
return AH_TRUE;
}
@@ -2362,7 +2344,7 @@ ar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower)
{
/* temp array for holding edge channels */
uint16_t tempChannelList[NUM_EDGES];
- uint16_t clo = 0, chi = 0, twiceMaxEdgePower;
+ uint16_t clo, chi, twiceMaxEdgePower;
int i, numEdges;

/* Get the edge power */
@@ -2434,20 +2416,21 @@ interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
* channel, and number of channels
*/
static void
-ar5212GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
const TRGT_POWER_INFO *powInfo,
uint16_t numChannels, TRGT_POWER_INFO *pNewPower)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
/* temp array for holding target power channels */
uint16_t tempChannelList[NUM_TEST_FREQUENCIES];
- uint16_t clo = 0, chi = 0, ixlo, ixhi;
+ uint16_t clo, chi, ixlo, ixhi;
int i;

/* Copy the target powers into the temp channel list */
for (i = 0; i < numChannels; i++)
tempChannelList[i] = powInfo[i].testChannel;

- ar5212GetLowerUpperValues(chan->channel, tempChannelList,
+ ar5212GetLowerUpperValues(freq, tempChannelList,
numChannels, &clo, &chi);

/* Get the indices for the channel */
@@ -2466,13 +2449,13 @@ ar5212GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL *chan,
* Get the lower and upper channels, target powers,
* and interpolate between them.
*/
- pNewPower->twicePwr6_24 = interpolate(chan->channel, clo, chi,
+ pNewPower->twicePwr6_24 = interpolate(freq, clo, chi,
powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24);
- pNewPower->twicePwr36 = interpolate(chan->channel, clo, chi,
+ pNewPower->twicePwr36 = interpolate(freq, clo, chi,
powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36);
- pNewPower->twicePwr48 = interpolate(chan->channel, clo, chi,
+ pNewPower->twicePwr48 = interpolate(freq, clo, chi,
powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48);
- pNewPower->twicePwr54 = interpolate(chan->channel, clo, chi,
+ pNewPower->twicePwr54 = interpolate(freq, clo, chi,
powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54);
}

@@ -2576,19 +2559,20 @@ ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits,
* by the turbo ratetable only
*/
void
-ar5212SetRateDurationTable(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212SetRateDurationTable(struct ath_hal *ah,
+ const struct ieee80211_channel *chan)
{
const HAL_RATE_TABLE *rt;
int i;

/* NB: band doesn't matter for 1/2 and 1/4 rate */
- if (IS_CHAN_HALF_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE);
- } else if (IS_CHAN_QUARTER_RATE(chan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE);
} else {
rt = ar5212GetRateTable(ah,
- IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G);
+ IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G);
}

for (i = 0; i < rt->rateCount; ++i)
@@ -2597,7 +2581,7 @@ ar5212SetRateDurationTable(struct ath_hal *ah, HAL_CHANNEL *chan)
ath_hal_computetxtime(ah, rt,
WLAN_CTRL_FRAME_SIZE,
rt->info[i].controlRate, AH_FALSE));
- if (!IS_CHAN_TURBO(chan)) {
+ if (!IEEE80211_IS_CHAN_TURBO(chan)) {
/* 11g Table is used to cover the CCK rates. */
rt = ar5212GetRateTable(ah, HAL_MODE_11G);
for (i = 0; i < rt->rateCount; ++i) {
@@ -2628,14 +2612,15 @@ ar5212SetRateDurationTable(struct ath_hal *ah, HAL_CHANNEL *chan)
* + IFS params: slot, eifs, misc etc.
*/
void
-ar5212SetIFSTiming(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec;

- HALASSERT(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan));
+ HALASSERT(IEEE80211_IS_CHAN_HALF(chan) ||
+ IEEE80211_IS_CHAN_QUARTER(chan));

refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32;
- if (IS_CHAN_HALF_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
slot = IFS_SLOT_HALF_RATE;
rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S;
txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S;
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_rfgain.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_rfgain.c
index 7b854b9..b07e3b8 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_rfgain.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_rfgain.c
@@ -239,34 +239,36 @@ ar5212AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)
/*
* Read rf register to determine if gainF needs correction
*/
-static void
+static uint32_t
ar5212GetGainFCorrection(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- GAIN_VALUES *gv = &ahp->ah_gainValues;
+ uint32_t correction;

HALASSERT(IS_RADX112_REV2(ah));

- gv->gainFCorrection = 0;
+ correction = 0;
if (ar5212GetRfField(ar5212GetRfBank(ah, 7), 1, 36, 0) == 1) {
+ const GAIN_VALUES *gv = &ahp->ah_gainValues;
uint32_t mixGain = gv->currStep->paramVal[0];
uint32_t gainStep =
ar5212GetRfField(ar5212GetRfBank(ah, 7), 4, 32, 0);
switch (mixGain) {
case 0 :
- gv->gainFCorrection = 0;
+ correction = 0;
break;
case 1 :
- gv->gainFCorrection = gainStep;
+ correction = gainStep;
break;
case 2 :
- gv->gainFCorrection = 2 * gainStep - 5;
+ correction = 2 * gainStep - 5;
break;
case 3 :
- gv->gainFCorrection = 2 * gainStep;
+ correction = 2 * gainStep;
break;
}
}
+ return correction;
}

/*
@@ -280,7 +282,8 @@ ar5212GetRfgain(struct ath_hal *ah)
GAIN_VALUES *gv = &ahp->ah_gainValues;
uint32_t rddata, probeType;

- if (!gv->active)
+ /* NB: beware of touching the BB when PHY is powered down */
+ if (!gv->active || !ahp->ah_phyPowerOn)
return HAL_RFGAIN_INACTIVE;

if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) {
@@ -302,9 +305,9 @@ ar5212GetRfgain(struct ath_hal *ah)
gv->currGain += PHY_PROBE_CCK_CORRECTION;
}
if (IS_RADX112_REV2(ah)) {
- ar5212GetGainFCorrection(ah);
- if (gv->currGain >= gv->gainFCorrection)
- gv->currGain -= gv->gainFCorrection;
+ uint32_t correct = ar5212GetGainFCorrection(ah);
+ if (gv->currGain >= correct)
+ gv->currGain -= correct;
else
gv->currGain = 0;
}
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_xmit.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_xmit.c
index ac195e2..23b1a89 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212_xmit.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212_xmit.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -48,16 +48,19 @@ ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
uint32_t txcfg, curLevel, newLevel;
HAL_INT omask;

+ if (ahp->ah_txTrigLev >= ahp->ah_maxTxTrigLev)
+ return AH_FALSE;
+
/*
* Disable interrupts while futzing with the fifo level.
*/
- omask = ar5212SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
+ omask = ath_hal_setInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);

txcfg = OS_REG_READ(ah, AR_TXCFG);
curLevel = MS(txcfg, AR_FTRIG);
newLevel = curLevel;
if (bIncTrigLevel) { /* increase the trigger level */
- if (curLevel < MAX_TX_FIFO_THRESHOLD)
+ if (curLevel < ahp->ah_maxTxTrigLev)
newLevel++;
} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
newLevel--;
@@ -66,8 +69,10 @@ ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
OS_REG_WRITE(ah, AR_TXCFG,
(txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));

+ ahp->ah_txTrigLev = newLevel;
+
/* re-enable chip interrupts */
- ar5212SetInterrupts(ah, omask);
+ ath_hal_setInterrupts(ah, omask);

return (newLevel != curLevel);
}
@@ -263,7 +268,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
{
struct ath_hal_5212 *ahp = AH5212(ah);
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_TX_QUEUE_INFO *qi;
uint32_t cwMin, chanCwMin, value, qmisc, dmisc;

@@ -286,7 +291,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
* Select cwmin according to channel type.
* NB: chan can be NULL during attach
*/
- if (chan && IS_CHAN_B(chan))
+ if (chan && IEEE80211_IS_CHAN_B(chan))
chanCwMin = INIT_CWMIN_11B;
else
chanCwMin = INIT_CWMIN;
@@ -869,16 +874,13 @@ ar5212ProcTxDesc(struct ath_hal *ah,
ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
break;
case 1:
- ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1) |
- HAL_TXSTAT_ALTRATE;
+ ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
break;
case 2:
- ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2) |
- HAL_TXSTAT_ALTRATE;
+ ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
break;
case 3:
- ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3) |
- HAL_TXSTAT_ALTRATE;
+ ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
break;
}
ts->ts_rssi = MS(ads->ds_txstatus1, AR_AckSigStrength);
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212phy.h b/sys/external/isc/atheros_hal/dist/ar5212/ar5212phy.h
index 42bf651..12cd3df 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212phy.h
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212phy.h
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5212phy.h,v 1.1.1.1 2008/12/11 04:46:43 alc Exp $
+ * $FreeBSD$
*/
#ifndef _DEV_ATH_AR5212PHY_H_
#define _DEV_ATH_AR5212PHY_H_
diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h b/sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h
index 01799f0..c2b3363 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h
@@ -463,7 +463,8 @@
#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */
#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */
#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */
-#define AR_ISR_S2_RESV0 0xE0F8FC00 /* Reserved */
+#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */
+#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */

#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
@@ -531,8 +532,14 @@
#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */
#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */
#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */
-#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */
-#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */
+#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */
+#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */
+
+/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */
+#define AR_IMR_SR2_BCNMISC \
+ (AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \
+ AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \
+ AR_IMR_S2_TBTT)

#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
@@ -693,6 +700,7 @@
#define AR_SCR_SLDWP 0x00080000 /* sleep duration write policy */
#define AR_SCR_SLEPOL 0x00100000 /* sleep policy mode */
#define AR_SCR_MIBIE 0x00200000 /* sleep perf cntrs MIB intr ena */
+#define AR_SCR_UNKNOWN 0x00400000

#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */

diff --git a/sys/external/isc/atheros_hal/dist/ar5212/ar5413.c b/sys/external/isc/atheros_hal/dist/ar5212/ar5413.c
index 7150424..ab6cc65 100644
--- a/sys/external/isc/atheros_hal/dist/ar5212/ar5413.c
+++ b/sys/external/isc/atheros_hal/dist/ar5212/ar5413.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5413.c,v 1.2 2009/01/06 06:03:57 mrg Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -75,29 +75,29 @@ ar5413WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar5413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;
- uint16_t freq;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, freq);

- if (chan->channel < 4800) {
+ if (freq < 4800) {
uint32_t txctl;

- if (((chan->channel - 2192) % 5) == 0) {
- channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+ if (((freq - 2192) % 5) == 0) {
+ channelSel = ((freq - 672) * 2 - 3040)/10;
bModeSynth = 0;
- } else if (((chan->channel - 2224) % 5) == 0) {
- channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+ } else if (((freq - 2224) % 5) == 0) {
+ channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -105,7 +105,7 @@ ar5413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
channelSel = ath_hal_reverseBits(channelSel, 8);

txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
- if (chan->channel == 2484) {
+ if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
@@ -113,26 +113,26 @@ ar5413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
- } else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
- freq = chan->channel - 2; /* Align to even 5MHz raster */
+ } else if (((freq % 5) == 2) && (freq <= 5435)) {
+ freq = freq - 2; /* Align to even 5MHz raster */
channelSel = ath_hal_reverseBits(
(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
aModeRefSel = ath_hal_reverseBits(0, 2);
- } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+ } else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 20 << 2), 8);
+ ((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
- } else if ((chan->channel % 10) == 0) {
+ } else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
- ((chan->channel - 4800) / 10 << 1), 8);
+ ((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
- } else if ((chan->channel % 5) == 0) {
+ } else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
- (chan->channel - 4800) / 5, 8);
+ (freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
- __func__, chan->channel);
+ __func__, freq);
return AH_FALSE;
}

@@ -154,7 +154,9 @@ ar5413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar5413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+ar5413SetRfRegs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
@@ -162,50 +164,49 @@ ar5413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5413[i][_col];\
} while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t ob5GHz = 0, db5GHz = 0;
uint16_t ob2GHz = 0, db2GHz = 0;
struct ar5413State *priv = AR5413(ah);
int regWrites = 0;

- HALDEBUG(ah, HAL_DEBUG_RFPARAM,
- "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
- __func__, chan->channel, chan->channelFlags, modesIndex);
+ HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
+ __func__, chan->ic_freq, chan->ic_flags, modesIndex);

HALASSERT(priv != AH_NULL);

/* Setup rf parameters */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_T:
- if (chan->channel > 4000 && chan->channel < 5260) {
+ switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
+ case IEEE80211_CHAN_A:
+ if (freq > 4000 && freq < 5260) {
ob5GHz = ee->ee_ob1;
db5GHz = ee->ee_db1;
- } else if (chan->channel >= 5260 && chan->channel < 5500) {
+ } else if (freq >= 5260 && freq < 5500) {
ob5GHz = ee->ee_ob2;
db5GHz = ee->ee_db2;
- } else if (chan->channel >= 5500 && chan->channel < 5725) {
+ } else if (freq >= 5500 && freq < 5725) {
ob5GHz = ee->ee_ob3;
db5GHz = ee->ee_db3;
- } else if (chan->channel >= 5725) {
+ } else if (freq >= 5725) {
ob5GHz = ee->ee_ob4;
db5GHz = ee->ee_db4;
} else {
/* XXX else */
}
break;
- case CHANNEL_B:
+ case IEEE80211_CHAN_B:
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
break;
- case CHANNEL_G:
- case CHANNEL_108G:
+ case IEEE80211_CHAN_G:
+ case IEEE80211_CHAN_PUREG: /* NB: really 108G */
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
+ __func__, chan->ic_flags);
return AH_FALSE;
}

@@ -222,7 +223,7 @@ ar5413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
RF_BANK_SETUP(priv, 6, modesIndex);

/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 241, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 238, 0);

@@ -231,7 +232,7 @@ ar5413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIn
ar5212ModifyRfBuffer(priv->Bank6Data, 1 , 1, 291, 2);

/* Optimum value for rf_pwd_iclobuf2G for PCIe chips only */
- if (IS_PCIE(ah)) {
+ if (AH_PRIVATE(ah)->ah_ispcie) {
ar5212ModifyRfBuffer(priv->Bank6Data, ath_hal_reverseBits(6, 3),
3, 131, 3);
}
@@ -338,7 +339,7 @@ ar5413FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
uint16_t ii, jj, kk;
int16_t currPwr = (int16_t)(2*Pmin);
/* since Pmin is pwr*2 and pwrList is 4*pwr */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;

ii = 0;
jj = 0;
@@ -403,7 +404,7 @@ ar5413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
#define VpdTable_I priv->vpdTable_I
uint32_t ii, jj, kk;
int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
- uint32_t idxL = 0, idxR = 0;
+ uint32_t idxL, idxR;
uint32_t numPdGainsUsed = 0;
/*
* If desired to support -ve power levels in future, just
@@ -537,10 +538,12 @@ ar5413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,

static HAL_BOOL
ar5413SetPowerTable(struct ath_hal *ah,
- int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
+ int16_t *minPower, int16_t *maxPower,
+ const struct ieee80211_channel *chan,
uint16_t *rfXpdGain)
{
struct ath_hal_5212 *ahp = AH5212(ah);
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
uint16_t pdGainOverlap_t2;
@@ -554,14 +557,14 @@ ar5413SetPowerTable(struct ath_hal *ah,
#endif

HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
- __func__, chan->channel,chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
- HALASSERT(IS_CHAN_5GHZ(chan));
+ HALASSERT(IEEE80211_IS_CHAN_5GHZ(chan));
pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
}

@@ -569,7 +572,7 @@ ar5413SetPowerTable(struct ath_hal *ah,
AR_PHY_TPCRG5_PD_GAIN_OVERLAP);

numPdGainsUsed = ar5413getGainBoundariesAndPdadcsForPowers(ah,
- chan->channel, pRawDataset, pdGainOverlap_t2,
+ freq, pRawDataset, pdGainOverlap_t2,
&minCalPower5413_t2,gainBoundaries, rfXpdGain, pdadcValues);
HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);

@@ -676,9 +679,11 @@ ar5413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
}

static HAL_BOOL
-ar5413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar5413GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
+ uint16_t freq = chan->ic_freq; /* NB: never mapped */
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
const RAW_DATA_PER_CHANNEL_2413 *data=AH_NULL;
@@ -687,12 +692,12 @@ ar5413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,

*maxPow = 0;

- if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+ if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
- else if (IS_CHAN_B(chan))
+ else if (IEEE80211_IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
- HALASSERT(IS_CHAN_5GHZ(chan));
+ HALASSERT(IEEE80211_IS_CHAN_5GHZ(chan));
pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
}

@@ -705,9 +710,9 @@ ar5413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
if (numChannels < 1)
return(AH_FALSE);

- if ((chan->channel < data[0].channelValue) ||
- (chan->channel > data[numChannels-1].channelValue)) {
- if (chan->channel < data[0].channelValue) {
+ if ((freq < data[0].channelValue) ||
+ (freq > data[numChannels-1].channelValue)) {
+ if (freq < data[0].channelValue) {
*maxPow = ar5413GetMaxPower(ah, &data[0]);
*minPow = ar5413GetMinPower(ah, &data[0]);
return(AH_TRUE);
@@ -719,19 +724,19 @@ ar5413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
}

/* Linearly interpolate the power value now */
- for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+ for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
last = i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = ar5413GetMaxPower(ah, &data[i]) - ar5413GetMaxPower(ah, &data[last]);
- *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) +
+ *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
ar5413GetMaxPower(ah, &data[last])*totalD)/totalD);
totalMin = ar5413GetMinPower(ah, &data[i]) - ar5413GetMinPower(ah, &data[last]);
- *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+ *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
ar5413GetMinPower(ah, &data[last])*totalD)/totalD);
return(AH_TRUE);
} else {
- if (chan->channel == data[i].channelValue) {
+ if (freq == data[i].channelValue) {
*maxPow = ar5413GetMaxPower(ah, &data[i]);
*minPow = ar5413GetMinPower(ah, &data[i]);
return(AH_TRUE);
diff --git a/sys/external/isc/atheros_hal/dist/ar5312/ar5312.h b/sys/external/isc/atheros_hal/dist/ar5312/ar5312.h
index c812211..df3cb33 100644
--- a/sys/external/isc/atheros_hal/dist/ar5312/ar5312.h
+++ b/sys/external/isc/atheros_hal/dist/ar5312/ar5312.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -41,14 +41,16 @@
extern HAL_BOOL ar5312IsInterruptPending(struct ath_hal *ah);

/* AR5312 */
-extern HAL_BOOL ar5312GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern HAL_BOOL ar5312GpioCfgOutput(struct ath_hal *, uint32_t gpio,
+ HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5312GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5312GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5312GpioGet(struct ath_hal *ah, uint32_t gpio);
extern void ar5312GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);

/* AR2315+ */
-extern HAL_BOOL ar5315GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern HAL_BOOL ar5315GpioCfgOutput(struct ath_hal *, uint32_t gpio,
+ HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5315GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5315GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5315GpioGet(struct ath_hal *ah, uint32_t gpio);
@@ -60,8 +62,10 @@ extern void ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
extern void ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
extern void ar5312DumpState(struct ath_hal *ah);
extern HAL_BOOL ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
-extern HAL_BOOL ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan);
+ struct ieee80211_channel *chan,
+ HAL_BOOL bChannelChange, HAL_STATUS *status);
+extern HAL_BOOL ar5312ChipReset(struct ath_hal *ah,
+ struct ieee80211_channel *chan);
extern HAL_BOOL ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
int setChip);
extern HAL_BOOL ar5312PhyDisable(struct ath_hal *ah);
diff --git a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_attach.c b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_attach.c
index ca93896..dc0cbdb 100644
--- a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_attach.c
+++ b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_attach.c
@@ -122,7 +122,7 @@ ar5312Attach(uint16_t devid, HAL_SOFTC sc,

/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
- HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 6);
+ HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);

if (!ar5312ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
@@ -321,6 +321,7 @@ ar5312Probe(uint16_t vendorid, uint16_t devid)
case AR5212_AR2315_REV7:
return "Atheros 2315 WiSoC";
case AR5212_AR2317_REV1:
+ case AR5212_AR2317_REV2:
return "Atheros 2317 WiSoC";
case AR5212_AR2413:
return "Atheros 2413";
diff --git a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_gpio.c b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_gpio.c
index 9b4b743..20a575d 100644
--- a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_gpio.c
+++ b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_gpio.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5312_gpio.c,v 1.1.1.1 2008/12/11 04:46:45 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -35,7 +35,7 @@
* Configure GPIO Output lines
*/
HAL_BOOL
-ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

diff --git a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_misc.c b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_misc.c
index 6e7466b..3d85ece 100644
--- a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_misc.c
+++ b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_misc.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5312_misc.c,v 1.1.1.1 2008/12/11 04:46:45 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

diff --git a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_reset.c b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_reset.c
index f13cdd7..212bb9e 100644
--- a/sys/external/isc/atheros_hal/dist/ar5312/ar5312_reset.c
+++ b/sys/external/isc/atheros_hal/dist/ar5312/ar5312_reset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -34,15 +34,21 @@
#define BASE_ACTIVATE_DELAY 100 /* 100 usec */
#define PLL_SETTLE_DELAY 300 /* 300 usec */

-extern int16_t ar5212GetNf(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
-extern void ar5212SetRateDurationTable(struct ath_hal *, HAL_CHANNEL *);
+extern int16_t ar5212GetNf(struct ath_hal *, const struct ieee80211_channel *);
+extern void ar5212SetRateDurationTable(struct ath_hal *,
+ const struct ieee80211_channel *);
extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain);
-extern void ar5212SetDeltaSlope(struct ath_hal *, HAL_CHANNEL *);
-extern HAL_BOOL ar5212SetBoardValues(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
-extern void ar5212SetIFSTiming(struct ath_hal *, HAL_CHANNEL *);
-extern HAL_BOOL ar5212IsSpurChannel(struct ath_hal *, HAL_CHANNEL *);
-extern HAL_BOOL ar5212ChannelChange(struct ath_hal *, HAL_CHANNEL *);
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain);
+extern void ar5212SetDeltaSlope(struct ath_hal *,
+ const struct ieee80211_channel *);
+extern HAL_BOOL ar5212SetBoardValues(struct ath_hal *,
+ const struct ieee80211_channel *);
+extern void ar5212SetIFSTiming(struct ath_hal *,
+ const struct ieee80211_channel *);
+extern HAL_BOOL ar5212IsSpurChannel(struct ath_hal *,
+ const struct ieee80211_channel *);
+extern HAL_BOOL ar5212ChannelChange(struct ath_hal *,
+ const struct ieee80211_channel *);

static HAL_BOOL ar5312SetResetReg(struct ath_hal *, uint32_t resetMask);

@@ -81,7 +87,8 @@ write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
*/
HAL_BOOL
ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+ struct ieee80211_channel *chan,
+ HAL_BOOL bChannelChange, HAL_STATUS *status)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
@@ -102,20 +109,6 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
ee = AH_PRIVATE(ah)->ah_eeprom;

OS_MARK(ah, AH_MARK_RESET, bChannelChange);
-#define IS(_c,_f) (((_c)->channelFlags & _f) || 0)
- if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
- if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
-#undef IS
/*
* Map public channel to private.
*/
@@ -123,7 +116,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
FAIL(HAL_EINVAL);
}
switch (opmode) {
@@ -176,10 +169,10 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* -the modes of the previous and requested channel are the same - some ugly code for XR
*/
if (bChannelChange &&
- (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
- (chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
- ((chan->channelFlags & CHANNEL_ALL) ==
- (AH_PRIVATE(ah)->ah_curchan->channelFlags & CHANNEL_ALL))) {
+ AH_PRIVATE(ah)->ah_curchan != AH_NULL &&
+ (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&
+ ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) ==
+ (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {
if (ar5212ChannelChange(ah, chan))
/* If ChannelChange completed - skip the rest of reset */
return AH_TRUE;
@@ -217,31 +210,13 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
}

/* Setup the indices for the next set of register array writes */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- modesIndex = 1;
- freqIndex = 1;
- break;
- case CHANNEL_T:
- modesIndex = 2;
- freqIndex = 1;
- break;
- case CHANNEL_B:
- modesIndex = 3;
- freqIndex = 2;
- break;
- case CHANNEL_PUREG:
- modesIndex = 4;
- freqIndex = 2;
- break;
- case CHANNEL_108G:
- modesIndex = 5;
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
freqIndex = 2;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- FAIL(HAL_EINVAL);
+ modesIndex = IEEE80211_IS_CHAN_108G(chan) ? 5 :
+ IEEE80211_IS_CHAN_G(chan) ? 4 : 3;
+ } else {
+ freqIndex = 1;
+ modesIndex = IEEE80211_IS_CHAN_ST(chan) ? 2 : 1;
}

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
@@ -256,9 +231,8 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

- if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))
ar5212SetIFSTiming(ah, chan);
- }

/* Overwrite INI values for revised chipsets */
if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
@@ -276,7 +250,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta);
}

- if (IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_G(chan)) {
OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
SM((ee->ee_cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
SM((cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX));
@@ -315,18 +289,18 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
SM(0x16, AR_PHY_SIGMA_DELTA_FILT1) |
SM(0, AR_PHY_SIGMA_DELTA_ADC_CLIP));

- if (IS_CHAN_2GHZ(chan))
+ if (IEEE80211_IS_CHAN_2GHZ(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);

/* CCK Short parameter adjustment in 11B mode */
- if (IS_CHAN_B(chan))
+ if (IEEE80211_IS_CHAN_B(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);

/* Set ADC/DAC select values */
OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);

/* Increase 11A AGC Settling */
- if ((chan->channelFlags & CHANNEL_ALL) == CHANNEL_A)
+ if (IEEE80211_IS_CHAN_A(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
} else {
/* Set ADC/DAC select values */
@@ -334,29 +308,29 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
}

/* Setup the transmit power values. */
- if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
+ if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error init'ing transmit power\n", __func__);
FAIL(HAL_EIO);
}

/* Write the analog registers */
- if (!ahp->ah_rfHal->setRfRegs(ah, ichan, modesIndex, rfXpdGain)) {
+ if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
__func__);
FAIL(HAL_EIO);
}

/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
- if (IS_CHAN_OFDM(chan)) {
- if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
- (!IS_CHAN_B(chan)))
- ar5212SetSpurMitigation(ah, ichan);
+ if (IEEE80211_IS_CHAN_OFDM(chan)) {
+ if (IS_5413(ah) ||
+ AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)
+ ar5212SetSpurMitigation(ah, chan);
ar5212SetDeltaSlope(ah, chan);
}

/* Setup board specific options for EEPROM version 3 */
- if (!ar5212SetBoardValues(ah, ichan)) {
+ if (!ar5212SetBoardValues(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error setting board options\n", __func__);
FAIL(HAL_EIO);
@@ -396,7 +370,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

- if (!ar5212SetChannel(ah, ichan))
+ if (!ar5212SetChannel(ah, chan))
FAIL(HAL_EIO);

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
@@ -407,10 +381,9 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,

/* Set Tx frame start to tx data start delay */
if (IS_RAD5112_ANY(ah) &&
- (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan) ||
- IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan))) {
+ (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) {
txFrm2TxDStart =
- (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) ?
+ IEEE80211_IS_CHAN_HALF(chan) ?
TX_FRAME_D_START_HALF_RATE:
TX_FRAME_D_START_QUARTER_RATE;
OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
@@ -445,7 +418,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* Value is in 100ns increments.
*/
synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
- if (IS_CHAN_CCK(chan)) {
+ if (IEEE80211_IS_CHAN_B(chan)) {
synthDelay = (4 * synthDelay) / 22;
} else {
synthDelay /= 10;
@@ -461,9 +434,9 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* extra BASE_ACTIVATE_DELAY usecs to ensure this condition
* does not happen.
*/
- if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
- } else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
} else {
OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
@@ -487,7 +460,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
| AR_PHY_AGC_CONTROL_CAL
| AR_PHY_AGC_CONTROL_NF);

- if (!IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
+ if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
@@ -583,12 +556,8 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

- if (bChannelChange) {
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
- }
+ if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
+ chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

@@ -597,7 +566,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
return AH_TRUE;
bad:
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
- if (*status)
+ if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
@@ -639,10 +608,10 @@ ar5312Disable(struct ath_hal *ah)
* WARNING: The order of the PLL and mode registers must be correct.
*/
HAL_BOOL
-ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
{

- OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
+ OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);

/*
* Reset the HW
@@ -683,50 +652,49 @@ ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
if (IS_RAD5112_ANY(ah)) {
rfMode = AR_PHY_MODE_AR5112;
if (!IS_5315(ah)) {
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
phyPLL = AR_PHY_PLL_CTL_44_5312;
} else {
- if (IS_CHAN_HALF_RATE(chan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
phyPLL = AR_PHY_PLL_CTL_40_5312_HALF;
- } else if (IS_CHAN_QUARTER_RATE(chan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
phyPLL = AR_PHY_PLL_CTL_40_5312_QUARTER;
} else {
phyPLL = AR_PHY_PLL_CTL_40_5312;
}
}
} else {
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+ if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44_5112;
else
phyPLL = AR_PHY_PLL_CTL_40_5112;
- if (IS_CHAN_HALF_RATE(chan))
+ if (IEEE80211_IS_CHAN_HALF(chan))
phyPLL |= AR_PHY_PLL_CTL_HALF;
- else if (IS_CHAN_QUARTER_RATE(chan))
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
phyPLL |= AR_PHY_PLL_CTL_QUARTER;
}
} else {
rfMode = AR_PHY_MODE_AR5111;
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+ if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44;
else
phyPLL = AR_PHY_PLL_CTL_40;
- if (IS_CHAN_HALF_RATE(chan))
+ if (IEEE80211_IS_CHAN_HALF(chan))
phyPLL = AR_PHY_PLL_CTL_HALF;
- else if (IS_CHAN_QUARTER_RATE(chan))
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
phyPLL = AR_PHY_PLL_CTL_QUARTER;
}
- if (IS_CHAN_OFDM(chan) && (IS_CHAN_CCK(chan) ||
- IS_CHAN_G(chan)))
+ if (IEEE80211_IS_CHAN_G(chan))
rfMode |= AR_PHY_MODE_DYNAMIC;
- else if (IS_CHAN_OFDM(chan))
+ else if (IEEE80211_IS_CHAN_OFDM(chan))
rfMode |= AR_PHY_MODE_OFDM;
else
rfMode |= AR_PHY_MODE_CCK;
- if (IS_CHAN_5GHZ(chan))
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
rfMode |= AR_PHY_MODE_RF5GHZ;
else
rfMode |= AR_PHY_MODE_RF2GHZ;
- turbo = IS_CHAN_TURBO(chan) ?
+ turbo = IEEE80211_IS_CHAN_TURBO(chan) ?
(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;
curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
/*
@@ -736,7 +704,7 @@ ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
* mode bit is set
* - Turbo cannot be set at the same time as CCK or DYNAMIC
*/
- if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
if (curPhyPLL != phyPLL) {
diff --git a/sys/external/isc/atheros_hal/dist/ar5312/ar5315_gpio.c b/sys/external/isc/atheros_hal/dist/ar5312/ar5315_gpio.c
index 4c14e1e..72baec6 100644
--- a/sys/external/isc/atheros_hal/dist/ar5312/ar5315_gpio.c
+++ b/sys/external/isc/atheros_hal/dist/ar5312/ar5315_gpio.c
@@ -35,7 +35,7 @@
* Configure GPIO Output lines
*/
HAL_BOOL
-ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar2133.c b/sys/external/isc/atheros_hal/dist/ar5416/ar2133.c
index 5548e8a..25c044c 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar2133.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar2133.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -46,14 +46,8 @@ struct ar2133State {

#define ar5416ModifyRfBuffer ar5212ModifyRfBuffer /*XXX*/

-extern void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
- uint32_t numBits, uint32_t firstBit, uint32_t column);
-HAL_BOOL ar2133GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL
- *chans, uint32_t nchans);
-
-static HAL_BOOL ar2133GetChannelMaxMinPower(struct ath_hal *, HAL_CHANNEL *,
- int16_t *maxPow,int16_t *minPow);
-int16_t ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
+void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+ uint32_t numBits, uint32_t firstBit, uint32_t column);

static void
ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
@@ -69,7 +63,7 @@ ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
-ar2133SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar2133SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
@@ -78,9 +72,9 @@ ar2133SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
uint16_t freq;
CHAN_CENTERS centers;

- OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+ OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);

- ar5416GetChannelCenters(ah, chan, &centers);
+ ar5416GetChannelCenters(ah, chan, &centers);
freq = centers.synth_center;

if (freq < 4800) {
@@ -169,7 +163,7 @@ ar2133GetRfBank(struct ath_hal *ah, int bank)
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
-ar2133SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+ar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
uint16_t modesIndex, uint16_t *rfXpdGain)
{
struct ar2133State *priv = AR2133(ah);
@@ -193,7 +187,7 @@ ar2133SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);

/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ar5416ModifyRfBuffer(priv->Bank6Data,
ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);
ar5416ModifyRfBuffer(priv->Bank6Data,
@@ -233,7 +227,7 @@ ar2133SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,

static HAL_BOOL
ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
- HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain)
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
{
return AH_TRUE;
}
@@ -267,8 +261,9 @@ ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
#endif

static HAL_BOOL
-ar2133GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan, int16_t *maxPow,
- int16_t *minPow)
+ar2133GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ int16_t *maxPow, int16_t *minPow)
{
#if 0
struct ath_hal_5212 *ahp = AH5212(ah);
@@ -390,7 +385,7 @@ ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
* Adjust NF based on statistical values for 5GHz frequencies.
* Stubbed:Not used by Fowl
*/
-int16_t
+static int16_t
ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
{
return 0;
@@ -420,6 +415,8 @@ ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)
struct ar2133State *priv;
uint32_t *bankData;

+ HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR2133 radio\n", __func__);
+
HALASSERT(ahp->ah_rfHal == AH_NULL);
priv = ath_hal_malloc(sizeof(struct ar2133State)
+ AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t)
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416.h b/sys/external/isc/atheros_hal/dist/ar5416/ar5416.h
index 6ae4560..9a8cc27 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416.h
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -21,6 +21,7 @@

#include "ar5212/ar5212.h"
#include "ar5416_cal.h"
+#include "ah_eeprom_v14.h" /* for CAL_TARGET_POWER_* */

#define AR5416_MAGIC 0x20065416

@@ -44,6 +45,9 @@ typedef struct {
#define AR5416_CCA_MAX_GOOD_VALUE -85
#define AR5416_CCA_MAX_HIGH_VALUE -62
#define AR5416_CCA_MIN_BAD_VALUE -140
+#define AR9285_CCA_MAX_GOOD_VALUE -118
+
+#define AR5416_SPUR_RSSI_THRESH 40

struct ath_hal_5416 {
struct ath_hal_5212 ah_5212;
@@ -57,8 +61,15 @@ struct ath_hal_5416 {
HAL_INI_ARRAY ah_ini_bank6;
HAL_INI_ARRAY ah_ini_bank7;
HAL_INI_ARRAY ah_ini_addac;
+ HAL_INI_ARRAY ah_ini_pcieserdes;
+
+ void (*ah_writeIni)(struct ath_hal *,
+ const struct ieee80211_channel *);
+ void (*ah_spurMitigate)(struct ath_hal *,
+ const struct ieee80211_channel *);

u_int ah_globaltxtimeout; /* global tx timeout */
+ u_int ah_gpioMask;
int ah_hangs; /* h/w hangs state */
uint8_t ah_keytype[AR5416_KEYTABLE_SIZE];
/*
@@ -83,16 +94,17 @@ extern HAL_BOOL ar2133RfAttach(struct ath_hal *, HAL_STATUS *);

struct ath_hal;

-extern struct ath_hal * ar5416Attach(uint16_t devid, HAL_SOFTC sc,
- HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
+extern uint32_t ar5416GetRadioRev(struct ath_hal *ah);
extern void ar5416InitState(struct ath_hal_5416 *, uint16_t devid,
HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
HAL_STATUS *status);
extern void ar5416Detach(struct ath_hal *ah);
+extern void ar5416AttachPCIE(struct ath_hal *ah);
extern HAL_BOOL ar5416FillCapabilityInfo(struct ath_hal *ah);

#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
- (IS_CHAN_5GHZ(_c) && ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G))
+ (IEEE80211_IS_CHAN_5GHZ(_c) && \
+ ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G))

extern void ar5416AniAttach(struct ath_hal *, const struct ar5212AniParams *,
const struct ar5212AniParams *, HAL_BOOL ena);
@@ -102,8 +114,8 @@ extern HAL_BOOL ar5416AniSetParams(struct ath_hal *,
const struct ar5212AniParams *, const struct ar5212AniParams *);
extern void ar5416ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
extern void ar5416AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
- HAL_CHANNEL *);
-extern void ar5416AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
+ const struct ieee80211_channel *);
+extern void ar5416AniReset(struct ath_hal *, const struct ieee80211_channel *,
HAL_OPMODE, int);

extern void ar5416SetBeaconTimers(struct ath_hal *, const HAL_BEACON_TIMERS *);
@@ -120,7 +132,8 @@ extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah);
extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *, HAL_INT *masked);
extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints);

-extern HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio,
+ HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5416GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5416GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio);
@@ -160,17 +173,34 @@ extern HAL_STATUS ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
struct ath_rx_status *);

extern HAL_BOOL ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
+ struct ieee80211_channel *chan,
+ HAL_BOOL bChannelChange, HAL_STATUS *status);
extern HAL_BOOL ar5416PhyDisable(struct ath_hal *ah);
extern HAL_RFGAIN ar5416GetRfgain(struct ath_hal *ah);
extern HAL_BOOL ar5416Disable(struct ath_hal *ah);
-extern HAL_BOOL ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *);
+extern HAL_BOOL ar5416ChipReset(struct ath_hal *ah,
+ const struct ieee80211_channel *);
+extern HAL_BOOL ar5416SetBoardValues(struct ath_hal *,
+ const struct ieee80211_channel *);
extern HAL_BOOL ar5416SetResetReg(struct ath_hal *, uint32_t type);
extern HAL_BOOL ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
+extern HAL_BOOL ar5416SetTransmitPower(struct ath_hal *,
+ const struct ieee80211_channel *, uint16_t *);
extern HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah,
- HAL_CHANNEL *chans, uint32_t nchans);
+ struct ieee80211_channel *chan);
extern void ar5416GetChannelCenters(struct ath_hal *,
- HAL_CHANNEL_INTERNAL *chan, CHAN_CENTERS *centers);
+ const struct ieee80211_channel *chan, CHAN_CENTERS *centers);
+extern void ar5416GetTargetPowers(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ CAL_TARGET_POWER_HT *powInfo,
+ uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
+ uint16_t numRates, HAL_BOOL isHt40Target);
+extern void ar5416GetTargetPowersLeg(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ CAL_TARGET_POWER_LEG *powInfo,
+ uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
+ uint16_t numRates, HAL_BOOL isExtTarget);
+

extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q);
extern HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416.ini b/sys/external/isc/atheros_hal/dist/ar5416/ar5416.ini
index 5e7a10e..dce764f 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416.ini
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416.ini
@@ -686,3 +686,17 @@ static const uint32_t ar5416Addac[][2] = {
{0x0989c, 0x00000000 },
{0x098c4, 0x00000000 },
};
+
+/* hand-crafted from code that does explicit register writes */
+static const uint32_t ar5416PciePhy[][2] = {
+ { AR_PCIE_SERDES, 0x9248fc00 },
+ { AR_PCIE_SERDES, 0x24924924 },
+ { AR_PCIE_SERDES, 0x28000039 },
+ { AR_PCIE_SERDES, 0x53160824 },
+ { AR_PCIE_SERDES, 0xe5980579 },
+ { AR_PCIE_SERDES, 0x001defff },
+ { AR_PCIE_SERDES, 0x1aaabe40 },
+ { AR_PCIE_SERDES, 0xbe105554 },
+ { AR_PCIE_SERDES, 0x000e3007 },
+ { AR_PCIE_SERDES2, 0x00000000 },
+};
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_ani.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_ani.c
index a1f0f3a..0311816 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_ani.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_ani.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -102,43 +102,6 @@ disableAniMIBCounters(struct ath_hal *ah)
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, 0);
}

-/*
- * This routine returns the index into the aniState array that
- * corresponds to the channel in *chan. If no match is found and the
- * array is still not fully utilized, a new entry is created for the
- * channel. We assume the attach function has already initialized the
- * ah_ani values and only the channel field needs to be set.
- */
-static int
-ar5416GetAniChannelIndex(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
-{
-#define N(a) (sizeof(a) / sizeof(a[0]))
- struct ath_hal_5212 *ahp = AH5212(ah);
- int i;
-
- for (i = 0; i < N(ahp->ah_ani); i++) {
- struct ar5212AniState *asp = &ahp->ah_ani[i];
- if (asp->c.channel == chan->channel)
- return i;
- if (asp->c.channel == 0) {
- asp->c.channel = chan->channel;
- asp->c.channelFlags = chan->channelFlags;
- asp->c.privFlags = chan->privFlags;
- asp->isSetup = AH_FALSE;
- if (IS_CHAN_2GHZ(chan))
- asp->params = &ahp->ah_aniParams24;
- else
- asp->params = &ahp->ah_aniParams5;
- return i;
- }
- }
- /* XXX statistic */
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "No more channel states left. Using channel 0\n");
- return 0; /* XXX gotta return something valid */
-#undef N
-}
-
static void
setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
{
@@ -220,7 +183,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

if (level >= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: level out of range (%u > %u)\n",
+ "%s: immunity level out of range (%u > %u)\n",
__func__, level, params->maxNoiseImmunityLevel);
return AH_FALSE;
}
@@ -304,7 +267,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

if (level >= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: level out of range (%u > %u)\n",
+ "%s: firstep level out of range (%u > %u)\n",
__func__, level, params->maxFirstepLevel);
return AH_FALSE;
}
@@ -322,7 +285,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)

if (level >= params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: level out of range (%u > %u)\n",
+ "%s: spur immunity level out of range (%u > %u)\n",
__func__, level, params->maxSpurImmunityLevel);
return AH_FALSE;
}
@@ -374,7 +337,7 @@ static void
ar5416AniOfdmErrTrigger(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
struct ar5212AniState *aniState;
const struct ar5212AniParams *params;

@@ -441,8 +404,7 @@ ar5416AniOfdmErrTrigger(struct ath_hal *ah)
* weak signal detection and zero firstepLevel to
* maximize CCK sensitivity
*/
- /* XXX can optimize */
- if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
if (!aniState->ofdmWeakSigDetectOff)
ar5416AniControl(ah,
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
@@ -460,7 +422,7 @@ static void
ar5416AniCckErrTrigger(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+ const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
struct ar5212AniState *aniState;
const struct ar5212AniParams *params;

@@ -493,8 +455,7 @@ ar5416AniCckErrTrigger(struct ath_hal *ah)
* Beacon rssi is low, zero firstep level to maximize
* CCK sensitivity in 11b/g mode.
*/
- /* XXX can optimize */
- if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
if (aniState->firstepLevel > 0)
ar5416AniControl(ah,
HAL_ANI_FIRSTEP_LEVEL, 0);
@@ -536,26 +497,33 @@ ar5416AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
* it is setup to reflect the current channel.
*/
void
-ar5416AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+ar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
HAL_OPMODE opmode, int restore)
{
struct ath_hal_5212 *ahp = AH5212(ah);
- struct ar5212AniState *aniState;
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
+ /* XXX bounds check ic_devdata */
+ struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];
uint32_t rxfilter;
- int index;

- index = ar5416GetAniChannelIndex(ah, chan);
- aniState = &ahp->ah_ani[index];
+ if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {
+ OS_MEMZERO(aniState, sizeof(*aniState));
+ if (IEEE80211_IS_CHAN_2GHZ(chan))
+ aniState->params = &ahp->ah_aniParams24;
+ else
+ aniState->params = &ahp->ah_aniParams5;
+ ichan->privFlags |= CHANNEL_ANI_INIT;
+ HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);
+ }
ahp->ah_curani = aniState;
#if 0
- ath_hal_printf(ah,"%s: chan %u/0x%x restore %d setup %d opmode %u\n",
- __func__, chan->channel, chan->channelFlags, restore,
- aniState->isSetup, opmode);
+ ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
+ __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
+ ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
#else
- HALDEBUG(ah, HAL_DEBUG_ANI,
- "%s: chan %u/0x%x restore %d setup %d opmode %u\n",
- __func__, chan->channel, chan->channelFlags, restore,
- aniState->isSetup, opmode);
+ HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
+ __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
+ ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
#endif
OS_MARK(ah, AH_MARK_ANI_RESET, opmode);

@@ -577,7 +545,7 @@ ar5416AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* XXX if ANI follows hardware, we don't care what mode we're
* XXX in, we should keep the ani parameters
*/
- if (restore && aniState->isSetup) {
+ if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {
ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel);
ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
@@ -595,7 +563,7 @@ ar5416AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
AH_TRUE);
ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
- aniState->isSetup = AH_TRUE;
+ ichan->privFlags |= CHANNEL_ANI_SETUP;
}
ar5416AniRestart(ah, aniState);

@@ -831,7 +799,7 @@ updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
*/
void
ar5416AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
- HAL_CHANNEL *chan)
+ const struct ieee80211_channel *chan)
{
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState = ahp->ah_curani;
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_attach.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_attach.c
index 25c6d25..7c894d3 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_attach.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_attach.c
@@ -22,12 +22,20 @@
#include "ah_internal.h"
#include "ah_devid.h"

+#include "ah_eeprom_v14.h"
+
#include "ar5416/ar5416.h"
#include "ar5416/ar5416reg.h"
#include "ar5416/ar5416phy.h"

#include "ar5416/ar5416.ini"

+static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
+static void ar5416WriteIni(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
+static void ar5416SpurMitigate(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
+
static void
ar5416AniSetup(struct ath_hal *ah)
{
@@ -76,10 +84,13 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
ah->ah_reset = ar5416Reset;
ah->ah_phyDisable = ar5416PhyDisable;
ah->ah_disable = ar5416Disable;
+ ah->ah_configPCIE = ar5416ConfigPCIE;
ah->ah_perCalibration = ar5416PerCalibration;
ah->ah_perCalibrationN = ar5416PerCalibrationN,
ah->ah_resetCalValid = ar5416ResetCalValid,
ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
+ ah->ah_setTxPower = ar5416SetTransmitPower;
+ ah->ah_setBoardValues = ar5416SetBoardValues;

/* Transmit functions */
ah->ah_stopTxDma = ar5416StopTxDma;
@@ -147,13 +158,10 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
#ifdef AH_SUPPORT_WRITE_EEPROM
ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
#endif
- ahp->ah_priv.ah_gpioCfgOutput = ar5416GpioCfgOutput;
- ahp->ah_priv.ah_gpioCfgInput = ar5416GpioCfgInput;
- ahp->ah_priv.ah_gpioGet = ar5416GpioGet;
- ahp->ah_priv.ah_gpioSet = ar5416GpioSet;
- ahp->ah_priv.ah_gpioSetIntr = ar5416GpioSetIntr;
ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;

+ AH5416(ah)->ah_writeIni = ar5416WriteIni;
+ AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
/*
* Start by setting all Owl devices to 2x2
*/
@@ -161,10 +169,25 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
}

+uint32_t
+ar5416GetRadioRev(struct ath_hal *ah)
+{
+ uint32_t val;
+ int i;
+
+ /* Read Radio Chip Rev Extract */
+ OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
+ for (i = 0; i < 8; i++)
+ OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
+ val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
+ val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
+ return ath_hal_reverseBits(val, 8);
+}
+
/*
* Attach for an AR5416 part.
*/
-struct ath_hal *
+static struct ath_hal *
ar5416Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
{
@@ -209,6 +232,7 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
+ AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);

/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
@@ -234,6 +258,13 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
}

+ HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
+ ar5416AttachPCIE(ah);
+
+ ecode = ath_hal_v14EepromAttach(ah);
+ if (ecode != HAL_OK)
+ goto bad;
+
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
__func__);
@@ -287,10 +318,6 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
#endif
}

- ecode = ath_hal_v14EepromAttach(ah);
- if (ecode != HAL_OK)
- goto bad;
-
/*
* Got everything we need now to setup the capabilities.
*/
@@ -319,8 +346,6 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);

- HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: Attaching AR2133 radio\n",
- __func__);
rfStatus = ar2133RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
@@ -358,6 +383,321 @@ ar5416Detach(struct ath_hal *ah)
ath_hal_free(ah);
}

+void
+ar5416AttachPCIE(struct ath_hal *ah)
+{
+ if (AH_PRIVATE(ah)->ah_ispcie)
+ ath_hal_configPCIE(ah, AH_FALSE);
+ else
+ ath_hal_disablePCIE(ah);
+}
+
+static void
+ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
+{
+ if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
+ ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
+ OS_DELAY(1000);
+ OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+ OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
+ }
+}
+
+static void
+ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ u_int modesIndex, freqIndex;
+ int regWrites = 0;
+
+ /* Setup the indices for the next set of register array writes */
+ /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
+ freqIndex = 2;
+ if (IEEE80211_IS_CHAN_HT40(chan))
+ modesIndex = 3;
+ else if (IEEE80211_IS_CHAN_108G(chan))
+ modesIndex = 5;
+ else
+ modesIndex = 4;
+ } else {
+ freqIndex = 1;
+ if (IEEE80211_IS_CHAN_HT40(chan) ||
+ IEEE80211_IS_CHAN_TURBO(chan))
+ modesIndex = 2;
+ else
+ modesIndex = 1;
+ }
+
+ /* Set correct Baseband to analog shift setting to access analog chips. */
+ OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+ /*
+ * Write addac shifts
+ */
+ OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
+#if 0
+ /* NB: only required for Sowl */
+ ar5416EepromSetAddac(ah, chan);
+#endif
+ regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
+ regWrites);
+ OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
+
+ regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
+ modesIndex, regWrites);
+ regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
+ 1, regWrites);
+
+ /* XXX updated regWrites? */
+ AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
+}
+
+/*
+ * Convert to baseband spur frequency given input channel frequency
+ * and compute register settings below.
+ */
+
+static void
+ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
+ static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
+ AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
+ static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
+ AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
+ static const int inc[4] = { 0, 100, 0, 0 };
+
+ int bb_spur = AR_NO_SPUR;
+ int bin, cur_bin;
+ int spur_freq_sd;
+ int spur_delta_phase;
+ int denominator;
+ int upper, lower, cur_vit_mask;
+ int tmp, new;
+ int i;
+
+ int8_t mask_m[123];
+ int8_t mask_p[123];
+ int8_t mask_amt;
+ int tmp_mask;
+ int cur_bb_spur;
+ HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
+
+ OS_MEMZERO(mask_m, sizeof(mask_m));
+ OS_MEMZERO(mask_p, sizeof(mask_p));
+
+ /*
+ * Need to verify range +/- 9.5 for static ht20, otherwise spur
+ * is out-of-band and can be ignored.
+ */
+ /* XXX ath9k changes */
+ for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+ cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
+ if (AR_NO_SPUR == cur_bb_spur)
+ break;
+ cur_bb_spur = cur_bb_spur - (freq * 10);
+ if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
+ bb_spur = cur_bb_spur;
+ break;
+ }
+ }
+ if (AR_NO_SPUR == bb_spur)
+ return;
+
+ bin = bb_spur * 32;
+
+ tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
+ new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+ AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+ AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+ AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+
+ OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
+
+ new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+ AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+ AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+ AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+ SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
+ OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
+ /*
+ * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
+ * config, no offset for HT20.
+ * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
+ * /80 for dyn2040.
+ */
+ spur_delta_phase = ((bb_spur * 524288) / 100) &
+ AR_PHY_TIMING11_SPUR_DELTA_PHASE;
+ /*
+ * in 11A mode the denominator of spur_freq_sd should be 40 and
+ * it should be 44 in 11G
+ */
+ denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
+ spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
+
+ new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+ SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
+ SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
+ OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
+
+
+ /*
+ * ============================================
+ * pilot mask 1 [31:0] = +6..-26, no 0 bin
+ * pilot mask 2 [19:0] = +26..+7
+ *
+ * channel mask 1 [31:0] = +6..-26, no 0 bin
+ * channel mask 2 [19:0] = +26..+7
+ */
+ //cur_bin = -26;
+ cur_bin = -6000;
+ upper = bin + 100;
+ lower = bin - 100;
+
+ for (i = 0; i < 4; i++) {
+ int pilot_mask = 0;
+ int chan_mask = 0;
+ int bp = 0;
+ for (bp = 0; bp < 30; bp++) {
+ if ((cur_bin > lower) && (cur_bin < upper)) {
+ pilot_mask = pilot_mask | 0x1 << bp;
+ chan_mask = chan_mask | 0x1 << bp;
+ }
+ cur_bin += 100;
+ }
+ cur_bin += inc[i];
+ OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
+ OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
+ }
+
+ /* =================================================
+ * viterbi mask 1 based on channel magnitude
+ * four levels 0-3
+ * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
+ * [1 2 2 1] for -9.6 or [1 2 1] for +16
+ * - enable_mask_ppm, all bins move with freq
+ *
+ * - mask_select, 8 bits for rates (reg 67,0x990c)
+ * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
+ * choose which mask to use mask or mask2
+ */
+
+ /*
+ * viterbi mask 2 2nd set for per data rate puncturing
+ * four levels 0-3
+ * - mask_select, 8 bits for rates (reg 67)
+ * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
+ * [1 2 2 1] for -9.6 or [1 2 1] for +16
+ */
+ cur_vit_mask = 6100;
+ upper = bin + 120;
+ lower = bin - 120;
+
+ for (i = 0; i < 123; i++) {
+ if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
+ if ((abs(cur_vit_mask - bin)) < 75) {
+ mask_amt = 1;
+ } else {
+ mask_amt = 0;
+ }
+ if (cur_vit_mask < 0) {
+ mask_m[abs(cur_vit_mask / 100)] = mask_amt;
+ } else {
+ mask_p[cur_vit_mask / 100] = mask_amt;
+ }
+ }
+ cur_vit_mask -= 100;
+ }
+
+ tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
+ | (mask_m[48] << 26) | (mask_m[49] << 24)
+ | (mask_m[50] << 22) | (mask_m[51] << 20)
+ | (mask_m[52] << 18) | (mask_m[53] << 16)
+ | (mask_m[54] << 14) | (mask_m[55] << 12)
+ | (mask_m[56] << 10) | (mask_m[57] << 8)
+ | (mask_m[58] << 6) | (mask_m[59] << 4)
+ | (mask_m[60] << 2) | (mask_m[61] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
+
+ tmp_mask = (mask_m[31] << 28)
+ | (mask_m[32] << 26) | (mask_m[33] << 24)
+ | (mask_m[34] << 22) | (mask_m[35] << 20)
+ | (mask_m[36] << 18) | (mask_m[37] << 16)
+ | (mask_m[48] << 14) | (mask_m[39] << 12)
+ | (mask_m[40] << 10) | (mask_m[41] << 8)
+ | (mask_m[42] << 6) | (mask_m[43] << 4)
+ | (mask_m[44] << 2) | (mask_m[45] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
+
+ tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
+ | (mask_m[18] << 26) | (mask_m[18] << 24)
+ | (mask_m[20] << 22) | (mask_m[20] << 20)
+ | (mask_m[22] << 18) | (mask_m[22] << 16)
+ | (mask_m[24] << 14) | (mask_m[24] << 12)
+ | (mask_m[25] << 10) | (mask_m[26] << 8)
+ | (mask_m[27] << 6) | (mask_m[28] << 4)
+ | (mask_m[29] << 2) | (mask_m[30] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
+
+ tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
+ | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
+ | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
+ | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
+ | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
+ | (mask_m[10] << 10) | (mask_m[11] << 8)
+ | (mask_m[12] << 6) | (mask_m[13] << 4)
+ | (mask_m[14] << 2) | (mask_m[15] << 0);
+ OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
+
+ tmp_mask = (mask_p[15] << 28)
+ | (mask_p[14] << 26) | (mask_p[13] << 24)
+ | (mask_p[12] << 22) | (mask_p[11] << 20)
+ | (mask_p[10] << 18) | (mask_p[ 9] << 16)
+ | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
+ | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
+ | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
+ | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
+
+ tmp_mask = (mask_p[30] << 28)
+ | (mask_p[29] << 26) | (mask_p[28] << 24)
+ | (mask_p[27] << 22) | (mask_p[26] << 20)
+ | (mask_p[25] << 18) | (mask_p[24] << 16)
+ | (mask_p[23] << 14) | (mask_p[22] << 12)
+ | (mask_p[21] << 10) | (mask_p[20] << 8)
+ | (mask_p[19] << 6) | (mask_p[18] << 4)
+ | (mask_p[17] << 2) | (mask_p[16] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
+
+ tmp_mask = (mask_p[45] << 28)
+ | (mask_p[44] << 26) | (mask_p[43] << 24)
+ | (mask_p[42] << 22) | (mask_p[41] << 20)
+ | (mask_p[40] << 18) | (mask_p[39] << 16)
+ | (mask_p[38] << 14) | (mask_p[37] << 12)
+ | (mask_p[36] << 10) | (mask_p[35] << 8)
+ | (mask_p[34] << 6) | (mask_p[33] << 4)
+ | (mask_p[32] << 2) | (mask_p[31] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
+
+ tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
+ | (mask_p[59] << 26) | (mask_p[58] << 24)
+ | (mask_p[57] << 22) | (mask_p[56] << 20)
+ | (mask_p[55] << 18) | (mask_p[54] << 16)
+ | (mask_p[53] << 14) | (mask_p[52] << 12)
+ | (mask_p[51] << 10) | (mask_p[50] << 8)
+ | (mask_p[49] << 6) | (mask_p[48] << 4)
+ | (mask_p[47] << 2) | (mask_p[46] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
+}
+
/*
* Fill all software cached or static hardware state information.
* Return failure if capabilities are to come from EEPROM and
@@ -443,6 +783,17 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)

pCap->halTstampPrecision = 32;
pCap->halHwPhyCounterSupport = AH_TRUE;
+ pCap->halIntrMask = HAL_INT_COMMON
+ | HAL_INT_RX
+ | HAL_INT_TX
+ | HAL_INT_FATAL
+ | HAL_INT_BNR
+ | HAL_INT_BMISC
+ | HAL_INT_DTIMSYNC
+ | HAL_INT_TSFOOR
+ | HAL_INT_CST
+ | HAL_INT_GTT
+ ;

pCap->halFastCCSupport = AH_TRUE;
pCap->halNumGpioPins = 6;
@@ -462,6 +813,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
pCap->halMbssidAggrSupport = AH_TRUE;
pCap->halForcePpmSupport = AH_TRUE;
pCap->halEnhancedPmSupport = AH_TRUE;
+ pCap->halBssidMatchSupport = AH_TRUE;

if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.c
index 4814dfe..712f7e0 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5416_cal.c,v 1.1.1.1 2008/12/11 04:46:47 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

@@ -32,26 +32,27 @@
#define NUM_NOISEFLOOR_READINGS 6 /* 3 chains * (ctl + ext) */

static void ar5416StartNFCal(struct ath_hal *ah);
-static void ar5416LoadNF(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *);
-static int16_t ar5416GetNf(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+static void ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *);
+static int16_t ar5416GetNf(struct ath_hal *, struct ieee80211_channel *);

/*
* Determine if calibration is supported by device and channel flags
*/
static OS_INLINE HAL_BOOL
-ar5416IsCalSupp(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_CAL_TYPE calType)
+ar5416IsCalSupp(struct ath_hal *ah, const struct ieee80211_channel *chan,
+ HAL_CAL_TYPE calType)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;

switch (calType & cal->suppCals) {
case IQ_MISMATCH_CAL:
/* Run IQ Mismatch for non-CCK only */
- return !IS_CHAN_B(chan);
+ return !IEEE80211_IS_CHAN_B(chan);
case ADC_GAIN_CAL:
case ADC_DC_CAL:
/* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
- return !IS_CHAN_B(chan) &&
- !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan));
+ return !IEEE80211_IS_CHAN_B(chan) &&
+ !(IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan));
}
return AH_FALSE;
}
@@ -164,7 +165,7 @@ ar5416RunInitCals(struct ath_hal *ah, int init_cal_count)
* Initialize Calibration infrastructure.
*/
HAL_BOOL
-ar5416InitCal(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
HAL_CHANNEL_INTERNAL *ichan;
@@ -279,7 +280,7 @@ ar5416InitCal(struct ath_hal *ah, HAL_CHANNEL *chan)
* Reset the calibration valid bit in channel.
*/
HAL_BOOL
-ar5416ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
@@ -292,7 +293,7 @@ ar5416ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
return AH_FALSE;
}
/*
@@ -312,8 +313,8 @@ ar5416ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)

HALDEBUG(ah, HAL_DEBUG_PERCAL,
"%s: Resetting Cal %d state for channel %u/0x%x\n",
- __func__, currCal->calData->calType, chan->channel,
- chan->channelFlags);
+ __func__, currCal->calData->calType, chan->ic_freq,
+ chan->ic_flags);

/* Disable cal validity in channel */
ichan->calValid &= ~currCal->calData->calType;
@@ -384,14 +385,14 @@ ar5416DoCalibration(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,
* Internal interface to schedule periodic calibration work.
*/
HAL_BOOL
-ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+ar5416PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
u_int rxchainmask, HAL_BOOL longcal, HAL_BOOL *isCalDone)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
HAL_CAL_LIST *currCal = cal->cal_curr;
HAL_CHANNEL_INTERNAL *ichan;

- OS_MARK(ah, AH_MARK_PERCAL, chan->channel);
+ OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);

*isCalDone = AH_TRUE;

@@ -400,7 +401,7 @@ ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ __func__, chan->ic_freq, chan->ic_flags);
return AH_FALSE;
}

@@ -432,7 +433,7 @@ ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
* Get the value from the previous NF cal
* and update the history buffer.
*/
- ar5416GetNf(ah, ichan);
+ ar5416GetNf(ah, chan);

/*
* Load the NF from history buffer of the current channel.
@@ -443,12 +444,6 @@ ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,

/* start NF calibration, without updating BB NF register*/
ar5416StartNFCal(ah);
-
- if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
- /* report up and clear internal state */
- chan->channelFlags |= CHANNEL_CW_INT;
- ichan->channelFlags &= ~CHANNEL_CW_INT;
- }
}
return AH_TRUE;
}
@@ -458,7 +453,8 @@ ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
* changes.
*/
HAL_BOOL
-ar5416PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+ar5416PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
+ HAL_BOOL *isIQdone)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
@@ -478,29 +474,19 @@ ar5416PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)

static HAL_BOOL
ar5416GetEepromNoiseFloorThresh(struct ath_hal *ah,
- const HAL_CHANNEL_INTERNAL *chan, int16_t *nft)
+ const struct ieee80211_channel *chan, int16_t *nft)
{
- switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
- case CHANNEL_A:
- case CHANNEL_A_HT20:
- case CHANNEL_A_HT40PLUS:
- case CHANNEL_A_HT40MINUS:
+ if (IEEE80211_IS_CHAN_5GHZ(chan)) {
ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_5, nft);
- break;
- case CHANNEL_B:
- case CHANNEL_G:
- case CHANNEL_G_HT20:
- case CHANNEL_G_HT40PLUS:
- case CHANNEL_G_HT40MINUS:
+ return AH_TRUE;
+ }
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_2, nft);
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- return AH_FALSE;
+ return AH_TRUE;
}
- return AH_TRUE;
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+ __func__, chan->ic_flags);
+ return AH_FALSE;
}

static void
@@ -512,7 +498,7 @@ ar5416StartNFCal(struct ath_hal *ah)
}

static void
-ar5416LoadNF(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
static const uint32_t ar5416_cca_regs[] = {
AR_PHY_CCA,
@@ -624,7 +610,7 @@ ar5416UpdateNFHistBuff(struct ar5212NfCalHist *h, int16_t *nfarray)
* Read the NF and check it against the noise floor threshhold
*/
static int16_t
-ar5416GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5416GetNf(struct ath_hal *ah, struct ieee80211_channel *chan)
{
int16_t nf, nfThresh;

@@ -635,6 +621,7 @@ ar5416GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
} else {
/* Finished NF cal, check against threshold */
int16_t nfarray[NUM_NOISEFLOOR_READINGS] = { 0 };
+ HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);

/* TODO - enhance for multiple chains and ext ch */
ath_hal_getNoiseFloor(ah, nfarray);
@@ -650,14 +637,14 @@ ar5416GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
* happens it indicates a problem regardless
* of the band.
*/
- chan->channelFlags |= CHANNEL_CW_INT;
+ chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
nf = 0;
}
} else {
nf = 0;
}
ar5416UpdateNFHistBuff(AH5416(ah)->ah_cal.nfCalHist, nfarray);
- chan->rawNoiseFloor = nf;
+ ichan->rawNoiseFloor = nf;
}
return nf;
}
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.h b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.h
index 64da0a0..e67f074 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.h
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -102,12 +102,13 @@ struct ar5416PerCal {
} \
} while (0)

-HAL_BOOL ar5416InitCal(struct ath_hal *ah, HAL_CHANNEL *chan);
-HAL_BOOL ar5416PerCalibration(struct ath_hal *, HAL_CHANNEL *,
+HAL_BOOL ar5416InitCal(struct ath_hal *, const struct ieee80211_channel *);
+HAL_BOOL ar5416PerCalibration(struct ath_hal *, struct ieee80211_channel *,
HAL_BOOL *isIQdone);
-HAL_BOOL ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+HAL_BOOL ar5416PerCalibrationN(struct ath_hal *, struct ieee80211_channel *,
u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
-HAL_BOOL ar5416ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+HAL_BOOL ar5416ResetCalValid(struct ath_hal *,
+ const struct ieee80211_channel *);

void ar5416IQCalCollect(struct ath_hal *ah);
void ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains);
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal_adcgain.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal_adcgain.c
index f3b770f..4af1ca4 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal_adcgain.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal_adcgain.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5416_cal_adcgain.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_eeprom.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_eeprom.c
index eda38a9..2947726 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_eeprom.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_eeprom.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5416_eeprom.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"

diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_gpio.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_gpio.c
index 8710442..fef663d 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_gpio.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_gpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -21,36 +21,95 @@
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
-#ifdef AH_DEBUG
-#include "ah_desc.h" /* NB: for HAL_PHYERR* */
-#endif

#include "ar5416/ar5416.h"
#include "ar5416/ar5416reg.h"
#include "ar5416/ar5416phy.h"

-#define AR_NUM_GPIO 6 /* 6 GPIO pins */
#define AR_GPIO_BIT(_gpio) (1 << _gpio)

/*
+ * Configure GPIO Output Mux control
+ */
+static void
+cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type)
+{
+ int addr;
+ uint32_t gpio_shift, reg;
+
+ /* each MUX controls 6 GPIO pins */
+ if (gpio > 11)
+ addr = AR_GPIO_OUTPUT_MUX3;
+ else if (gpio > 5)
+ addr = AR_GPIO_OUTPUT_MUX2;
+ else
+ addr = AR_GPIO_OUTPUT_MUX1;
+
+ /*
+ * 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux,
+ * bits 5..9 for 2nd pin, etc.
+ */
+ gpio_shift = (gpio % 6) * 5;
+
+ /*
+ * From Owl to Merlin 1.0, the value read from MUX1 bit 4 to bit
+ * 9 are wrong. Here is hardware's coding:
+ * PRDATA[4:0] <= gpio_output_mux[0];
+ * PRDATA[9:4] <= gpio_output_mux[1];
+ * <==== Bit 4 is used by both gpio_output_mux[0] [1].
+ * Currently the max value for gpio_output_mux[] is 6. So bit 4
+ * will never be used. So it should be fine that bit 4 won't be
+ * able to recover.
+ */
+ reg = OS_REG_READ(ah, addr);
+ if (addr == AR_GPIO_OUTPUT_MUX1 && !AR_SREV_MERLIN_20_OR_LATER(ah))
+ reg = ((reg & 0x1F0) << 1) | (reg & ~0x1F0);
+ reg &= ~(0x1f << gpio_shift);
+ reg |= type << gpio_shift;
+ OS_REG_WRITE(ah, addr, reg);
+}
+
+/*
* Configure GPIO Output lines
*/
HAL_BOOL
-ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
- HALASSERT(gpio < AR_NUM_GPIO);
- OS_REG_CLR_BIT(ah, AR_GPIO_INTR_OUT, AR_GPIO_BIT(gpio));
+ uint32_t gpio_shift, reg;
+
+ HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
+
+ /* NB: type maps directly to hardware */
+ cfgOutputMux(ah, gpio, type);
+ gpio_shift = gpio << 1; /* 2 bits per output mode */
+
+ reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
+ reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
+ reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
+ OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
+
return AH_TRUE;
}
-
+
/*
* Configure GPIO Input lines
*/
HAL_BOOL
ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
{
- HALASSERT(gpio < AR_NUM_GPIO);
- OS_REG_SET_BIT(ah, AR_GPIO_INTR_OUT, AR_GPIO_BIT(gpio));
+ uint32_t gpio_shift, reg;
+
+ HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
+
+ /* TODO: configure input mux for AR5416 */
+ /* If configured as input, set output to tristate */
+ gpio_shift = gpio << 1;
+
+ reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
+ reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
+ reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
+ OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
+
return AH_TRUE;
}

@@ -62,14 +121,14 @@ ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
{
uint32_t reg;

- HALASSERT(gpio < AR_NUM_GPIO);
- reg = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_OUT_VAL);
+ HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
+
+ reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);
if (val & 1)
reg |= AR_GPIO_BIT(gpio);
else
reg &= ~AR_GPIO_BIT(gpio);
-
- OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_OUT_VAL, reg);
+ OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg);
return AH_TRUE;
}

@@ -79,34 +138,94 @@ ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
uint32_t
ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
{
- if (gpio >= AR_NUM_GPIO)
+ uint32_t bits;
+
+ if (gpio >= AH_PRIVATE(ah)->ah_caps.halNumGpioPins)
return 0xffffffff;
- return ((OS_REG_READ(ah, AR_GPIO_IN) & AR_GPIO_BIT(gpio)) >> gpio);
+ /*
+ * Read output value for all gpio's, shift it,
+ * and verify whether the specific bit is set.
+ */
+ if (AR_SREV_KITE_10_OR_LATER(ah))
+ bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
+ else if (AR_SREV_MERLIN_10_OR_LATER(ah))
+ bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
+ else
+ bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
+ return ((bits & AR_GPIO_BIT(gpio)) != 0);
}

/*
- * Set the GPIO Interrupt
+ * Set the GPIO Interrupt Sync and Async interrupts are both set/cleared.
+ * Async GPIO interrupts may not be raised when the chip is put to sleep.
*/
void
ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
{
- uint32_t val;
-
- HALASSERT(gpio < AR_NUM_GPIO);
- /* XXX bounds check gpio */
- val = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_INTR_CTRL);
- if (ilevel) /* 0 == interrupt on pin high */
- val &= ~AR_GPIO_BIT(gpio);
- else /* 1 == interrupt on pin low */
- val |= AR_GPIO_BIT(gpio);
- OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_INTR_CTRL, val);
-
- /* Change the interrupt mask. */
- val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_GPIO);
- val |= AR_GPIO_BIT(gpio);
- OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_GPIO, val);
-
- val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_GPIO);
- val |= AR_GPIO_BIT(gpio);
- OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_GPIO, val);
+ uint32_t val, mask;
+
+ HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
+
+ if (ilevel == HAL_GPIO_INTR_DISABLE) {
+ val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
+ AR_INTR_ASYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
+ AR_INTR_ASYNC_ENABLE_GPIO, val);
+
+ mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
+ AR_INTR_ASYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
+ AR_INTR_ASYNC_MASK_GPIO, mask);
+
+ /* Clear synchronous GPIO interrupt registers and pending interrupt flag */
+ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),
+ AR_INTR_SYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
+ AR_INTR_SYNC_ENABLE_GPIO, val);
+
+ mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),
+ AR_INTR_SYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
+ AR_INTR_SYNC_MASK_GPIO, mask);
+
+ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_CAUSE),
+ AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE,
+ AR_INTR_SYNC_ENABLE_GPIO, val);
+ } else {
+ val = MS(OS_REG_READ(ah, AR_GPIO_INTR_POL),
+ AR_GPIO_INTR_POL_VAL);
+ if (ilevel == HAL_GPIO_INTR_HIGH) {
+ /* 0 == interrupt on pin high */
+ val &= ~AR_GPIO_BIT(gpio);
+ } else if (ilevel == HAL_GPIO_INTR_LOW) {
+ /* 1 == interrupt on pin low */
+ val |= AR_GPIO_BIT(gpio);
+ }
+ OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL,
+ AR_GPIO_INTR_POL_VAL, val);
+
+ /* Change the interrupt mask. */
+ val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
+ AR_INTR_ASYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
+ AR_INTR_ASYNC_ENABLE_GPIO, val);
+
+ mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
+ AR_INTR_ASYNC_MASK_GPIO) | AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
+ AR_INTR_ASYNC_MASK_GPIO, mask);
+
+ /* Set synchronous GPIO interrupt registers as well */
+ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),
+ AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
+ AR_INTR_SYNC_ENABLE_GPIO, val);
+
+ mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),
+ AR_INTR_SYNC_MASK_GPIO) | AR_GPIO_BIT(gpio);
+ OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
+ AR_INTR_SYNC_MASK_GPIO, mask);
+ }
+ AH5416(ah)->ah_gpioMask = mask; /* for ar5416SetInterrupts */
}
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c
index 43fbe3f..0cdd87e 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c
@@ -104,7 +104,7 @@ ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
isr = OS_REG_READ(ah, AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
- return AH_FALSE;;
+ return AH_FALSE;
}

*masked = isr & HAL_INT_COMMON;
@@ -167,7 +167,7 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
{
struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t omask = ahp->ah_maskReg;
- uint32_t mask,mask2;
+ uint32_t mask, mask2;

HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
__func__, omask, ints);
@@ -248,11 +248,19 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);

- OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
- OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+ mask = AR_INTR_MAC_IRQ;
+ if (ints & HAL_INT_GPIO)
+ mask |= SM(AH5416(ah)->ah_gpioMask,
+ AR_INTR_ASYNC_MASK_GPIO);
+ OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask);
+ OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask);

- OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
- OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_DEFAULT);
+ mask = AR_INTR_SYNC_DEFAULT;
+ if (ints & HAL_INT_GPIO)
+ mask |= SM(AH5416(ah)->ah_gpioMask,
+ AR_INTR_SYNC_MASK_GPIO);
+ OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask);
+ OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask);
}

return omask;
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_misc.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_misc.c
index 0cbd685..30d46f8 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_misc.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_misc.c
@@ -30,7 +30,7 @@
#include "ar5416/ar5416phy.h"

/*
- * Return the wireless modes (a,b,g,t) supported by hardware.
+ * Return the wireless modes (a,b,g,n,t) supported by hardware.
*
* This value is what is actually supported by the hardware
* and is unaffected by regulatory/country code settings.
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_phy.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_phy.c
index d3368ea..9b9bc2c 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_phy.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_phy.c
@@ -34,35 +34,35 @@ HAL_RATE_TABLE ar5416_11ng_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0, 0, 0 },
-/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1, 0, 0 },
-/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 2, 0, 0 },
-/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 3, 0, 0 },
+/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0 },
+/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1 },
+/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 2 },
+/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 3 },
/* Remove rates 6, 9 from rate ctrl */
-/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4, 0, 0 },
-/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8, 0, 0 },
-/* 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 8, 0, 0 },
-/* 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 8, 0, 0 },
-/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 8, 0, 0 },
-/* 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8, 0, 0 },
-/* 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8, 0, 0 },
-/* 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8, 0, 0 },
-/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8, 0, 0 },
-/* 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8, 0, 0 },
-/* 13 Mb */ { AH_TRUE, HT, 13000, 0x88, 0x00, 8, 8, 0, 0 },
-/* 26 Mb */ { AH_TRUE, HT, 26000, 0x89, 0x00, 9, 8, 0, 0 },
-/* 39 Mb */ { AH_TRUE, HT, 39000, 0x8a, 0x00, 10, 8, 0, 0 },
-/* 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8, 0, 0 },
-/* 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8, 0, 0 },
-/* 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8, 0, 0 },
-/* 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8, 0, 0 },
-/* 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8, 0, 0 },
+/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 },
+/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 },
+/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 },
+/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 },
+/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 },
+/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 },
+/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 },
+/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 },
+/* 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 8 },
+/* 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 8 },
+/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 8 },
+/* 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8 },
+/* 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 },
+/* 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 },
+/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 },
+/* 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 },
+/* 13 Mb */ { AH_TRUE, HT, 13000, 0x88, 0x00, 8, 8 },
+/* 26 Mb */ { AH_TRUE, HT, 26000, 0x89, 0x00, 9, 8 },
+/* 39 Mb */ { AH_TRUE, HT, 39000, 0x8a, 0x00, 10, 8 },
+/* 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8 },
+/* 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 },
+/* 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 },
+/* 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 },
+/* 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 },
},
};

@@ -72,30 +72,30 @@ static HAL_RATE_TABLE ar5416_11na_table = {
{
/* short ctrl */
/* valid rateCode Preamble dot11Rate Rate */
-/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 },
-/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0, 0, 0 },
-/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 },
-/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2, 0, 0 },
-/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 },
-/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8, 0, 0 },
-/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8, 0, 0 },
-/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8, 0, 0 },
-/* 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 8, 0, 0 },
-/* 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 8, 0, 0 },
-/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 8, 0, 0 },
-/* 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8, 0, 0 },
-/* 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8, 0, 0 },
-/* 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8, 0, 0 },
-/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8, 0, 0 },
-/* 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8, 0, 0 },
-/* 13 Mb */ { AH_TRUE, HT, 13000, 0x88, 0x00, 8, 8, 0, 0 },
-/* 26 Mb */ { AH_TRUE, HT, 26000, 0x89, 0x00, 9, 8, 0, 0 },
-/* 39 Mb */ { AH_TRUE, HT, 39000, 0x8a, 0x00, 10, 8, 0, 0 },
-/* 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8, 0, 0 },
-/* 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8, 0, 0 },
-/* 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8, 0, 0 },
-/* 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8, 0, 0 },
-/* 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8, 0, 0 },
+/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0 },
+/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 },
+/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2 },
+/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 },
+/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4 },
+/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 },
+/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 },
+/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 },
+/* 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 8 },
+/* 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 8 },
+/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 8 },
+/* 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8 },
+/* 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 },
+/* 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 },
+/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 },
+/* 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 },
+/* 13 Mb */ { AH_TRUE, HT, 13000, 0x88, 0x00, 8, 8 },
+/* 26 Mb */ { AH_TRUE, HT, 26000, 0x89, 0x00, 9, 8 },
+/* 39 Mb */ { AH_TRUE, HT, 39000, 0x8a, 0x00, 10, 8 },
+/* 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8 },
+/* 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 },
+/* 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 },
+/* 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 },
+/* 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 },
},
};

diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c
index a954dff..261ee65 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -27,9 +27,6 @@
#include "ar5416/ar5416.h"
#include "ar5416/ar5416reg.h"
#include "ar5416/ar5416phy.h"
-#ifdef AH_SUPPORT_AR9280
-#include "ar5416/ar9280.h"
-#endif

/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
#define EEP_MINOR(_ah) \
@@ -43,53 +40,37 @@
#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */

static void ar5416InitDMA(struct ath_hal *ah);
-static void ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan);
+static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *);
static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);
static void ar5416InitQoS(struct ath_hal *ah);
static void ar5416InitUserSettings(struct ath_hal *ah);

-static HAL_BOOL ar5416SetTransmitPower(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain);
-
#if 0
-static HAL_BOOL ar5416ChannelChange(struct ath_hal *, HAL_CHANNEL *);
-#endif
-static void ar5416SetDeltaSlope(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
-static void ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan);
-#ifdef AH_SUPPORT_AR9280
-static void ar9280SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan);
+static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *);
#endif
+static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *);

static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
-static void ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan);
-static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
struct ar5416eeprom *pEepData,
- HAL_CHANNEL_INTERNAL *chan, int16_t *ratesArray,
+ const struct ieee80211_channel *chan, int16_t *ratesArray,
uint16_t cfgCtl, uint16_t AntennaReduction,
uint16_t twiceMaxRegulatoryPower,
uint16_t powerLimit);
static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
struct ar5416eeprom *pEepData,
- HAL_CHANNEL_INTERNAL *chan,
+ const struct ieee80211_channel *chan,
int16_t *pTxPowerIndexOffset);
static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
-static void ar5416GetTargetPowers(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, CAL_TARGET_POWER_HT *powInfo,
- uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
- uint16_t numRates, HAL_BOOL isHt40Target);
-static void ar5416GetTargetPowersLeg(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, CAL_TARGET_POWER_LEG *powInfo,
- uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
- uint16_t numRates, HAL_BOOL isExtTarget);

static int16_t interpolate(uint16_t target, uint16_t srcLeft,
uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
-static void ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan);
+static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet,
+ const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet,
uint8_t * bChans, uint16_t availPiers,
uint16_t tPdGainOverlap, int16_t *pMinCalPower,
uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
@@ -110,37 +91,22 @@ static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
*/
HAL_BOOL
ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
- HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+ struct ieee80211_channel *chan,
+ HAL_BOOL bChannelChange, HAL_STATUS *status)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
HAL_CHANNEL_INTERNAL *ichan;
- uint32_t softLedCfg;
uint32_t saveDefAntenna, saveLedState;
uint32_t macStaId1;
uint16_t rfXpdGain[2];
- u_int modesIndex, freqIndex;
HAL_STATUS ecode;
- int i, regWrites = 0;
uint32_t powerVal, rssiThrReg;
uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow;
+ int i;

OS_MARK(ah, AH_MARK_RESET, bChannelChange);
-#define IS(_c,_f) (((_c)->channelFlags & _f) || 0)
- if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
- if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
- __func__, chan->channel, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
-#undef IS

/* Bring out of sleep mode */
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
@@ -153,16 +119,8 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
* Map public channel to private.
*/
ichan = ath_hal_checkchannel(ah, chan);
- if (ichan == AH_NULL) {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: invalid channel %u/0x%x; no mapping\n",
- __func__, chan->channel, chan->channelFlags);
+ if (ichan == AH_NULL)
FAIL(HAL_EINVAL);
- } else {
- HALDEBUG(ah, HAL_DEBUG_RESET,
- "%s: Ch=%u Max=%d Min=%d\n",__func__,
- ichan->channel, ichan->maxTxPower, ichan->minTxPower);
- }
switch (opmode) {
case HAL_M_STA:
case HAL_M_IBSS:
@@ -202,13 +160,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
saveLedState = OS_REG_READ(ah, AR_MAC_LED) &
(AR_MAC_LED_ASSOC | AR_MAC_LED_MODE |
AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW);
- softLedCfg = OS_REG_READ(ah, AR_GPIO_INTR_OUT);
-
- /*
- * Adjust gain parameters before reset if
- * there's an outstanding gain updated.
- */
- (void) ar5416GetRfgain(ah);

if (!ar5416ChipReset(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
@@ -218,83 +169,12 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
/* Restore bmiss rssi & count thresholds */
OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg);

- /* Setup the indices for the next set of register array writes */
- /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
- switch (chan->channelFlags & CHANNEL_ALL) {
- case CHANNEL_A:
- case CHANNEL_A_HT20:
- modesIndex = 1;
- freqIndex = 1;
- break;
- case CHANNEL_T:
- case CHANNEL_A_HT40PLUS:
- case CHANNEL_A_HT40MINUS:
- modesIndex = 2;
- freqIndex = 1;
- break;
- case CHANNEL_PUREG:
- case CHANNEL_G_HT20:
- case CHANNEL_B: /* treat as channel G , no B mode suport in owl */
- modesIndex = 4;
- freqIndex = 2;
- break;
- case CHANNEL_G_HT40PLUS:
- case CHANNEL_G_HT40MINUS:
- modesIndex = 3;
- freqIndex = 2;
- break;
- case CHANNEL_108G:
- modesIndex = 5;
- freqIndex = 2;
- break;
- default:
- HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
- __func__, chan->channelFlags);
- FAIL(HAL_EINVAL);
- }
-
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

- /* Set correct Baseband to analog shift setting to access analog chips. */
- OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+ AH5416(ah)->ah_writeIni(ah, chan);

- /*
- * Write addac shifts
- */
- OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
-#if 0
- /* NB: only required for Sowl */
- ar5416EepromSetAddac(ah, ichan);
-#endif
- regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
- regWrites);
- OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
-
- /* XXX Merlin ini fixups */
- /* XXX Merlin 100us delay for shift registers */
- regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex,
- regWrites);
-#ifdef AH_SUPPORT_AR9280
- if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
- regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
- modesIndex, regWrites);
- regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
- modesIndex, regWrites);
- }
-#endif
- /* XXX Merlin 100us delay for shift registers */
- regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_common, 1, regWrites);
/* Setup 11n MAC/Phy mode registers */
- ar5416Set11nRegs(ah,chan);
- /* XXX updated regWrites? */
- ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
-#ifdef AH_SUPPORT_AR9280
- if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
- /* 5GHz channels w/ Fast Clock use different modal values */
- regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
- modesIndex, regWrites);
- }
-#endif
+ ar5416Set11nRegs(ah, chan);

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);

@@ -332,32 +212,28 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);

/* Setup the transmit power values. */
- if (!ar5416SetTransmitPower(ah, ichan, rfXpdGain)) {
+ if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error init'ing transmit power\n", __func__);
FAIL(HAL_EIO);
}

/* Write the analog registers */
- if (!ahp->ah_rfHal->setRfRegs(ah, ichan, freqIndex, rfXpdGain)) {
+ if (!ahp->ah_rfHal->setRfRegs(ah, chan,
+ IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: ar5212SetRfRegs failed\n", __func__);
FAIL(HAL_EIO);
}

/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
- if (IS_CHAN_OFDM(chan)|| IS_CHAN_HT(chan))
- ar5416SetDeltaSlope(ah, ichan);
+ if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan))
+ ar5416SetDeltaSlope(ah, chan);

-#ifdef AH_SUPPORT_AR9280
- if (AR_SREV_MERLIN_10_OR_LATER(ah))
- ar9280SpurMitigate(ah, ichan);
- else
-#endif
- ar5416SpurMitigate(ah, ichan);
+ AH5416(ah)->ah_spurMitigate(ah, chan);

/* Setup board specific options for EEPROM version 3 */
- if (!ar5416SetBoardValues(ah, ichan)) {
+ if (!ah->ah_setBoardValues(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error setting board options\n", __func__);
FAIL(HAL_EIO);
@@ -379,8 +255,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,

/* Restore previous led state */
OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState);
- /* Restore soft Led state to GPIO */
- OS_REG_WRITE(ah, AR_GPIO_INTR_OUT, softLedCfg);

/* Restore previous antenna */
OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
@@ -394,7 +268,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,

OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */

- if (!ar5212SetChannel(ah, ichan))
+ if (!ar5212SetChannel(ah, chan))
FAIL(HAL_EIO);

OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
@@ -453,15 +327,8 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,

AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */

- if (bChannelChange) {
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
- chan->maxRegTxPower = ichan->maxRegTxPower;
- chan->maxTxPower = ichan->maxTxPower;
- chan->minTxPower = ichan->minTxPower;
- }
+ if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
+ chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;

HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);

@@ -470,7 +337,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
return AH_TRUE;
bad:
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
- if (*status)
+ if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
@@ -485,7 +352,7 @@ bad:
* time, the function returns false as a reset is necessary
*/
HAL_BOOL
-ar5416ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan)
{
uint32_t ulCount;
uint32_t data, synthDelay, qnum;
@@ -520,11 +387,11 @@ ar5416ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */

/* Change the synth */
- if (!ar5212SetChannel(ah, ichan))
+ if (!ar5212SetChannel(ah, chan))
return AH_FALSE;

/* Setup the transmit power values. */
- if (!ar5416SetTransmitPower(ah, ichan, rfXpdGain)) {
+ if (!ar5416SetTransmitPower(ah, chan, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error init'ing transmit power\n", __func__);
return AH_FALSE;
@@ -548,27 +415,20 @@ ar5416ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);

/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
- if (IS_CHAN_OFDM(ichan)|| IS_CHAN_HT(chan)) {
- if (ahp->ah_eeprom.ee_version >= AR_EEPROM_VER5_3 &&
- !IS_CHAN_B(chan))
- ar5212SetSpurMitigation(ah, ichan);
- ar5416SetDeltaSlope(ah, ichan);
+ if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) {
+ HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3);
+ ar5212SetSpurMitigation(ah, chan);
+ ar5416SetDeltaSlope(ah, chan);
}

/* XXX spur mitigation for Melin */

- /* Copy over internal channel flags to public hal channel */
-
- if (!(ichan->privFlags & CHANNEL_DFS))
- ichan->privFlags &= ~CHANNEL_INTERFERENCE;
- chan->channelFlags = ichan->channelFlags;
- chan->privFlags = ichan->privFlags;
- chan->maxRegTxPower = ichan->maxRegTxPower;
- chan->maxTxPower = ichan->maxTxPower;
- chan->minTxPower = ichan->minTxPower;
- AH_PRIVATE(ah)->ah_curchan->ah_channel_time=0;
- AH_PRIVATE(ah)->ah_curchan->ah_tsf_last = ar5212GetTsf64(ah);
- ar5212TxEnable(ah,AH_TRUE);
+ if (!IEEE80211_IS_CHAN_DFS(chan))
+ chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
+
+ ichan->channel_time = 0;
+ ichan->tsf_last = ar5212GetTsf64(ah);
+ ar5212TxEnable(ah, AH_TRUE);
return AH_TRUE;
}
#endif
@@ -576,6 +436,7 @@ ar5416ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
static void
ar5416InitDMA(struct ath_hal *ah)
{
+ struct ath_hal_5212 *ahp = AH5212(ah);

/*
* set AHB_MODE not to do cacheline prefetches
@@ -594,7 +455,10 @@ ar5416InitDMA(struct ath_hal *ah)
OS_REG_WRITE(ah, AR_RXCFG,
(OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B);

- /* XXX restore TX trigger level */
+ /* restore TX trigger level */
+ OS_REG_WRITE(ah, AR_TXCFG,
+ (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) |
+ SM(ahp->ah_txTrigLev, AR_FTRIG));

/*
* Setup receive FIFO threshold to hold off TX activities
@@ -609,7 +473,7 @@ ar5416InitDMA(struct ath_hal *ah)
}

static void
-ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t synthDelay;

@@ -619,7 +483,7 @@ ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan)
* Value is in 100ns increments.
*/
synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
- if (IS_CHAN_CCK(chan)) {
+ if (IEEE80211_IS_CHAN_CCK(chan)) {
synthDelay = (4 * synthDelay) / 22;
} else {
synthDelay /= 10;
@@ -627,7 +491,7 @@ ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan)

/* Turn on PLL on 5416 */
HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n",
- __func__, IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz");
+ __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz");
ar5416InitPLL(ah, chan);

/* Activate the PHY (includes baseband activate and synthesizer on) */
@@ -639,9 +503,9 @@ ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan)
* extra BASE_ACTIVATE_DELAY usecs to ensure this condition
* does not happen.
*/
- if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ if (IEEE80211_IS_CHAN_HALF(chan)) {
OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
- } else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
} else {
OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
@@ -673,10 +537,9 @@ ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode)
ahp->ah_maskReg |= AR_IMR_MIB;
OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
/* Enable bus errors that are OR'd to set the HIUERR bit */
-
#if 0
OS_REG_WRITE(ah, AR_IMR_S2,
- OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);
+ OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);
#endif
}

@@ -731,11 +594,9 @@ ar5416InitUserSettings(struct ath_hal *ah)
* Places the hardware into reset and then pulls it out of reset
*/
HAL_BOOL
-ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
- uint32_t rfMode = 0;
-
- OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
+ OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
/*
* Warm reset is optimistic.
*/
@@ -761,15 +622,17 @@ ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
* radio device.
*/
if (chan != AH_NULL) {
+ uint32_t rfMode;
+
/* treat channel B as channel G , no B mode suport in owl */
- rfMode |= (IS_CHAN_G(chan) || IS_CHAN_B(chan)) ?
- AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
+ rfMode = IEEE80211_IS_CHAN_CCK(chan) ?
+ AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
/* phy mode bits for 5GHz channels require Fast Clock */
rfMode |= AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE;
} else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) {
- rfMode |= (IS_CHAN_5GHZ(chan)) ?
+ rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ?
AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
}
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
@@ -811,23 +674,23 @@ ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled,
}

void
-ar5416SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
#define INIT_CLOCKMHZSCALED 0x64000000
uint32_t coef_scaled, ds_coef_exp, ds_coef_man;
- uint32_t clockMhzScaled = INIT_CLOCKMHZSCALED;
+ uint32_t clockMhzScaled;

CHAN_CENTERS centers;

- if (IS_CHAN_TURBO(chan))
- clockMhzScaled *= 2;
/* half and quarter rate can divide the scaled clock by 2 or 4 respectively */
/* scale for selected channel bandwidth */
- if (IS_CHAN_HALF_RATE(chan)) {
- clockMhzScaled = clockMhzScaled >> 1;
- } else if (IS_CHAN_QUARTER_RATE(chan)) {
- clockMhzScaled = clockMhzScaled >> 2;
- }
+ clockMhzScaled = INIT_CLOCKMHZSCALED;
+ if (IEEE80211_IS_CHAN_TURBO(chan))
+ clockMhzScaled <<= 1;
+ else if (IEEE80211_IS_CHAN_HALF(chan))
+ clockMhzScaled >>= 1;
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ clockMhzScaled >>= 2;

/*
* ALGO -> coef = 1e8/fcarrier*fclock/40;
@@ -835,14 +698,14 @@ ar5416SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
*/
ar5416GetChannelCenters(ah, chan, &centers);
coef_scaled = clockMhzScaled / centers.synth_center;
-
+
ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
-
+
/*
* For Short GI,
* scaled coeff is 9/10 that of normal coeff
@@ -860,556 +723,6 @@ ar5416SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
}

/*
- * Convert to baseband spur frequency given input channel frequency
- * and compute register settings below.
- */
-#define SPUR_RSSI_THRESH 40
-
-static void
-ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
-{
- static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
- AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
- static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
- AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
- static const int inc[4] = { 0, 100, 0, 0 };
-
- int bb_spur = AR_NO_SPUR;
- int bin, cur_bin;
- int spur_freq_sd;
- int spur_delta_phase;
- int denominator;
- int upper, lower, cur_vit_mask;
- int tmp, new;
- int i;
-
- int8_t mask_m[123];
- int8_t mask_p[123];
- int8_t mask_amt;
- int tmp_mask;
- int cur_bb_spur;
- HAL_BOOL is2GHz = IS_CHAN_2GHZ(chan);
-
- OS_MEMZERO(mask_m, sizeof(mask_m));
- OS_MEMZERO(mask_p, sizeof(mask_p));
-
- /*
- * Need to verify range +/- 9.5 for static ht20, otherwise spur
- * is out-of-band and can be ignored.
- */
- for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
- cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
- if (AR_NO_SPUR == cur_bb_spur)
- break;
- cur_bb_spur = cur_bb_spur - (chan->channel * 10);
- if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
- bb_spur = cur_bb_spur;
- break;
- }
- }
- if (AR_NO_SPUR == bb_spur)
- return;
-
- bin = bb_spur * 32;
-
- tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
- new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
- AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
- AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
- AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
-
- OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
-
- new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
- AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
- AR_PHY_SPUR_REG_MASK_RATE_SELECT |
- AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
- SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
- OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
- /*
- * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
- * config, no offset for HT20.
- * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
- * /80 for dyn2040.
- */
- spur_delta_phase = ((bb_spur * 524288) / 100) &
- AR_PHY_TIMING11_SPUR_DELTA_PHASE;
- /*
- * in 11A mode the denominator of spur_freq_sd should be 40 and
- * it should be 44 in 11G
- */
- denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
- spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
-
- new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
- SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
- SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
- OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
-
-
- /*
- * ============================================
- * pilot mask 1 [31:0] = +6..-26, no 0 bin
- * pilot mask 2 [19:0] = +26..+7
- *
- * channel mask 1 [31:0] = +6..-26, no 0 bin
- * channel mask 2 [19:0] = +26..+7
- */
- //cur_bin = -26;
- cur_bin = -6000;
- upper = bin + 100;
- lower = bin - 100;
-
- for (i = 0; i < 4; i++) {
- int pilot_mask = 0;
- int chan_mask = 0;
- int bp = 0;
- for (bp = 0; bp < 30; bp++) {
- if ((cur_bin > lower) && (cur_bin < upper)) {
- pilot_mask = pilot_mask | 0x1 << bp;
- chan_mask = chan_mask | 0x1 << bp;
- }
- cur_bin += 100;
- }
- cur_bin += inc[i];
- OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
- OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
- }
-
- /* =================================================
- * viterbi mask 1 based on channel magnitude
- * four levels 0-3
- * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
- * [1 2 2 1] for -9.6 or [1 2 1] for +16
- * - enable_mask_ppm, all bins move with freq
- *
- * - mask_select, 8 bits for rates (reg 67,0x990c)
- * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
- * choose which mask to use mask or mask2
- */
-
- /*
- * viterbi mask 2 2nd set for per data rate puncturing
- * four levels 0-3
- * - mask_select, 8 bits for rates (reg 67)
- * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
- * [1 2 2 1] for -9.6 or [1 2 1] for +16
- */
- cur_vit_mask = 6100;
- upper = bin + 120;
- lower = bin - 120;
-
- for (i = 0; i < 123; i++) {
- if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
- if ((abs(cur_vit_mask - bin)) < 75) {
- mask_amt = 1;
- } else {
- mask_amt = 0;
- }
- if (cur_vit_mask < 0) {
- mask_m[abs(cur_vit_mask / 100)] = mask_amt;
- } else {
- mask_p[cur_vit_mask / 100] = mask_amt;
- }
- }
- cur_vit_mask -= 100;
- }
-
- tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
- | (mask_m[48] << 26) | (mask_m[49] << 24)
- | (mask_m[50] << 22) | (mask_m[51] << 20)
- | (mask_m[52] << 18) | (mask_m[53] << 16)
- | (mask_m[54] << 14) | (mask_m[55] << 12)
- | (mask_m[56] << 10) | (mask_m[57] << 8)
- | (mask_m[58] << 6) | (mask_m[59] << 4)
- | (mask_m[60] << 2) | (mask_m[61] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
-
- tmp_mask = (mask_m[31] << 28)
- | (mask_m[32] << 26) | (mask_m[33] << 24)
- | (mask_m[34] << 22) | (mask_m[35] << 20)
- | (mask_m[36] << 18) | (mask_m[37] << 16)
- | (mask_m[48] << 14) | (mask_m[39] << 12)
- | (mask_m[40] << 10) | (mask_m[41] << 8)
- | (mask_m[42] << 6) | (mask_m[43] << 4)
- | (mask_m[44] << 2) | (mask_m[45] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
-
- tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
- | (mask_m[18] << 26) | (mask_m[18] << 24)
- | (mask_m[20] << 22) | (mask_m[20] << 20)
- | (mask_m[22] << 18) | (mask_m[22] << 16)
- | (mask_m[24] << 14) | (mask_m[24] << 12)
- | (mask_m[25] << 10) | (mask_m[26] << 8)
- | (mask_m[27] << 6) | (mask_m[28] << 4)
- | (mask_m[29] << 2) | (mask_m[30] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
-
- tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
- | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
- | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
- | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
- | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
- | (mask_m[10] << 10) | (mask_m[11] << 8)
- | (mask_m[12] << 6) | (mask_m[13] << 4)
- | (mask_m[14] << 2) | (mask_m[15] << 0);
- OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
-
- tmp_mask = (mask_p[15] << 28)
- | (mask_p[14] << 26) | (mask_p[13] << 24)
- | (mask_p[12] << 22) | (mask_p[11] << 20)
- | (mask_p[10] << 18) | (mask_p[ 9] << 16)
- | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
- | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
- | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
- | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
-
- tmp_mask = (mask_p[30] << 28)
- | (mask_p[29] << 26) | (mask_p[28] << 24)
- | (mask_p[27] << 22) | (mask_p[26] << 20)
- | (mask_p[25] << 18) | (mask_p[24] << 16)
- | (mask_p[23] << 14) | (mask_p[22] << 12)
- | (mask_p[21] << 10) | (mask_p[20] << 8)
- | (mask_p[19] << 6) | (mask_p[18] << 4)
- | (mask_p[17] << 2) | (mask_p[16] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
-
- tmp_mask = (mask_p[45] << 28)
- | (mask_p[44] << 26) | (mask_p[43] << 24)
- | (mask_p[42] << 22) | (mask_p[41] << 20)
- | (mask_p[40] << 18) | (mask_p[39] << 16)
- | (mask_p[38] << 14) | (mask_p[37] << 12)
- | (mask_p[36] << 10) | (mask_p[35] << 8)
- | (mask_p[34] << 6) | (mask_p[33] << 4)
- | (mask_p[32] << 2) | (mask_p[31] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
-
- tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
- | (mask_p[59] << 26) | (mask_p[58] << 24)
- | (mask_p[57] << 22) | (mask_p[56] << 20)
- | (mask_p[55] << 18) | (mask_p[54] << 16)
- | (mask_p[53] << 14) | (mask_p[52] << 12)
- | (mask_p[51] << 10) | (mask_p[50] << 8)
- | (mask_p[49] << 6) | (mask_p[48] << 4)
- | (mask_p[47] << 2) | (mask_p[46] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
-}
-
-#ifdef AH_SUPPORT_AR9280
-#define AR_BASE_FREQ_2GHZ 2300
-#define AR_BASE_FREQ_5GHZ 4900
-#define AR_SPUR_FEEQ_BOUND_HT40 19
-#define AR_SPUR_FEEQ_BOUND_HT20 10
-
-static void
-ar9280SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
-{
- static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
- AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
- static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
- AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
- static int inc[4] = { 0, 100, 0, 0 };
-
- int bb_spur = AR_NO_SPUR;
- int freq;
- int bin, cur_bin;
- int bb_spur_off, spur_subchannel_sd;
- int spur_freq_sd;
- int spur_delta_phase;
- int denominator;
- int upper, lower, cur_vit_mask;
- int tmp, newVal;
- int i;
- CHAN_CENTERS centers;
-
- int8_t mask_m[123];
- int8_t mask_p[123];
- int8_t mask_amt;
- int tmp_mask;
- int cur_bb_spur;
- HAL_BOOL is2GHz = IS_CHAN_2GHZ(ichan);
-
- OS_MEMZERO(&mask_m, sizeof(int8_t) * 123);
- OS_MEMZERO(&mask_p, sizeof(int8_t) * 123);
-
- ar5416GetChannelCenters(ah, ichan, &centers);
- freq = centers.synth_center;
-
- /*
- * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40,
- * otherwise spur is out-of-band and can be ignored.
- */
- for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
- cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
- /* Get actual spur freq in MHz from EEPROM read value */
- if (is2GHz) {
- cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
- } else {
- cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
- }
-
- if (AR_NO_SPUR == cur_bb_spur)
- break;
- cur_bb_spur = cur_bb_spur - freq;
-
- if (IS_CHAN_HT40(ichan)) {
- if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
- (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
- bb_spur = cur_bb_spur;
- break;
- }
- } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
- (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
- bb_spur = cur_bb_spur;
- break;
- }
- }
-
- if (AR_NO_SPUR == bb_spur) {
-#if 1
- /*
- * MRC CCK can interfere with beacon detection and cause deaf/mute.
- * Disable MRC CCK for now.
- */
- OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
-#else
- /* Enable MRC CCK if no spur is found in this channel. */
- OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
-#endif
- return;
- } else {
- /*
- * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur
- * is found in this channel.
- */
- OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
- }
-
- bin = bb_spur * 320;
-
- tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
-
- newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
- AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
- AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
- AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
- OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
-
- newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
- AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
- AR_PHY_SPUR_REG_MASK_RATE_SELECT |
- AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
- SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
- OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
-
- /* Pick control or extn channel to cancel the spur */
- if (IS_CHAN_HT40(ichan)) {
- if (bb_spur < 0) {
- spur_subchannel_sd = 1;
- bb_spur_off = bb_spur + 10;
- } else {
- spur_subchannel_sd = 0;
- bb_spur_off = bb_spur - 10;
- }
- } else {
- spur_subchannel_sd = 0;
- bb_spur_off = bb_spur;
- }
-
- /*
- * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
- * /80 for dyn2040.
- */
- if (IS_CHAN_HT40(ichan))
- spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
- else
- spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
-
- /*
- * in 11A mode the denominator of spur_freq_sd should be 40 and
- * it should be 44 in 11G
- */
- denominator = IS_CHAN_2GHZ(ichan) ? 44 : 40;
- spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
-
- newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
- SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
- SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
- OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
-
- /* Choose to cancel between control and extension channels */
- newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
- OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
-
- /*
- * ============================================
- * Set Pilot and Channel Masks
- *
- * pilot mask 1 [31:0] = +6..-26, no 0 bin
- * pilot mask 2 [19:0] = +26..+7
- *
- * channel mask 1 [31:0] = +6..-26, no 0 bin
- * channel mask 2 [19:0] = +26..+7
- */
- cur_bin = -6000;
- upper = bin + 100;
- lower = bin - 100;
-
- for (i = 0; i < 4; i++) {
- int pilot_mask = 0;
- int chan_mask = 0;
- int bp = 0;
- for (bp = 0; bp < 30; bp++) {
- if ((cur_bin > lower) && (cur_bin < upper)) {
- pilot_mask = pilot_mask | 0x1 << bp;
- chan_mask = chan_mask | 0x1 << bp;
- }
- cur_bin += 100;
- }
- cur_bin += inc[i];
- OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
- OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
- }
-
- /* =================================================
- * viterbi mask 1 based on channel magnitude
- * four levels 0-3
- * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
- * [1 2 2 1] for -9.6 or [1 2 1] for +16
- * - enable_mask_ppm, all bins move with freq
- *
- * - mask_select, 8 bits for rates (reg 67,0x990c)
- * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
- * choose which mask to use mask or mask2
- */
-
- /*
- * viterbi mask 2 2nd set for per data rate puncturing
- * four levels 0-3
- * - mask_select, 8 bits for rates (reg 67)
- * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
- * [1 2 2 1] for -9.6 or [1 2 1] for +16
- */
- cur_vit_mask = 6100;
- upper = bin + 120;
- lower = bin - 120;
-
- for (i = 0; i < 123; i++) {
- if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
- if ((abs(cur_vit_mask - bin)) < 75) {
- mask_amt = 1;
- } else {
- mask_amt = 0;
- }
- if (cur_vit_mask < 0) {
- mask_m[abs(cur_vit_mask / 100)] = mask_amt;
- } else {
- mask_p[cur_vit_mask / 100] = mask_amt;
- }
- }
- cur_vit_mask -= 100;
- }
-
- tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
- | (mask_m[48] << 26) | (mask_m[49] << 24)
- | (mask_m[50] << 22) | (mask_m[51] << 20)
- | (mask_m[52] << 18) | (mask_m[53] << 16)
- | (mask_m[54] << 14) | (mask_m[55] << 12)
- | (mask_m[56] << 10) | (mask_m[57] << 8)
- | (mask_m[58] << 6) | (mask_m[59] << 4)
- | (mask_m[60] << 2) | (mask_m[61] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
-
- tmp_mask = (mask_m[31] << 28)
- | (mask_m[32] << 26) | (mask_m[33] << 24)
- | (mask_m[34] << 22) | (mask_m[35] << 20)
- | (mask_m[36] << 18) | (mask_m[37] << 16)
- | (mask_m[48] << 14) | (mask_m[39] << 12)
- | (mask_m[40] << 10) | (mask_m[41] << 8)
- | (mask_m[42] << 6) | (mask_m[43] << 4)
- | (mask_m[44] << 2) | (mask_m[45] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
-
- tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
- | (mask_m[18] << 26) | (mask_m[18] << 24)
- | (mask_m[20] << 22) | (mask_m[20] << 20)
- | (mask_m[22] << 18) | (mask_m[22] << 16)
- | (mask_m[24] << 14) | (mask_m[24] << 12)
- | (mask_m[25] << 10) | (mask_m[26] << 8)
- | (mask_m[27] << 6) | (mask_m[28] << 4)
- | (mask_m[29] << 2) | (mask_m[30] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
-
- tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
- | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
- | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
- | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
- | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
- | (mask_m[10] << 10) | (mask_m[11] << 8)
- | (mask_m[12] << 6) | (mask_m[13] << 4)
- | (mask_m[14] << 2) | (mask_m[15] << 0);
- OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
-
- tmp_mask = (mask_p[15] << 28)
- | (mask_p[14] << 26) | (mask_p[13] << 24)
- | (mask_p[12] << 22) | (mask_p[11] << 20)
- | (mask_p[10] << 18) | (mask_p[ 9] << 16)
- | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
- | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
- | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
- | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
-
- tmp_mask = (mask_p[30] << 28)
- | (mask_p[29] << 26) | (mask_p[28] << 24)
- | (mask_p[27] << 22) | (mask_p[26] << 20)
- | (mask_p[25] << 18) | (mask_p[24] << 16)
- | (mask_p[23] << 14) | (mask_p[22] << 12)
- | (mask_p[21] << 10) | (mask_p[20] << 8)
- | (mask_p[19] << 6) | (mask_p[18] << 4)
- | (mask_p[17] << 2) | (mask_p[16] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
-
- tmp_mask = (mask_p[45] << 28)
- | (mask_p[44] << 26) | (mask_p[43] << 24)
- | (mask_p[42] << 22) | (mask_p[41] << 20)
- | (mask_p[40] << 18) | (mask_p[39] << 16)
- | (mask_p[38] << 14) | (mask_p[37] << 12)
- | (mask_p[36] << 10) | (mask_p[35] << 8)
- | (mask_p[34] << 6) | (mask_p[33] << 4)
- | (mask_p[32] << 2) | (mask_p[31] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
-
- tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
- | (mask_p[59] << 26) | (mask_p[58] << 24)
- | (mask_p[57] << 22) | (mask_p[56] << 20)
- | (mask_p[55] << 18) | (mask_p[54] << 16)
- | (mask_p[53] << 14) | (mask_p[52] << 12)
- | (mask_p[51] << 10) | (mask_p[50] << 8)
- | (mask_p[49] << 6) | (mask_p[48] << 4)
- | (mask_p[47] << 2) | (mask_p[46] << 0);
- OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
- OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
-}
-#endif /* AH_SUPPORT_AR9280 */
-
-/*
* Set a limit on the overall output power. Used for dynamic
* transmit power control and the like.
*
@@ -1426,37 +739,29 @@ ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
}

HAL_BOOL
-ar5416GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+ar5416GetChipPowerLimits(struct ath_hal *ah,
+ struct ieee80211_channel *chan)
{
struct ath_hal_5212 *ahp = AH5212(ah);
int16_t minPower, maxPower;
- HAL_CHANNEL *chan;
- int i;

/*
* Get Pier table max and min powers.
*/
- for (i = 0; i < nchans; i++) {
- chan = &chans[i];
- if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
- /* NB: rf code returns 1/4 dBm units, convert */
- chan->maxTxPower = maxPower / 2;
- chan->minTxPower = minPower / 2;
- } else {
- HALDEBUG(ah, HAL_DEBUG_ANY,
- "%s: no min/max power for %u/0x%x\n",
- __func__, chan->channel, chan->channelFlags);
- chan->maxTxPower = AR5416_MAX_RATE_POWER;
- chan->minTxPower = 0;
- }
- }
-#ifdef AH_DEBUG
- for (i=0; i<nchans; i++) {
- HALDEBUG(ah, HAL_DEBUG_RESET,
- "Chan %d: MaxPow = %d MinPow = %d\n",
- chans[i].channel,chans[i].maxTxPower, chans[i].minTxPower);
+ if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
+ /* NB: rf code returns 1/4 dBm units, convert */
+ chan->ic_maxpower = maxPower / 2;
+ chan->ic_minpower = minPower / 2;
+ } else {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: no min/max power for %u/0x%x\n",
+ __func__, chan->ic_freq, chan->ic_flags);
+ chan->ic_maxpower = AR5416_MAX_RATE_POWER;
+ chan->ic_minpower = 0;
}
-#endif
+ HALDEBUG(ah, HAL_DEBUG_RESET,
+ "Chan %d: MaxPow = %d MinPow = %d\n",
+ chan->ic_freq, chan->ic_maxpower, chan->ic_minpower);
return AH_TRUE;
}

@@ -1480,8 +785,9 @@ typedef enum Ar5416_Rates {
* Set the transmit power in the baseband for the given
* operating channel and mode.
*/
-static HAL_BOOL
-ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain)
+HAL_BOOL
+ar5416SetTransmitPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
{
#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
#define N(a) (sizeof (a) / sizeof (a[0]))
@@ -1504,14 +810,14 @@ ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t
HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);

/* Setup info for the actual eeprom */
- ath_hal_memzero(ratesArray, sizeof(ratesArray));
- cfgCtl = ath_hal_getctl(ah, (HAL_CHANNEL *)chan);
- powerLimit = chan->maxRegTxPower * 2;
- twiceAntennaReduction = chan->antennaMax;
+ OS_MEMZERO(ratesArray, sizeof(ratesArray));
+ cfgCtl = ath_hal_getctl(ah, chan);
+ powerLimit = chan->ic_maxregpower * 2;
+ twiceAntennaReduction = chan->ic_maxantgain;
twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
- pModal = &pEepData->modalHeader[IS_CHAN_2GHZ(chan)];
+ pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
- __func__,chan->channel, cfgCtl );
+ __func__,chan->ic_freq, cfgCtl );

if (IS_EEP_MINOR_V2(ah)) {
ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
@@ -1534,11 +840,11 @@ ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t

maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);

- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
}

- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
}

@@ -1574,7 +880,7 @@ ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t
| POW_SM(ratesArray[rate24mb], 0)
);

- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
/* Write the CCK power per rate set */
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
POW_SM(ratesArray[rate2s], 24)
@@ -1608,7 +914,7 @@ ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t
| POW_SM(ratesArray[rateHt20_4], 0)
);

- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
/* Write the HT40 power per rate set */
/* Correct PAR difference between HT40 and HT20/LEGACY */
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
@@ -1681,21 +987,14 @@ ar5416PhyDisable(struct ath_hal *ah)
HAL_BOOL
ar5416SetResetReg(struct ath_hal *ah, uint32_t type)
{
- /*
- * Set force wake
- */
- OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
- AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
-
switch (type) {
case HAL_RESET_POWER_ON:
return ar5416SetResetPowerOn(ah);
- break;
case HAL_RESET_WARM:
case HAL_RESET_COLD:
return ar5416SetReset(ah, type);
- break;
default:
+ HALASSERT(AH_FALSE);
return AH_FALSE;
}
}
@@ -1738,7 +1037,7 @@ ar5416SetResetPowerOn(struct ath_hal *ah)
static HAL_BOOL
ar5416SetReset(struct ath_hal *ah, int type)
{
- uint32_t tmpReg;
+ uint32_t tmpReg, mask;

/*
* Force wake
@@ -1764,11 +1063,11 @@ ar5416SetReset(struct ath_hal *ah, int type)
case HAL_RESET_WARM:
OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM);
break;
- case HAL_RESET_COLD:
+ case HAL_RESET_COLD:
OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD);
break;
- default:
- HALASSERT(0);
+ default:
+ HALASSERT(AH_FALSE);
break;
}

@@ -1784,23 +1083,22 @@ ar5416SetReset(struct ath_hal *ah, int type)
/* Clear AHB reset */
OS_REG_WRITE(ah, AR_RC, 0);

- /* Set register and descriptor swapping on
- * Bigendian platforms on cold reset
- */
-#ifdef __BIG_ENDIAN__
- if (type == HAL_RESET_COLD) {
- uint32_t mask;
-
- HALDEBUG(ah, HAL_DEBUG_RESET,
- "%s Applying descriptor swap\n", __func__);
-
- mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
+ if (type == HAL_RESET_COLD) {
+ if (isBigEndian()) {
+ /*
+ * Set CFG, little-endian for register
+ * and descriptor accesses.
+ */
+ mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
#ifndef AH_NEED_DESC_SWAP
- mask |= AR_CFG_SWTD;
+ mask |= AR_CFG_SWTD;
#endif
- OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
+ HALDEBUG(ah, HAL_DEBUG_RESET,
+ "%s Applying descriptor swap\n", __func__);
+ OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
+ } else
+ OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
}
-#endif

ar5416InitPLL(ah, AH_NULL);

@@ -1812,62 +1110,57 @@ ar5416SetReset(struct ath_hal *ah, int type)
#endif

static void
-ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t pll;

- if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+ if (AR_SREV_MERLIN_20(ah) &&
+ chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) {
+ /*
+ * PLL WAR for Merlin 2.0/2.1
+ * When doing fast clock, set PLL to 0x142c
+ * Else, set PLL to 0x2850 to prevent reset-to-reset variation
+ */
+ pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
+ } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
-
- if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) {
- pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
- } else if (chan && IS_CHAN_QUARTER_RATE(chan)) {
- pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
- }
- if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) {
- pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
-
- /*
- * PLL WAR for Merlin 2.0/2.1
- * When doing fast clock, set PLL to 0x142c
- * Else, set PLL to 0x2850 to prevent reset-to-reset variation
- */
- if (AR_SREV_MERLIN_20(ah)) {
- if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
- pll = 0x142c;
- } else {
- pll = 0x2850;
- }
- }
- } else {
+ if (chan != AH_NULL) {
+ if (IEEE80211_IS_CHAN_HALF(chan))
+ pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_5GHZ(chan))
+ pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
+ else
+ pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
+ } else
pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
- }
} else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
-
- if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) {
- pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
- } else if (chan && IS_CHAN_QUARTER_RATE(chan)) {
- pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
- }
- if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) {
- pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
- } else {
+ if (chan != AH_NULL) {
+ if (IEEE80211_IS_CHAN_HALF(chan))
+ pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_5GHZ(chan))
+ pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
+ else
+ pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
+ } else
pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
- }
} else {
pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
-
- if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) {
- pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
- } else if (chan != AH_NULL && IS_CHAN_QUARTER_RATE(chan)) {
- pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
- }
- if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) {
- pll |= SM(0xa, AR_RTC_PLL_DIV);
- } else {
+ if (chan != AH_NULL) {
+ if (IEEE80211_IS_CHAN_HALF(chan))
+ pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_5GHZ(chan))
+ pll |= SM(0xa, AR_RTC_PLL_DIV);
+ else
+ pll |= SM(0xb, AR_RTC_PLL_DIV);
+ } else
pll |= SM(0xb, AR_RTC_PLL_DIV);
- }
}
OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

@@ -1884,8 +1177,8 @@ ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan)
* Read EEPROM header info and program the device for correct operation
* given the channel value.
*/
-static HAL_BOOL
-ar5416SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+HAL_BOOL
+ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
const struct ar5416eeprom *eep = &ee->ee_base;
@@ -1894,9 +1187,10 @@ ar5416SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */

HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
- pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
+ pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];

- txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; /* workaround for eeprom versions <= 14.2 */
+ /* NB: workaround for eeprom versions <= 14.2 */
+ txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;

OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
@@ -1968,7 +1262,7 @@ ar5416SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
}

if (IS_EEP_MINOR_V3(ah)) {
- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
/* Overwrite switch settling with HT40 value */
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
}
@@ -2012,7 +1306,7 @@ ar5416SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
*/
static HAL_BOOL
ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
- HAL_CHANNEL_INTERNAL *chan,
+ const struct ieee80211_channel *chan,
int16_t *ratesArray, uint16_t cfgCtl,
uint16_t AntennaReduction,
uint16_t twiceMaxRegulatoryPower,
@@ -2050,29 +1344,30 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,

/* Compute TxPower reduction due to Antenna Gain */

- twiceLargestAntenna = AH_MAX(AH_MAX(pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[0],
- pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
- pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
+ twiceLargestAntenna = AH_MAX(AH_MAX(
+ pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
+ pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
+ pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
#if 0
/* Turn it back on if we need to calculate per chain antenna gain reduction */
/* Use only if the expected gain > 6dbi */
/* Chain 0 is always used */
- twiceLargestAntenna = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[0];
+ twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0];

/* Look at antenna gains of Chains 1 and 2 if the TX mask is set */
if (ahp->ah_tx_chainmask & 0x2)
twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
- pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
+ pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]);

if (ahp->ah_tx_chainmask & 0x4)
twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
- pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
+ pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
#endif
twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);

/* XXX setup for 5212 use (really used?) */
ath_hal_eepromSet(ah,
- IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5,
+ IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5,
twiceLargestAntenna);

/*
@@ -2087,10 +1382,10 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
case 1:
break;
case 2:
- scaledPower -= pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
+ scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
break;
case 3:
- scaledPower -= pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
+ scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
break;
default:
return AH_FALSE; /* Unsupported number of chains */
@@ -2099,7 +1394,7 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
scaledPower = AH_MAX(0, scaledPower);

/* Get target powers from EEPROM - our baseline for TX Power */
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
/* Setup for CTL modes */
numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
pCtlMode = ctlModesFor11g;
@@ -2111,7 +1406,7 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);

- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
@@ -2132,7 +1427,7 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,
AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);

- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */

ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40,
@@ -2152,9 +1447,8 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
*
*/
for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
-
HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
- (pCtlMode[ctlMode] == CTL_2GHT40);
+ (pCtlMode[ctlMode] == CTL_2GHT40);
if (isHt40CtlMode) {
freq = centers.ctl_center;
} else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
@@ -2174,7 +1468,7 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
rep = &(pEepData->ctlData[i]);
twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
- IS_CHAN_2GHZ(chan));
+ IEEE80211_IS_CHAN_2GHZ(chan));
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
/* Find the minimum of all CTL edge powers that apply to this channel */
twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
@@ -2235,20 +1529,20 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
}

- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ratesArray[rate1l] = targetPowerCck.tPow2x[0];
ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
}
- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
}
ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
}
}
@@ -2320,8 +1614,8 @@ ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2G
* Return the rates of target power for the given target power table
* channel, and number of channels
*/
-static void
-ar5416GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+void
+ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels,
CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates,
HAL_BOOL isHt40Target)
@@ -2336,22 +1630,22 @@ ar5416GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
freq = isHt40Target ? centers.synth_center : centers.ctl_center;

/* Copy the target powers into the temp channel list */
- if (freq <= fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
+ if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
matchIndex = 0;
} else {
for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
- if (freq == fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) {
+ if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
matchIndex = i;
break;
- } else if ((freq < fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) &&
- (freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan))))
+ } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) &&
+ (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))))
{
lowIndex = i - 1;
break;
}
}
if ((matchIndex == -1) && (lowIndex == -1)) {
- HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan)));
+ HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)));
matchIndex = i - 1;
}
}
@@ -2364,8 +1658,8 @@ ar5416GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* Get the lower and upper channels, target powers,
* and interpolate between them.
*/
- clo = fbin2freq(powInfo[lowIndex].bChannel, IS_CHAN_2GHZ(chan));
- chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IS_CHAN_2GHZ(chan));
+ clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
+ chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));

for (i = 0; i < numRates; i++) {
pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi,
@@ -2379,9 +1673,9 @@ ar5416GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* Return the four rates of target power for the given target power table
* channel, and number of channels
*/
-static void
+void
ar5416GetTargetPowersLeg(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan,
+ const struct ieee80211_channel *chan,
CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels,
CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates,
HAL_BOOL isExtTarget)
@@ -2396,22 +1690,22 @@ ar5416GetTargetPowersLeg(struct ath_hal *ah,
freq = (isExtTarget) ? centers.ext_center :centers.ctl_center;

/* Copy the target powers into the temp channel list */
- if (freq <= fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
+ if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
matchIndex = 0;
} else {
for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
- if (freq == fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) {
+ if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
matchIndex = i;
break;
- } else if ((freq < fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) &&
- (freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan))))
+ } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) &&
+ (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))))
{
lowIndex = i - 1;
break;
}
}
if ((matchIndex == -1) && (lowIndex == -1)) {
- HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan)));
+ HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)));
matchIndex = i - 1;
}
}
@@ -2424,8 +1718,8 @@ ar5416GetTargetPowersLeg(struct ath_hal *ah,
* Get the lower and upper channels, target powers,
* and interpolate between them.
*/
- clo = fbin2freq(powInfo[lowIndex].bChannel, IS_CHAN_2GHZ(chan));
- chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IS_CHAN_2GHZ(chan));
+ clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
+ chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));

for (i = 0; i < numRates; i++) {
pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi,
@@ -2442,7 +1736,8 @@ ar5416GetTargetPowersLeg(struct ath_hal *ah,
* linear voltage to power level table.
*/
static HAL_BOOL
-ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, HAL_CHANNEL_INTERNAL *chan, int16_t *pTxPowerIndexOffset)
+ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
+ const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
{
CAL_DATA_PER_FREQ *pRawDataset;
uint8_t *pCalBChans = AH_NULL;
@@ -2455,17 +1750,17 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, HAL_CH
uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
uint32_t reg32, regOffset, regChainOffset;

- ath_hal_memzero(xpdGainValues, sizeof(xpdGainValues));
+ OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));

- xpdMask = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].xpdGain;
+ xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;

if (IS_EEP_MINOR_V2(ah)) {
- pdGainOverlap_t2 = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pdGainOverlap;
+ pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
} else {
pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
}

- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
pCalBChans = pEepData->calFreqPier2G;
numPiers = AR5416_NUM_2G_CAL_PIERS;
} else {
@@ -2505,7 +1800,7 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, HAL_CH
}

if (pEepData->baseEepHeader.txMask & (1 << i)) {
- if (IS_CHAN_2GHZ(chan)) {
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
pRawDataset = pEepData->calPierData2G[i];
} else {
pRawDataset = pEepData->calPierData5G[i];
@@ -2567,7 +1862,8 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, HAL_CH
*/
static void
ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet,
+ const struct ieee80211_channel *chan,
+ CAL_DATA_PER_FREQ *pRawDataSet,
uint8_t * bChans, uint16_t availPiers,
uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
uint8_t * pPDADCValues, uint16_t numXpdGains)
@@ -2575,7 +1871,7 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,

int i, j, k;
int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
- uint16_t idxL = 0, idxR = 0, numPiers; /* Pier indexes */
+ uint16_t idxL, idxR, numPiers; /* Pier indexes */

/* filled out Vpd table for all pdGains (chanL) */
static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
@@ -2606,7 +1902,7 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
}

/* Find pier indexes around the current channel */
- match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
+ match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
bChans, numPiers, &idxL, &idxR);

if (match) {
@@ -2637,7 +1933,7 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,

/* Interpolate the final vpd */
for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
- vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
+ vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
}
}
@@ -2771,6 +2067,7 @@ getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
}
}
HALASSERT(0);
+ *indexL = *indexR = 0;
return AH_FALSE;
}

@@ -2786,7 +2083,7 @@ ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
{
uint16_t i, k;
uint8_t currPwr = pwrMin;
- uint16_t idxL = 0, idxR = 0;
+ uint16_t idxL, idxR;

HALASSERT(pwrMax > pwrMin);
for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
@@ -2830,12 +2127,12 @@ interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
}

static void
-ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan)
+ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t phymode;
HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */

- if (!IS_CHAN_HT(chan))
+ if (!IEEE80211_IS_CHAN_HT(chan))
return;

/* Enable 11n HT, 20 MHz */
@@ -2843,11 +2140,11 @@ ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan)
| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;

/* Configure baseband for dynamic 20/40 operation */
- if (IS_CHAN_HT40(chan)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40;

/* Configure control (primary) channel at +-10MHz */
- if ((chan->channelFlags & CHANNEL_HT40PLUS))
+ if (IEEE80211_IS_CHAN_HT40U(chan))
phymode |= AR_PHY_FC_DYN2040_PRI_CH;
#if 0
/* Configure 20/25 spacing */
@@ -2873,23 +2170,25 @@ ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan)

void
ar5416GetChannelCenters(struct ath_hal *ah,
- HAL_CHANNEL_INTERNAL *chan, CHAN_CENTERS *centers)
+ const struct ieee80211_channel *chan, CHAN_CENTERS *centers)
{
- centers->ctl_center = chan->channel;
- centers->synth_center = chan->channel;
+ uint16_t freq = ath_hal_gethwchannel(ah, chan);
+
+ centers->ctl_center = freq;
+ centers->synth_center = freq;
/*
* In 20/40 phy mode, the center frequency is
* "between" the control and extension channels.
*/
- if (chan->channelFlags & CHANNEL_HT40PLUS) {
+ if (IEEE80211_IS_CHAN_HT40U(chan)) {
centers->synth_center += HT40_CHANNEL_CENTER_SHIFT;
centers->ext_center =
centers->synth_center + HT40_CHANNEL_CENTER_SHIFT;
- } else if (chan->channelFlags & CHANNEL_HT40MINUS) {
+ } else if (IEEE80211_IS_CHAN_HT40D(chan)) {
centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT;
centers->ext_center =
centers->synth_center - HT40_CHANNEL_CENTER_SHIFT;
} else {
- centers->ext_center = chan->channel;
+ centers->ext_center = freq;
}
}
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_xmit.c b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_xmit.c
index 3330b31..37f36af 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416_xmit.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416_xmit.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -519,16 +519,13 @@ ar5416ProcTxDesc(struct ath_hal *ah,
ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
break;
case 1:
- ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1) |
- HAL_TXSTAT_ALTRATE;
+ ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
break;
case 2:
- ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2) |
- HAL_TXSTAT_ALTRATE;
+ ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
break;
case 3:
- ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3) |
- HAL_TXSTAT_ALTRATE;
+ ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
break;
}

diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416phy.h b/sys/external/isc/atheros_hal/dist/ar5416/ar5416phy.h
index 4967c35..d5185b6 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416phy.h
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416phy.h
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5416phy.h,v 1.1.1.1 2008/12/11 04:46:51 alc Exp $
+ * $FreeBSD$
*/
#ifndef _DEV_ATH_AR5416PHY_H_
#define _DEV_ATH_AR5416PHY_H_
@@ -48,6 +48,7 @@
#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
+#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800

#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
#define AR_PHY_TIMING2_USE_FORCE 0x00001000
@@ -78,6 +79,20 @@
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0

+#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
+#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
+#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
+#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
+#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
+#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
+#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
+#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
+
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
+
#define AR_PHY_EXT_CCA 0x99bc
#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
@@ -207,6 +222,9 @@
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20

+#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
+#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
+
#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
#define AR_PHY_MASK2_M_31_45 0xa3a4
#define AR_PHY_MASK2_M_16_30 0xa3a8
@@ -247,4 +265,5 @@

#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
#define AR_PHY_CL_CAL_ENABLE 0x00000002
+#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
#endif /* _DEV_ATH_AR5416PHY_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar5416reg.h b/sys/external/isc/atheros_hal/dist/ar5416/ar5416reg.h
index 4ee06b4..b1b626f 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar5416reg.h
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar5416reg.h
@@ -19,7 +19,7 @@
#ifndef _DEV_ATH_AR5416REG_H
#define _DEV_ATH_AR5416REG_H

-#include "ar5212/ar5212reg.h"
+#include <dev/ath/ath_hal/ar5212/ar5212reg.h>

/*
* Register added starting with the AR5416
@@ -31,7 +31,8 @@
#define AR_GTTM 0x0068 /* global transmit timeout mode */
#define AR_CST 0x006C /* carrier sense timeout */
#define AR_MAC_LED 0x1f04 /* LED control */
-#define AR5416_PCIE_PM_CTRL 0x4014
+#define AR_WA 0x4004 /* PCIE work-arounds */
+#define AR_PCIE_PM_CTRL 0x4014
#define AR_AHB_MODE 0x4024 /* AHB mode for dma */
#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */
#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */
@@ -42,8 +43,15 @@
#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */
#define AR5416_PCIE_SERDES 0x4040
#define AR5416_PCIE_SERDES2 0x4044
-#define AR_GPIO_IN 0x4048 /* GPIO input register */
-#define AR_GPIO_INTR_OUT 0x404c /* GPIO output register */
+#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */
+#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */
+#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */
+#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */
+#define AR_GPIO_INPUT_MUX1 0x4058
+#define AR_GPIO_INPUT_MUX2 0x405c
+#define AR_GPIO_OUTPUT_MUX1 0x4060
+#define AR_GPIO_OUTPUT_MUX2 0x4064
+#define AR_GPIO_OUTPUT_MUX3 0x4068
#define AR_EEPROM_STATUS_DATA 0x407c
#define AR_OBS 0x4080
#define AR_RTC_RC 0x7000 /* reset control */
@@ -62,8 +70,20 @@
#define AR_AN_RF5G1_CH1 0x783C
#define AR_AN_TOP2 0x7894
#define AR_AN_SYNTH9 0x7868
-#define AR9285_AN_RF2G3 0x7828
+#define AR9285_AN_RF2G1 0x7820
+#define AR9285_AN_RF2G2 0x7824
+#define AR9285_AN_RF2G3 0x7828
+#define AR9285_AN_RF2G4 0x782C
+#define AR9285_AN_RF2G6 0x7834
+#define AR9285_AN_RF2G7 0x7838
+#define AR9285_AN_RF2G8 0x783C
+#define AR9285_AN_RF2G9 0x7840
+#define AR9285_AN_RXTXBB1 0x7854
+#define AR9285_AN_TOP2 0x7868
#define AR9285_AN_TOP3 0x786c
+#define AR9285_AN_TOP4 0x7870
+#define AR9285_AN_TOP4_DEFAULT 0x10142c00
+
#define AR_RESET_TSF 0x8020
#define AR_RXFIFO_CFG 0x8114
#define AR_PHY_ERR_1 0x812c
@@ -179,6 +199,17 @@
#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */
#define AR_MAC_LED_ASSOC_S 10

+#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */
+#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */
+#define AR_WA_ANALOG_SHIFT 0x00100000
+#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */
+
+#define AR_WA_DEFAULT 0x0000073f
+#define AR9280_WA_DEFAULT 0x0040073f
+#define AR9285_WA_DEFAULT 0x004a05cb
+
+#define AR_PCIE_PM_CTRL_ENA 0x00080000
+
#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */
#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/
#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */
@@ -258,6 +289,21 @@
AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \
AR_INTR_SYNC_MAC_SLEEP_ACCESS)

+#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
+#define AR_INTR_SYNC_MASK_GPIO_S 18
+
+#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
+#define AR_INTR_SYNC_ENABLE_GPIO_S 18
+
+#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */
+#define AR_INTR_ASYNC_MASK_GPIO_S 18
+
+#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */
+#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO)
+
+#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */
+#define AR_INTR_ASYNC_ENABLE_GPIO_S 18
+
/* RTC registers */
#define AR_RTC_RC_M 0x00000003
#define AR_RTC_RC_MAC_WARM 0x00000001
@@ -325,42 +371,83 @@
#define AR_AN_SYNTH9_REFDIVA_S 27

/* AR9285 Analog registers */
-#define AR9285_AN_RF2G3_OB_0 0x00E00000
-#define AR9285_AN_RF2G3_OB_0_S 21
-#define AR9285_AN_RF2G3_OB_1 0x001C0000
-#define AR9285_AN_RF2G3_OB_1_S 18
-#define AR9285_AN_RF2G3_OB_2 0x00038000
-#define AR9285_AN_RF2G3_OB_2_S 15
-#define AR9285_AN_RF2G3_OB_3 0x00007000
-#define AR9285_AN_RF2G3_OB_3_S 12
-#define AR9285_AN_RF2G3_OB_4 0x00000E00
-#define AR9285_AN_RF2G3_OB_4_S 9
-
-#define AR9285_AN_RF2G3_DB1_0 0x000001C0
-#define AR9285_AN_RF2G3_DB1_0_S 6
-#define AR9285_AN_RF2G3_DB1_1 0x00000038
-#define AR9285_AN_RF2G3_DB1_1_S 3
-#define AR9285_AN_RF2G3_DB1_2 0x00000007
-#define AR9285_AN_RF2G3_DB1_2_S 0
-#define AR9285_AN_RF2G4 0x782C
-#define AR9285_AN_RF2G4_DB1_3 0xE0000000
-#define AR9285_AN_RF2G4_DB1_3_S 29
-#define AR9285_AN_RF2G4_DB1_4 0x1C000000
-#define AR9285_AN_RF2G4_DB1_4_S 26
-
-#define AR9285_AN_RF2G4_DB2_0 0x03800000
-#define AR9285_AN_RF2G4_DB2_0_S 23
-#define AR9285_AN_RF2G4_DB2_1 0x00700000
-#define AR9285_AN_RF2G4_DB2_1_S 20
-#define AR9285_AN_RF2G4_DB2_2 0x000E0000
-#define AR9285_AN_RF2G4_DB2_2_S 17
-#define AR9285_AN_RF2G4_DB2_3 0x0001C000
-#define AR9285_AN_RF2G4_DB2_3_S 14
-#define AR9285_AN_RF2G4_DB2_4 0x00003800
-#define AR9285_AN_RF2G4_DB2_4_S 11
+#define AR9285_AN_RF2G1_ENPACAL 0x00000800
+#define AR9285_AN_RF2G1_ENPACAL_S 11
+#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
+#define AR9285_AN_RF2G1_PDPADRV1_S 25
+#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
+#define AR9285_AN_RF2G1_PDPADRV2_S 24
+#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
+#define AR9285_AN_RF2G1_PDPAOUT_S 23
+
+#define AR9285_AN_RF2G2_OFFCAL 0x00001000
+#define AR9285_AN_RF2G2_OFFCAL_S 12
+
+#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
+#define AR9285_AN_RF2G3_PDVCCOMP_S 25
+#define AR9285_AN_RF2G3_OB_0 0x00E00000
+#define AR9285_AN_RF2G3_OB_0_S 21
+#define AR9285_AN_RF2G3_OB_1 0x001C0000
+#define AR9285_AN_RF2G3_OB_1_S 18
+#define AR9285_AN_RF2G3_OB_2 0x00038000
+#define AR9285_AN_RF2G3_OB_2_S 15
+#define AR9285_AN_RF2G3_OB_3 0x00007000
+#define AR9285_AN_RF2G3_OB_3_S 12
+#define AR9285_AN_RF2G3_OB_4 0x00000E00
+#define AR9285_AN_RF2G3_OB_4_S 9
+
+#define AR9285_AN_RF2G3_DB1_0 0x000001C0
+#define AR9285_AN_RF2G3_DB1_0_S 6
+#define AR9285_AN_RF2G3_DB1_1 0x00000038
+#define AR9285_AN_RF2G3_DB1_1_S 3
+#define AR9285_AN_RF2G3_DB1_2 0x00000007
+#define AR9285_AN_RF2G3_DB1_2_S 0
+
+#define AR9285_AN_RF2G4_DB1_3 0xE0000000
+#define AR9285_AN_RF2G4_DB1_3_S 29
+#define AR9285_AN_RF2G4_DB1_4 0x1C000000
+#define AR9285_AN_RF2G4_DB1_4_S 26
+
+#define AR9285_AN_RF2G4_DB2_0 0x03800000
+#define AR9285_AN_RF2G4_DB2_0_S 23
+#define AR9285_AN_RF2G4_DB2_1 0x00700000
+#define AR9285_AN_RF2G4_DB2_1_S 20
+#define AR9285_AN_RF2G4_DB2_2 0x000E0000
+#define AR9285_AN_RF2G4_DB2_2_S 17
+#define AR9285_AN_RF2G4_DB2_3 0x0001C000
+#define AR9285_AN_RF2G4_DB2_3_S 14
+#define AR9285_AN_RF2G4_DB2_4 0x00003800
+#define AR9285_AN_RF2G4_DB2_4_S 11
+
+#define AR9285_AN_RF2G6_CCOMP 0x00007800
+#define AR9285_AN_RF2G6_CCOMP_S 11
+#define AR9285_AN_RF2G6_OFFS 0x03f00000
+#define AR9285_AN_RF2G6_OFFS_S 20
+
+#define AR9271_AN_RF2G6_OFFS 0x07f00000
+#define AR9271_AN_RF2G6_OFFS_S 20
+
+#define AR9285_AN_RF2G7_PWDDB 0x00000002
+#define AR9285_AN_RF2G7_PWDDB_S 1
+#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
+#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
+
+#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
+#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
+
+#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
+#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
+#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
+#define AR9285_AN_RXTXBB1_PDV2I_S 7
+#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
+#define AR9285_AN_RXTXBB1_PDDACIF_S 8
+#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
+#define AR9285_AN_RXTXBB1_SPARE9_S 0

#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
+#define AR9285_AN_TOP3_PWDDAC 0x00800000
+#define AR9285_AN_TOP3_PWDDAC_S 23

/* Sleep control */
#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */
@@ -418,10 +505,27 @@
#define AR_GPIO_INTR_CTRL 0x3FF00000
#define AR_GPIO_INTR_CTRL_S 20

+#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */
+#define AR_GPIO_IN_VAL_S 14
+#define AR928X_GPIO_IN_VAL 0x000FFC00
+#define AR928X_GPIO_IN_VAL_S 10
+#define AR9285_GPIO_IN_VAL 0x00FFF000
+#define AR9285_GPIO_IN_VAL_S 12
+
+#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */
+#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */
+#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */
+#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */
+#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */
+
+#define AR_GPIO_INTR_POL_VAL 0x1FFF
+#define AR_GPIO_INTR_POL_VAL_S 0
+
#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */

#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
+#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380

/* Eeprom defines */
#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
@@ -472,6 +576,8 @@
#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */
#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */
#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */
+#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */
+#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */

#define AR_SREV_OWL_20_OR_LATER(_ah) \
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
@@ -494,7 +600,7 @@
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
#define AR_SREV_MERLIN_20(_ah) \
(AR_SREV_MERLIN(_ah) && \
- AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
+ AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20)
#define AR_SREV_MERLIN_20_OR_LATER(_ah) \
(AR_SREV_MERLIN_20(_ah) || \
AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)
@@ -503,4 +609,16 @@
(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
#define AR_SREV_KITE_10_OR_LATER(_ah) \
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
+#define AR_SREV_KITE_11(_ah) \
+ (AR_SREV_KITE(ah) && \
+ AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11)
+#define AR_SREV_KITE_11_OR_LATER(_ah) \
+ (AR_SREV_KITE_11(_ah) || \
+ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)
+#define AR_SREV_KITE_12(_ah) \
+ (AR_SREV_KITE(ah) && \
+ AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12)
+#define AR_SREV_KITE_12_OR_LATER(_ah) \
+ (AR_SREV_KITE_12(_ah) || \
+ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)
#endif /* _DEV_ATH_AR5416REG_H */
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9160.ini b/sys/external/isc/atheros_hal/dist/ar5416/ar9160.ini
old mode 100755
new mode 100644
index ae4fbd3..275aa48
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar9160.ini
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9160.ini
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar9160.ini,v 1.1.1.1 2008/12/11 04:46:51 alc Exp $
+ * $FreeBSD$
*/
/* Auto Generated PCI Register Writes. Created: 05/22/08 */

@@ -697,3 +697,17 @@ static const uint32_t ar9160Addac_1_1[][2] = {
{0x0000989c, 0x00000000 },
{0x000098cc, 0x00000000 },
};
+
+/* hand-crafted from code that does explicit register writes */
+static const uint32_t ar9160PciePhy[][2] = {
+ { AR_PCIE_SERDES, 0x9248fc00 },
+ { AR_PCIE_SERDES, 0x24924924 },
+ { AR_PCIE_SERDES, 0x28000039 },
+ { AR_PCIE_SERDES, 0x53160824 },
+ { AR_PCIE_SERDES, 0xe5980579 },
+ { AR_PCIE_SERDES, 0x001defff },
+ { AR_PCIE_SERDES, 0x1aaabe40 },
+ { AR_PCIE_SERDES, 0xbe105554 },
+ { AR_PCIE_SERDES, 0x000e3007 },
+ { AR_PCIE_SERDES2, 0x00000000 },
+};
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9160_attach.c b/sys/external/isc/atheros_hal/dist/ar5416/ar9160_attach.c
index 473a699..1d75ed1 100644
--- a/sys/external/isc/atheros_hal/dist/ar5416/ar9160_attach.c
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9160_attach.c
@@ -57,9 +57,6 @@ static const HAL_PERCAL_DATA ar9160_adc_init_dc_cal = {
.calPostProc = ar5416AdcDcCalibration
};

-struct ath_hal *ar9160Attach(uint16_t devid, HAL_SOFTC sc,
- HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
-static void ar9160Detach(struct ath_hal *);
static HAL_BOOL ar9160FillCapabilityInfo(struct ath_hal *ah);

static void
@@ -90,7 +87,7 @@ ar9160AniSetup(struct ath_hal *ah)
/*
* Attach for an AR9160 part.
*/
-struct ath_hal *
+static struct ath_hal *
ar9160Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
{
@@ -118,7 +115,6 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,

/* XXX override with 9160 specific state */
/* override 5416 methods for our needs */
- ah->ah_detach = ar9160Detach;

AH5416(ah)->ah_cal.iqCalData.calData = &ar9160_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9160_adc_gain_cal;
@@ -150,7 +146,7 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
AH_PRIVATE(ah)->ah_macVersion =
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
- /* XXX extract pcie info */
+ AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;

/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar9160Modes, 6);
@@ -168,6 +164,13 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
else
HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac, 2);

+ ecode = ath_hal_v14EepromAttach(ah);
+ if (ecode != HAL_OK)
+ goto bad;
+
+ HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar9160PciePhy, 2);
+ ar5416AttachPCIE(ah);
+
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
@@ -190,7 +193,7 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);

/* Read Radio Chip Rev Extract */
- AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+ AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
@@ -210,8 +213,6 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
goto bad;
#endif
}
- HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: Attaching AR2133 radio\n",
- __func__);
rfStatus = ar2133RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
@@ -219,10 +220,6 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
goto bad;
}

- ecode = ath_hal_v14EepromAttach(ah);
- if (ecode != HAL_OK)
- goto bad;
-
/*
* Got everything we need now to setup the capabilities.
*/
@@ -259,23 +256,12 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
return ah;
bad:
if (ahp)
- ar9160Detach((struct ath_hal *) ahp);
+ ar5416Detach((struct ath_hal *) ahp);
if (status)
*status = ecode;
return AH_NULL;
}

-void
-ar9160Detach(struct ath_hal *ah)
-{
- HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
-
- HALASSERT(ah != AH_NULL);
- HALASSERT(ah->ah_magic == AR5416_MAGIC);
-
- ar5416Detach(ah);
-}
-
/*
* Fill all software cached or static hardware state information.
* Return failure if capabilities are to come from EEPROM and
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9280.c b/sys/external/isc/atheros_hal/dist/ar5416/ar9280.c
new file mode 100644
index 0000000..72720f7
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9280.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+
+/*
+ * NB: Merlin and later have a simpler RF backend.
+ */
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v14.h"
+
+#include "ar5416/ar9280.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#define N(a) (sizeof(a)/sizeof(a[0]))
+
+struct ar9280State {
+ RF_HAL_FUNCS base; /* public state, must be first */
+ uint16_t pcdacTable[1]; /* XXX */
+};
+#define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal)
+
+static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *,
+ const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow);
+int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
+
+static void
+ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+ int writes)
+{
+ (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
+ freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ *
+ * Actual Expression,
+ *
+ * For 2GHz channel,
+ * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
+ * (freq_ref = 40MHz)
+ *
+ * For 5GHz channel,
+ * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
+ * (freq_ref = 40MHz/(24>>amodeRefSel))
+ *
+ * For 5GHz channels which are 5MHz spaced,
+ * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
+ * (freq_ref = 40MHz)
+ */
+static HAL_BOOL
+ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ uint16_t bMode, fracMode, aModeRefSel = 0;
+ uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
+ CHAN_CENTERS centers;
+ uint32_t refDivA = 24;
+
+ OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
+
+ ar5416GetChannelCenters(ah, chan, &centers);
+ freq = centers.synth_center;
+
+ reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
+ reg32 &= 0xc0000000;
+
+ if (freq < 4800) { /* 2 GHz, fractional mode */
+ uint32_t txctl;
+
+ bMode = 1;
+ fracMode = 1;
+ aModeRefSel = 0;
+ channelSel = (freq * 0x10000)/15;
+
+ txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+ if (freq == 2484) {
+ /* Enable channel spreading for channel 14 */
+ OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+ txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+ } else {
+ OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+ txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+ }
+ } else {
+ bMode = 0;
+ fracMode = 0;
+
+ if ((freq % 20) == 0) {
+ aModeRefSel = 3;
+ } else if ((freq % 10) == 0) {
+ aModeRefSel = 2;
+ } else {
+ aModeRefSel = 0;
+ /* Enable 2G (fractional) mode for channels which are 5MHz spaced */
+ fracMode = 1;
+ refDivA = 1;
+ channelSel = (freq * 0x8000)/15;
+
+ /* RefDivA setting */
+ OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
+ AR_AN_SYNTH9_REFDIVA, refDivA);
+ }
+ if (!fracMode) {
+ ndiv = (freq * (refDivA >> aModeRefSel))/60;
+ channelSel = ndiv & 0x1ff;
+ channelFrac = (ndiv & 0xfffffe00) * 2;
+ channelSel = (channelSel << 17) | channelFrac;
+ }
+ }
+
+ reg32 = reg32 | (bMode << 29) | (fracMode << 28) |
+ (aModeRefSel << 26) | (channelSel);
+
+ OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
+
+ AH_PRIVATE(ah)->ah_curchan = chan;
+
+ return AH_TRUE;
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar9280GetRfBank(struct ath_hal *ah, int bank)
+{
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+ __func__, bank);
+ return AH_NULL;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ */
+static HAL_BOOL
+ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
+ uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+ return AH_TRUE; /* nothing to do */
+}
+
+/*
+ * Read the transmit power levels from the structures taken from EEPROM
+ * Interpolate read transmit power values for this channel
+ * Organize the transmit power values into a table for writing into the hardware
+ */
+
+static HAL_BOOL
+ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
+{
+ return AH_TRUE;
+}
+
+#if 0
+static int16_t
+ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
+{
+ int i, minIndex;
+ int16_t minGain,minPwr,minPcdac,retVal;
+
+ /* Assume NUM_POINTS_XPD0 > 0 */
+ minGain = data->pDataPerXPD[0].xpd_gain;
+ for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
+ if (data->pDataPerXPD[i].xpd_gain < minGain) {
+ minIndex = i;
+ minGain = data->pDataPerXPD[i].xpd_gain;
+ }
+ }
+ minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
+ minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
+ for (i=1; i<NUM_POINTS_XPD0; i++) {
+ if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
+ minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
+ minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
+ }
+ }
+ retVal = minPwr - (minPcdac*2);
+ return(retVal);
+}
+#endif
+
+static HAL_BOOL
+ar9280GetChannelMaxMinPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ int16_t *maxPow, int16_t *minPow)
+{
+#if 0
+ struct ath_hal_5212 *ahp = AH5212(ah);
+ int numChannels=0,i,last;
+ int totalD, totalF,totalMin;
+ EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
+ EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
+
+ *maxPow = 0;
+ if (IS_CHAN_A(chan)) {
+ powerArray = ahp->ah_modePowerArray5112;
+ data = powerArray[headerInfo11A].pDataPerChannel;
+ numChannels = powerArray[headerInfo11A].numChannels;
+ } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
+ /* XXX - is this correct? Should we also use the same power for turbo G? */
+ powerArray = ahp->ah_modePowerArray5112;
+ data = powerArray[headerInfo11G].pDataPerChannel;
+ numChannels = powerArray[headerInfo11G].numChannels;
+ } else if (IS_CHAN_B(chan)) {
+ powerArray = ahp->ah_modePowerArray5112;
+ data = powerArray[headerInfo11B].pDataPerChannel;
+ numChannels = powerArray[headerInfo11B].numChannels;
+ } else {
+ return (AH_TRUE);
+ }
+ /* Make sure the channel is in the range of the TP values
+ * (freq piers)
+ */
+ if ((numChannels < 1) ||
+ (chan->channel < data[0].channelValue) ||
+ (chan->channel > data[numChannels-1].channelValue))
+ return(AH_FALSE);
+
+ /* Linearly interpolate the power value now */
+ for (last=0,i=0;
+ (i<numChannels) && (chan->channel > data[i].channelValue);
+ last=i++);
+ totalD = data[i].channelValue - data[last].channelValue;
+ if (totalD > 0) {
+ totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
+ *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
+
+ totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]);
+ *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD);
+ return (AH_TRUE);
+ } else {
+ if (chan->channel == data[i].channelValue) {
+ *maxPow = data[i].maxPower_t4;
+ *minPow = ar9280GetMinPower(ah, &data[i]);
+ return(AH_TRUE);
+ } else
+ return(AH_FALSE);
+ }
+#else
+ *maxPow = *minPow = 0;
+ return AH_FALSE;
+#endif
+}
+
+static void
+ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
+{
+ int16_t nf;
+
+ nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
+ if (nf & 0x100)
+ nf = 0 - ((nf ^ 0x1ff) + 1);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "NF calibrated [ctl] [chain 0] is %d\n", nf);
+ nfarray[0] = nf;
+
+ nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
+ if (nf & 0x100)
+ nf = 0 - ((nf ^ 0x1ff) + 1);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "NF calibrated [ctl] [chain 1] is %d\n", nf);
+ nfarray[1] = nf;
+
+ nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
+ if (nf & 0x100)
+ nf = 0 - ((nf ^ 0x1ff) + 1);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "NF calibrated [ext] [chain 0] is %d\n", nf);
+ nfarray[3] = nf;
+
+ nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
+ if (nf & 0x100)
+ nf = 0 - ((nf ^ 0x1ff) + 1);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "NF calibrated [ext] [chain 1] is %d\n", nf);
+ nfarray[4] = nf;
+}
+
+/*
+ * Adjust NF based on statistical values for 5GHz frequencies.
+ * Stubbed:Not used by Fowl
+ */
+int16_t
+ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
+{
+ return 0;
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar9280RfDetach(struct ath_hal *ah)
+{
+ struct ath_hal_5212 *ahp = AH5212(ah);
+
+ HALASSERT(ahp->ah_rfHal != AH_NULL);
+ ath_hal_free(ahp->ah_rfHal);
+ ahp->ah_rfHal = AH_NULL;
+}
+
+HAL_BOOL
+ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+ struct ath_hal_5212 *ahp = AH5212(ah);
+ struct ar9280State *priv;
+
+ HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);
+
+ HALASSERT(ahp->ah_rfHal == AH_NULL);
+ priv = ath_hal_malloc(sizeof(struct ar9280State));
+ if (priv == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: cannot allocate private state\n", __func__);
+ *status = HAL_ENOMEM; /* XXX */
+ return AH_FALSE;
+ }
+ priv->base.rfDetach = ar9280RfDetach;
+ priv->base.writeRegs = ar9280WriteRegs;
+ priv->base.getRfBank = ar9280GetRfBank;
+ priv->base.setChannel = ar9280SetChannel;
+ priv->base.setRfRegs = ar9280SetRfRegs;
+ priv->base.setPowerTable = ar9280SetPowerTable;
+ priv->base.getChannelMaxMinPower = ar9280GetChannelMaxMinPower;
+ priv->base.getNfAdjust = ar9280GetNfAdjust;
+
+ ahp->ah_pcdacTable = priv->pcdacTable;
+ ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+ ahp->ah_rfHal = &priv->base;
+ /*
+ * Set noise floor adjust method; we arrange a
+ * direct call instead of thunking.
+ */
+ AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
+ AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor;
+
+ return AH_TRUE;
+}
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9280.h b/sys/external/isc/atheros_hal/dist/ar5416/ar9280.h
new file mode 100644
index 0000000..59039f0
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9280.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#ifndef _ATH_AR9280_H_
+#define _ATH_AR9280_H_
+
+#include "ar5416/ar5416.h"
+
+struct ath_hal_9280 {
+ struct ath_hal_5416 ah_5416;
+
+ HAL_INI_ARRAY ah_ini_xmodes;
+ HAL_INI_ARRAY ah_ini_rxgain;
+ HAL_INI_ARRAY ah_ini_txgain;
+};
+#define AH9280(_ah) ((struct ath_hal_9280 *)(_ah))
+
+#define AR9280_DEFAULT_RXCHAINMASK 3
+#define AR9285_DEFAULT_RXCHAINMASK 1
+#define AR9280_DEFAULT_TXCHAINMASK 1
+#define AR9285_DEFAULT_TXCHAINMASK 1
+
+HAL_BOOL ar9280RfAttach(struct ath_hal *, HAL_STATUS *);
+
+struct ath_hal;
+
+HAL_BOOL ar9280SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
+void ar9280SpurMitigate(struct ath_hal *,
+ const struct ieee80211_channel *);
+
+#endif /* _ATH_AR9280_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9280_attach.c b/sys/external/isc/atheros_hal/dist/ar5416/ar9280_attach.c
new file mode 100644
index 0000000..8436482
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9280_attach.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */
+
+#include "ar5416/ar9280.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#include "ar5416/ar9280v1.ini"
+#include "ar5416/ar9280v2.ini"
+
+static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
+ .calName = "IQ", .calType = IQ_MISMATCH_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = PER_MAX_LOG_COUNT,
+ .calCollect = ar5416IQCalCollect,
+ .calPostProc = ar5416IQCalibration
+};
+static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
+ .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = PER_MIN_LOG_COUNT,
+ .calCollect = ar5416AdcGainCalCollect,
+ .calPostProc = ar5416AdcGainCalibration
+};
+static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
+ .calName = "ADC DC", .calType = ADC_DC_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = PER_MIN_LOG_COUNT,
+ .calCollect = ar5416AdcDcCalCollect,
+ .calPostProc = ar5416AdcDcCalibration
+};
+static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
+ .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = INIT_LOG_COUNT,
+ .calCollect = ar5416AdcDcCalCollect,
+ .calPostProc = ar5416AdcDcCalibration
+};
+
+static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
+static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah);
+static void ar9280WriteIni(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
+
+static void
+ar9280AniSetup(struct ath_hal *ah)
+{
+ /* NB: disable ANI for reliable RIFS rx */
+ ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
+}
+
+/*
+ * Attach for an AR9280 part.
+ */
+static struct ath_hal *
+ar9280Attach(uint16_t devid, HAL_SOFTC sc,
+ HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+ struct ath_hal_9280 *ahp9280;
+ struct ath_hal_5212 *ahp;
+ struct ath_hal *ah;
+ uint32_t val;
+ HAL_STATUS ecode;
+ HAL_BOOL rfStatus;
+
+ HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+ __func__, sc, (void*) st, (void*) sh);
+
+ /* NB: memory is returned zero'd */
+ ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));
+ if (ahp9280 == AH_NULL) {
+ HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+ "%s: cannot allocate memory for state block\n", __func__);
+ *status = HAL_ENOMEM;
+ return AH_NULL;
+ }
+ ahp = AH5212(ahp9280);
+ ah = &ahp->ah_priv.h;
+
+ ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
+
+ /* XXX override with 9280 specific state */
+ /* override 5416 methods for our needs */
+ ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;
+ ah->ah_configPCIE = ar9280ConfigPCIE;
+
+ AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
+ AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
+ AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
+ AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
+ AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
+
+ AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
+ AH5416(ah)->ah_writeIni = ar9280WriteIni;
+ AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
+ AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
+
+ if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
+ /* reset chip */
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
+ __func__);
+ ecode = HAL_EIO;
+ goto bad;
+ }
+
+ if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
+ __func__);
+ ecode = HAL_EIO;
+ goto bad;
+ }
+ /* Read Revisions from Chips before taking out of reset */
+ val = OS_REG_READ(ah, AR_SREV);
+ HALDEBUG(ah, HAL_DEBUG_ATTACH,
+ "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
+ __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
+ MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
+ /* NB: include chip type to differentiate from pre-Sowl versions */
+ AH_PRIVATE(ah)->ah_macVersion =
+ (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
+ AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
+ AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
+
+ /* setup common ini data; rf backends handle remainder */
+ if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
+ HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
+ HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
+ ar9280PciePhy_clkreq_always_on_L1_v2, 2);
+ HAL_INI_INIT(&ahp9280->ah_ini_xmodes,
+ ar9280Modes_fast_clock_v2, 3);
+ } else {
+ HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);
+ HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);
+ HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
+ ar9280PciePhy_v1, 2);
+ }
+ ar5416AttachPCIE(ah);
+
+ ecode = ath_hal_v14EepromAttach(ah);
+ if (ecode != HAL_OK)
+ goto bad;
+
+ if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+ ecode = HAL_EIO;
+ goto bad;
+ }
+
+ AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+ if (!ar5212ChipTest(ah)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+ __func__);
+ ecode = HAL_ESELFTEST;
+ goto bad;
+ }
+
+ /*
+ * Set correct Baseband to analog shift
+ * setting to access analog chips.
+ */
+ OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+ /* Read Radio Chip Rev Extract */
+ AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
+ switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+ case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
+ case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
+ break;
+ default:
+ if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
+ AH_PRIVATE(ah)->ah_analog5GhzRev =
+ AR_RAD5133_SREV_MAJOR;
+ break;
+ }
+#ifdef AH_DEBUG
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: 5G Radio Chip Rev 0x%02X is not supported by "
+ "this driver\n", __func__,
+ AH_PRIVATE(ah)->ah_analog5GhzRev);
+ ecode = HAL_ENOTSUPP;
+ goto bad;
+#endif
+ }
+ rfStatus = ar9280RfAttach(ah, &ecode);
+ if (!rfStatus) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+ __func__, ecode);
+ goto bad;
+ }
+
+ if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ /* setup rxgain table */
+ switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {
+ case AR5416_EEP_RXGAIN_13dB_BACKOFF:
+ HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
+ ar9280Modes_backoff_13db_rxgain_v2, 6);
+ break;
+ case AR5416_EEP_RXGAIN_23dB_BACKOFF:
+ HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
+ ar9280Modes_backoff_23db_rxgain_v2, 6);
+ break;
+ case AR5416_EEP_RXGAIN_ORIG:
+ HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
+ ar9280Modes_original_rxgain_v2, 6);
+ break;
+ default:
+ HALASSERT(AH_FALSE);
+ goto bad; /* XXX ? try to continue */
+ }
+ }
+ if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ /* setp txgain table */
+ switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
+ case AR5416_EEP_TXGAIN_HIGH_POWER:
+ HAL_INI_INIT(&ahp9280->ah_ini_txgain,
+ ar9280Modes_high_power_tx_gain_v2, 6);
+ break;
+ case AR5416_EEP_TXGAIN_ORIG:
+ HAL_INI_INIT(&ahp9280->ah_ini_txgain,
+ ar9280Modes_original_tx_gain_v2, 6);
+ break;
+ default:
+ HALASSERT(AH_FALSE);
+ goto bad; /* XXX ? try to continue */
+ }
+ }
+
+ /*
+ * Got everything we need now to setup the capabilities.
+ */
+ if (!ar9280FillCapabilityInfo(ah)) {
+ ecode = HAL_EEREAD;
+ goto bad;
+ }
+
+ ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+ if (ecode != HAL_OK) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: error getting mac address from EEPROM\n", __func__);
+ goto bad;
+ }
+ /* XXX How about the serial number ? */
+ /* Read Reg Domain */
+ AH_PRIVATE(ah)->ah_currentRD =
+ ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
+
+ /*
+ * ah_miscMode is populated by ar5416FillCapabilityInfo()
+ * starting from griffin. Set here to make sure that
+ * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
+ * placed into hardware.
+ */
+ if (ahp->ah_miscMode != 0)
+ OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+
+ ar9280AniSetup(ah); /* Anti Noise Immunity */
+ ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
+
+ HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+ return ah;
+bad:
+ if (ah != AH_NULL)
+ ah->ah_detach(ah);
+ if (status)
+ *status = ecode;
+ return AH_NULL;
+}
+
+static void
+ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
+{
+ if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
+ ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
+ OS_DELAY(1000);
+ OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+ OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
+ }
+}
+
+static void
+ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ u_int modesIndex, freqIndex;
+ int regWrites = 0;
+
+ /* Setup the indices for the next set of register array writes */
+ /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
+ freqIndex = 2;
+ if (IEEE80211_IS_CHAN_HT40(chan))
+ modesIndex = 3;
+ else if (IEEE80211_IS_CHAN_108G(chan))
+ modesIndex = 5;
+ else
+ modesIndex = 4;
+ } else {
+ freqIndex = 1;
+ if (IEEE80211_IS_CHAN_HT40(chan) ||
+ IEEE80211_IS_CHAN_TURBO(chan))
+ modesIndex = 2;
+ else
+ modesIndex = 1;
+ }
+
+ /* Set correct Baseband to analog shift setting to access analog chips. */
+ OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+ OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
+
+ /* XXX Merlin ini fixups */
+ /* XXX Merlin 100us delay for shift registers */
+ regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
+ modesIndex, regWrites);
+ if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
+ modesIndex, regWrites);
+ regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
+ modesIndex, regWrites);
+ }
+ /* XXX Merlin 100us delay for shift registers */
+ regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
+ 1, regWrites);
+
+ if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
+ /* 5GHz channels w/ Fast Clock use different modal values */
+ regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
+ modesIndex, regWrites);
+ }
+}
+
+#define AR_BASE_FREQ_2GHZ 2300
+#define AR_BASE_FREQ_5GHZ 4900
+#define AR_SPUR_FEEQ_BOUND_HT40 19
+#define AR_SPUR_FEEQ_BOUND_HT20 10
+
+void
+ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
+ AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
+ static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
+ AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
+ static int inc[4] = { 0, 100, 0, 0 };
+
+ int bb_spur = AR_NO_SPUR;
+ int freq;
+ int bin, cur_bin;
+ int bb_spur_off, spur_subchannel_sd;
+ int spur_freq_sd;
+ int spur_delta_phase;
+ int denominator;
+ int upper, lower, cur_vit_mask;
+ int tmp, newVal;
+ int i;
+ CHAN_CENTERS centers;
+
+ int8_t mask_m[123];
+ int8_t mask_p[123];
+ int8_t mask_amt;
+ int tmp_mask;
+ int cur_bb_spur;
+ HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
+
+ OS_MEMZERO(&mask_m, sizeof(int8_t) * 123);
+ OS_MEMZERO(&mask_p, sizeof(int8_t) * 123);
+
+ ar5416GetChannelCenters(ah, chan, &centers);
+ freq = centers.synth_center;
+
+ /*
+ * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40,
+ * otherwise spur is out-of-band and can be ignored.
+ */
+ for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+ cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
+ /* Get actual spur freq in MHz from EEPROM read value */
+ if (is2GHz) {
+ cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
+ } else {
+ cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
+ }
+
+ if (AR_NO_SPUR == cur_bb_spur)
+ break;
+ cur_bb_spur = cur_bb_spur - freq;
+
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
+ (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
+ bb_spur = cur_bb_spur;
+ break;
+ }
+ } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
+ (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
+ bb_spur = cur_bb_spur;
+ break;
+ }
+ }
+
+ if (AR_NO_SPUR == bb_spur) {
+#if 1
+ /*
+ * MRC CCK can interfere with beacon detection and cause deaf/mute.
+ * Disable MRC CCK for now.
+ */
+ OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+#else
+ /* Enable MRC CCK if no spur is found in this channel. */
+ OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+#endif
+ return;
+ } else {
+ /*
+ * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur
+ * is found in this channel.
+ */
+ OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+ }
+
+ bin = bb_spur * 320;
+
+ tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
+
+ newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+ AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+ AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+ AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+ OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
+
+ newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+ AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+ AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+ AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+ SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
+ OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
+
+ /* Pick control or extn channel to cancel the spur */
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ if (bb_spur < 0) {
+ spur_subchannel_sd = 1;
+ bb_spur_off = bb_spur + 10;
+ } else {
+ spur_subchannel_sd = 0;
+ bb_spur_off = bb_spur - 10;
+ }
+ } else {
+ spur_subchannel_sd = 0;
+ bb_spur_off = bb_spur;
+ }
+
+ /*
+ * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
+ * /80 for dyn2040.
+ */
+ if (IEEE80211_IS_CHAN_HT40(chan))
+ spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
+ else
+ spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
+
+ /*
+ * in 11A mode the denominator of spur_freq_sd should be 40 and
+ * it should be 44 in 11G
+ */
+ denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40;
+ spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
+
+ newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+ SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
+ SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
+ OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
+
+ /* Choose to cancel between control and extension channels */
+ newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
+ OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
+
+ /*
+ * ============================================
+ * Set Pilot and Channel Masks
+ *
+ * pilot mask 1 [31:0] = +6..-26, no 0 bin
+ * pilot mask 2 [19:0] = +26..+7
+ *
+ * channel mask 1 [31:0] = +6..-26, no 0 bin
+ * channel mask 2 [19:0] = +26..+7
+ */
+ cur_bin = -6000;
+ upper = bin + 100;
+ lower = bin - 100;
+
+ for (i = 0; i < 4; i++) {
+ int pilot_mask = 0;
+ int chan_mask = 0;
+ int bp = 0;
+ for (bp = 0; bp < 30; bp++) {
+ if ((cur_bin > lower) && (cur_bin < upper)) {
+ pilot_mask = pilot_mask | 0x1 << bp;
+ chan_mask = chan_mask | 0x1 << bp;
+ }
+ cur_bin += 100;
+ }
+ cur_bin += inc[i];
+ OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
+ OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
+ }
+
+ /* =================================================
+ * viterbi mask 1 based on channel magnitude
+ * four levels 0-3
+ * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
+ * [1 2 2 1] for -9.6 or [1 2 1] for +16
+ * - enable_mask_ppm, all bins move with freq
+ *
+ * - mask_select, 8 bits for rates (reg 67,0x990c)
+ * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
+ * choose which mask to use mask or mask2
+ */
+
+ /*
+ * viterbi mask 2 2nd set for per data rate puncturing
+ * four levels 0-3
+ * - mask_select, 8 bits for rates (reg 67)
+ * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
+ * [1 2 2 1] for -9.6 or [1 2 1] for +16
+ */
+ cur_vit_mask = 6100;
+ upper = bin + 120;
+ lower = bin - 120;
+
+ for (i = 0; i < 123; i++) {
+ if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
+ if ((abs(cur_vit_mask - bin)) < 75) {
+ mask_amt = 1;
+ } else {
+ mask_amt = 0;
+ }
+ if (cur_vit_mask < 0) {
+ mask_m[abs(cur_vit_mask / 100)] = mask_amt;
+ } else {
+ mask_p[cur_vit_mask / 100] = mask_amt;
+ }
+ }
+ cur_vit_mask -= 100;
+ }
+
+ tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
+ | (mask_m[48] << 26) | (mask_m[49] << 24)
+ | (mask_m[50] << 22) | (mask_m[51] << 20)
+ | (mask_m[52] << 18) | (mask_m[53] << 16)
+ | (mask_m[54] << 14) | (mask_m[55] << 12)
+ | (mask_m[56] << 10) | (mask_m[57] << 8)
+ | (mask_m[58] << 6) | (mask_m[59] << 4)
+ | (mask_m[60] << 2) | (mask_m[61] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
+
+ tmp_mask = (mask_m[31] << 28)
+ | (mask_m[32] << 26) | (mask_m[33] << 24)
+ | (mask_m[34] << 22) | (mask_m[35] << 20)
+ | (mask_m[36] << 18) | (mask_m[37] << 16)
+ | (mask_m[48] << 14) | (mask_m[39] << 12)
+ | (mask_m[40] << 10) | (mask_m[41] << 8)
+ | (mask_m[42] << 6) | (mask_m[43] << 4)
+ | (mask_m[44] << 2) | (mask_m[45] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
+
+ tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
+ | (mask_m[18] << 26) | (mask_m[18] << 24)
+ | (mask_m[20] << 22) | (mask_m[20] << 20)
+ | (mask_m[22] << 18) | (mask_m[22] << 16)
+ | (mask_m[24] << 14) | (mask_m[24] << 12)
+ | (mask_m[25] << 10) | (mask_m[26] << 8)
+ | (mask_m[27] << 6) | (mask_m[28] << 4)
+ | (mask_m[29] << 2) | (mask_m[30] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
+
+ tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
+ | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
+ | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
+ | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
+ | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
+ | (mask_m[10] << 10) | (mask_m[11] << 8)
+ | (mask_m[12] << 6) | (mask_m[13] << 4)
+ | (mask_m[14] << 2) | (mask_m[15] << 0);
+ OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
+
+ tmp_mask = (mask_p[15] << 28)
+ | (mask_p[14] << 26) | (mask_p[13] << 24)
+ | (mask_p[12] << 22) | (mask_p[11] << 20)
+ | (mask_p[10] << 18) | (mask_p[ 9] << 16)
+ | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
+ | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
+ | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
+ | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
+
+ tmp_mask = (mask_p[30] << 28)
+ | (mask_p[29] << 26) | (mask_p[28] << 24)
+ | (mask_p[27] << 22) | (mask_p[26] << 20)
+ | (mask_p[25] << 18) | (mask_p[24] << 16)
+ | (mask_p[23] << 14) | (mask_p[22] << 12)
+ | (mask_p[21] << 10) | (mask_p[20] << 8)
+ | (mask_p[19] << 6) | (mask_p[18] << 4)
+ | (mask_p[17] << 2) | (mask_p[16] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
+
+ tmp_mask = (mask_p[45] << 28)
+ | (mask_p[44] << 26) | (mask_p[43] << 24)
+ | (mask_p[42] << 22) | (mask_p[41] << 20)
+ | (mask_p[40] << 18) | (mask_p[39] << 16)
+ | (mask_p[38] << 14) | (mask_p[37] << 12)
+ | (mask_p[36] << 10) | (mask_p[35] << 8)
+ | (mask_p[34] << 6) | (mask_p[33] << 4)
+ | (mask_p[32] << 2) | (mask_p[31] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
+
+ tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
+ | (mask_p[59] << 26) | (mask_p[58] << 24)
+ | (mask_p[57] << 22) | (mask_p[56] << 20)
+ | (mask_p[55] << 18) | (mask_p[54] << 16)
+ | (mask_p[53] << 14) | (mask_p[52] << 12)
+ | (mask_p[51] << 10) | (mask_p[50] << 8)
+ | (mask_p[49] << 6) | (mask_p[48] << 4)
+ | (mask_p[47] << 2) | (mask_p[46] << 0);
+ OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
+ OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ * Return failure if capabilities are to come from EEPROM and
+ * cannot be read.
+ */
+static HAL_BOOL
+ar9280FillCapabilityInfo(struct ath_hal *ah)
+{
+ HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+ if (!ar5416FillCapabilityInfo(ah))
+ return AH_FALSE;
+ pCap->halNumGpioPins = 10;
+ pCap->halWowSupport = AH_TRUE;
+ pCap->halWowMatchPatternExact = AH_TRUE;
+#if 0
+ pCap->halWowMatchPatternDword = AH_TRUE;
+#endif
+ pCap->halCSTSupport = AH_TRUE;
+ pCap->halRifsRxSupport = AH_TRUE;
+ pCap->halRifsTxSupport = AH_TRUE;
+ pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
+ pCap->halExtChanDfsSupport = AH_TRUE;
+#if 0
+ /* XXX bluetooth */
+ pCap->halBtCoexSupport = AH_TRUE;
+#endif
+ pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
+#if 0
+ pCap->hal4kbSplitTransSupport = AH_FALSE;
+#endif
+ pCap->halRxStbcSupport = 1;
+ pCap->halTxStbcSupport = 1;
+
+ return AH_TRUE;
+}
+
+HAL_BOOL
+ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
+{
+#define ANTENNA0_CHAINMASK 0x1
+#define ANTENNA1_CHAINMASK 0x2
+ struct ath_hal_5416 *ahp = AH5416(ah);
+
+ /* Antenna selection is done by setting the tx/rx chainmasks approp. */
+ switch (settings) {
+ case HAL_ANT_FIXED_A:
+ /* Enable first antenna only */
+ ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
+ ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
+ break;
+ case HAL_ANT_FIXED_B:
+ /* Enable second antenna only, after checking capability */
+ if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
+ ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
+ ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
+ break;
+ case HAL_ANT_VARIABLE:
+ /* Restore original chainmask settings */
+ /* XXX */
+ ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
+ ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
+ break;
+ }
+ return AH_TRUE;
+#undef ANTENNA0_CHAINMASK
+#undef ANTENNA1_CHAINMASK
+}
+
+static const char*
+ar9280Probe(uint16_t vendorid, uint16_t devid)
+{
+ if (vendorid == ATHEROS_VENDOR_ID &&
+ (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE))
+ return "Atheros 9280";
+ return AH_NULL;
+}
+AH_CHIP(AR9280, ar9280Probe, ar9280Attach);
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9280v1.ini b/sys/external/isc/atheros_hal/dist/ar5416/ar9280v1.ini
new file mode 100644
index 0000000..96e0f44
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9280v1.ini
@@ -0,0 +1,582 @@
+/*
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+/* Auto Generated PCI Register Writes. Created: 10/12/07 */
+
+static const uint32_t ar9280Modes_v1[][6] = {
+ { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+ { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+ { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+ { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
+ { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
+ { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
+ { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+ { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+ { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+ { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+ { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
+ { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
+ { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
+ { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
+ { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
+ { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
+ { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
+ { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+ { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
+ { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
+ { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
+ { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
+ { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
+ { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
+ { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
+ { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
+ { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
+ { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
+ { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
+ { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
+ { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+ { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
+ { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+ { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+ { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
+ { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
+ { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
+ { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
+ { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
+ { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
+ { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
+ { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
+ { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
+ { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
+ { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
+ { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
+ { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
+ { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
+ { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
+ { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
+ { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
+ { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
+ { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
+ { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
+ { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
+ { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
+ { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
+ { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
+ { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
+ { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
+ { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
+ { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
+ { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
+ { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
+ { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
+ { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
+ { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
+ { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
+ { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
+ { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
+ { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
+ { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
+ { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
+ { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
+ { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
+ { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
+ { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
+ { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
+ { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
+ { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
+ { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
+ { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
+ { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
+ { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
+ { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
+ { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
+ { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
+ { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
+ { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
+ { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
+ { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
+ { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
+ { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
+ { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
+ { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
+ { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
+ { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
+ { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
+ { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
+ { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
+ { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
+ { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
+ { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
+ { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
+ { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
+ { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
+ { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
+ { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
+ { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
+ { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
+ { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
+ { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
+ { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
+ { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
+ { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
+ { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
+ { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
+ { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
+ { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
+ { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
+ { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
+ { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
+ { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
+ { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
+ { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
+ { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
+ { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
+ { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
+ { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
+ { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
+ { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
+ { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
+ { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
+ { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
+ { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
+ { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
+ { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
+ { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+ { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+ { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
+ { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
+ { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
+ { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
+ { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
+ { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
+ { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
+ { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
+ { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
+ { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
+ { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
+ { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
+ { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
+ { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
+ { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
+ { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
+ { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
+ { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
+ { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
+ { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
+ { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
+ { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
+ { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
+ { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
+ { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
+ { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
+};
+
+static const uint32_t ar9280Common_v1[][2] = {
+ { 0x0000000c, 0x00000000 },
+ { 0x00000030, 0x00020015 },
+ { 0x00000034, 0x00000005 },
+ { 0x00000040, 0x00000000 },
+ { 0x00000044, 0x00000008 },
+ { 0x00000048, 0x00000008 },
+ { 0x0000004c, 0x00000010 },
+ { 0x00000050, 0x00000000 },
+ { 0x00000054, 0x0000001f },
+ { 0x00000800, 0x00000000 },
+ { 0x00000804, 0x00000000 },
+ { 0x00000808, 0x00000000 },
+ { 0x0000080c, 0x00000000 },
+ { 0x00000810, 0x00000000 },
+ { 0x00000814, 0x00000000 },
+ { 0x00000818, 0x00000000 },
+ { 0x0000081c, 0x00000000 },
+ { 0x00000820, 0x00000000 },
+ { 0x00000824, 0x00000000 },
+ { 0x00001040, 0x002ffc0f },
+ { 0x00001044, 0x002ffc0f },
+ { 0x00001048, 0x002ffc0f },
+ { 0x0000104c, 0x002ffc0f },
+ { 0x00001050, 0x002ffc0f },
+ { 0x00001054, 0x002ffc0f },
+ { 0x00001058, 0x002ffc0f },
+ { 0x0000105c, 0x002ffc0f },
+ { 0x00001060, 0x002ffc0f },
+ { 0x00001064, 0x002ffc0f },
+ { 0x00001230, 0x00000000 },
+ { 0x00001270, 0x00000000 },
+ { 0x00001038, 0x00000000 },
+ { 0x00001078, 0x00000000 },
+ { 0x000010b8, 0x00000000 },
+ { 0x000010f8, 0x00000000 },
+ { 0x00001138, 0x00000000 },
+ { 0x00001178, 0x00000000 },
+ { 0x000011b8, 0x00000000 },
+ { 0x000011f8, 0x00000000 },
+ { 0x00001238, 0x00000000 },
+ { 0x00001278, 0x00000000 },
+ { 0x000012b8, 0x00000000 },
+ { 0x000012f8, 0x00000000 },
+ { 0x00001338, 0x00000000 },
+ { 0x00001378, 0x00000000 },
+ { 0x000013b8, 0x00000000 },
+ { 0x000013f8, 0x00000000 },
+ { 0x00001438, 0x00000000 },
+ { 0x00001478, 0x00000000 },
+ { 0x000014b8, 0x00000000 },
+ { 0x000014f8, 0x00000000 },
+ { 0x00001538, 0x00000000 },
+ { 0x00001578, 0x00000000 },
+ { 0x000015b8, 0x00000000 },
+ { 0x000015f8, 0x00000000 },
+ { 0x00001638, 0x00000000 },
+ { 0x00001678, 0x00000000 },
+ { 0x000016b8, 0x00000000 },
+ { 0x000016f8, 0x00000000 },
+ { 0x00001738, 0x00000000 },
+ { 0x00001778, 0x00000000 },
+ { 0x000017b8, 0x00000000 },
+ { 0x000017f8, 0x00000000 },
+ { 0x0000103c, 0x00000000 },
+ { 0x0000107c, 0x00000000 },
+ { 0x000010bc, 0x00000000 },
+ { 0x000010fc, 0x00000000 },
+ { 0x0000113c, 0x00000000 },
+ { 0x0000117c, 0x00000000 },
+ { 0x000011bc, 0x00000000 },
+ { 0x000011fc, 0x00000000 },
+ { 0x0000123c, 0x00000000 },
+ { 0x0000127c, 0x00000000 },
+ { 0x000012bc, 0x00000000 },
+ { 0x000012fc, 0x00000000 },
+ { 0x0000133c, 0x00000000 },
+ { 0x0000137c, 0x00000000 },
+ { 0x000013bc, 0x00000000 },
+ { 0x000013fc, 0x00000000 },
+ { 0x0000143c, 0x00000000 },
+ { 0x0000147c, 0x00000000 },
+ { 0x00004030, 0x00000002 },
+ { 0x0000403c, 0x00000002 },
+ { 0x00004024, 0x0000001f },
+ { 0x00007010, 0x00000033 },
+ { 0x00007038, 0x000004c2 },
+ { 0x00008004, 0x00000000 },
+ { 0x00008008, 0x00000000 },
+ { 0x0000800c, 0x00000000 },
+ { 0x00008018, 0x00000700 },
+ { 0x00008020, 0x00000000 },
+ { 0x00008038, 0x00000000 },
+ { 0x0000803c, 0x00000000 },
+ { 0x00008048, 0x40000000 },
+ { 0x00008054, 0x00000000 },
+ { 0x00008058, 0x00000000 },
+ { 0x0000805c, 0x000fc78f },
+ { 0x00008060, 0x0000000f },
+ { 0x00008064, 0x00000000 },
+ { 0x00008070, 0x00000000 },
+ { 0x000080c0, 0x2a82301a },
+ { 0x000080c4, 0x05dc01e0 },
+ { 0x000080c8, 0x1f402710 },
+ { 0x000080cc, 0x01f40000 },
+ { 0x000080d0, 0x00001e00 },
+ { 0x000080d4, 0x00000000 },
+ { 0x000080d8, 0x00400000 },
+ { 0x000080e0, 0xffffffff },
+ { 0x000080e4, 0x0000ffff },
+ { 0x000080e8, 0x003f3f3f },
+ { 0x000080ec, 0x00000000 },
+ { 0x000080f0, 0x00000000 },
+ { 0x000080f4, 0x00000000 },
+ { 0x000080f8, 0x00000000 },
+ { 0x000080fc, 0x00020000 },
+ { 0x00008100, 0x00020000 },
+ { 0x00008104, 0x00000001 },
+ { 0x00008108, 0x00000052 },
+ { 0x0000810c, 0x00000000 },
+ { 0x00008110, 0x00000168 },
+ { 0x00008118, 0x000100aa },
+ { 0x0000811c, 0x00003210 },
+ { 0x00008120, 0x08f04800 },
+ { 0x00008124, 0x00000000 },
+ { 0x00008128, 0x00000000 },
+ { 0x0000812c, 0x00000000 },
+ { 0x00008130, 0x00000000 },
+ { 0x00008134, 0x00000000 },
+ { 0x00008138, 0x00000000 },
+ { 0x0000813c, 0x00000000 },
+ { 0x00008144, 0x00000000 },
+ { 0x00008168, 0x00000000 },
+ { 0x0000816c, 0x00000000 },
+ { 0x00008170, 0x32143320 },
+ { 0x00008174, 0xfaa4fa50 },
+ { 0x00008178, 0x00000100 },
+ { 0x0000817c, 0x00000000 },
+ { 0x000081c4, 0x00000000 },
+ { 0x000081d0, 0x00003210 },
+ { 0x000081ec, 0x00000000 },
+ { 0x000081f0, 0x00000000 },
+ { 0x000081f4, 0x00000000 },
+ { 0x000081f8, 0x00000000 },
+ { 0x000081fc, 0x00000000 },
+ { 0x00008200, 0x00000000 },
+ { 0x00008204, 0x00000000 },
+ { 0x00008208, 0x00000000 },
+ { 0x0000820c, 0x00000000 },
+ { 0x00008210, 0x00000000 },
+ { 0x00008214, 0x00000000 },
+ { 0x00008218, 0x00000000 },
+ { 0x0000821c, 0x00000000 },
+ { 0x00008220, 0x00000000 },
+ { 0x00008224, 0x00000000 },
+ { 0x00008228, 0x00000000 },
+ { 0x0000822c, 0x00000000 },
+ { 0x00008230, 0x00000000 },
+ { 0x00008234, 0x00000000 },
+ { 0x00008238, 0x00000000 },
+ { 0x0000823c, 0x00000000 },
+ { 0x00008240, 0x00100000 },
+ { 0x00008244, 0x0010f400 },
+ { 0x00008248, 0x00000100 },
+ { 0x0000824c, 0x0001e800 },
+ { 0x00008250, 0x00000000 },
+ { 0x00008254, 0x00000000 },
+ { 0x00008258, 0x00000000 },
+ { 0x0000825c, 0x400000ff },
+ { 0x00008260, 0x00080922 },
+ { 0x00008270, 0x00000000 },
+ { 0x00008274, 0x40000000 },
+ { 0x00008278, 0x003e4180 },
+ { 0x0000827c, 0x00000000 },
+ { 0x00008284, 0x0000002c },
+ { 0x00008288, 0x0000002c },
+ { 0x0000828c, 0x00000000 },
+ { 0x00008294, 0x00000000 },
+ { 0x00008298, 0x00000000 },
+ { 0x00008300, 0x00000000 },
+ { 0x00008304, 0x00000000 },
+ { 0x00008308, 0x00000000 },
+ { 0x0000830c, 0x00000000 },
+ { 0x00008310, 0x00000000 },
+ { 0x00008314, 0x00000000 },
+ { 0x00008318, 0x00000000 },
+ { 0x00008328, 0x00000000 },
+ { 0x0000832c, 0x00000007 },
+ { 0x00008330, 0x00000302 },
+ { 0x00008334, 0x00000e00 },
+ { 0x00008338, 0x00000000 },
+ { 0x0000833c, 0x00000000 },
+ { 0x00008340, 0x000107ff },
+ { 0x00008344, 0x00000000 },
+ { 0x00009808, 0x00000000 },
+ { 0x0000980c, 0xaf268e30 },
+ { 0x00009810, 0xfd14e000 },
+ { 0x00009814, 0x9c0a9f6b },
+ { 0x0000981c, 0x00000000 },
+ { 0x0000982c, 0x0000a000 },
+ { 0x00009830, 0x00000000 },
+ { 0x0000983c, 0x00200400 },
+ { 0x00009840, 0x206a01ae },
+ { 0x0000984c, 0x0040233c },
+ { 0x0000a84c, 0x0040233c },
+ { 0x00009854, 0x00000044 },
+ { 0x00009900, 0x00000000 },
+ { 0x00009904, 0x00000000 },
+ { 0x00009908, 0x00000000 },
+ { 0x0000990c, 0x00000000 },
+ { 0x0000991c, 0x10000fff },
+ { 0x00009920, 0x04900000 },
+ { 0x0000a920, 0x04900000 },
+ { 0x00009928, 0x00000001 },
+ { 0x0000992c, 0x00000004 },
+ { 0x00009934, 0x1e1f2022 },
+ { 0x00009938, 0x0a0b0c0d },
+ { 0x0000993c, 0x00000000 },
+ { 0x00009948, 0x9280c00a },
+ { 0x0000994c, 0x00020028 },
+ { 0x00009954, 0xe250a51e },
+ { 0x00009958, 0x3388ffff },
+ { 0x00009940, 0x00781204 },
+ { 0x0000c95c, 0x004b6a8e },
+ { 0x0000c968, 0x000003ce },
+ { 0x00009970, 0x190fb514 },
+ { 0x00009974, 0x00000000 },
+ { 0x00009978, 0x00000001 },
+ { 0x0000997c, 0x00000000 },
+ { 0x00009980, 0x00000000 },
+ { 0x00009984, 0x00000000 },
+ { 0x00009988, 0x00000000 },
+ { 0x0000998c, 0x00000000 },
+ { 0x00009990, 0x00000000 },
+ { 0x00009994, 0x00000000 },
+ { 0x00009998, 0x00000000 },
+ { 0x0000999c, 0x00000000 },
+ { 0x000099a0, 0x00000000 },
+ { 0x000099a4, 0x00000001 },
+ { 0x000099a8, 0x201fff00 },
+ { 0x000099ac, 0x006f00c4 },
+ { 0x000099b0, 0x03051000 },
+ { 0x000099b4, 0x00000820 },
+ { 0x000099dc, 0x00000000 },
+ { 0x000099e0, 0x00000000 },
+ { 0x000099e4, 0xaaaaaaaa },
+ { 0x000099e8, 0x3c466478 },
+ { 0x000099ec, 0x0cc80caa },
+ { 0x000099fc, 0x00001042 },
+ { 0x0000a210, 0x4080a333 },
+ { 0x0000a214, 0x40206c10 },
+ { 0x0000a218, 0x009c4060 },
+ { 0x0000a220, 0x01834061 },
+ { 0x0000a224, 0x00000400 },
+ { 0x0000a228, 0x000003b5 },
+ { 0x0000a22c, 0x23277200 },
+ { 0x0000a234, 0x20202020 },
+ { 0x0000a238, 0x20202020 },
+ { 0x0000a23c, 0x13c889af },
+ { 0x0000a240, 0x38490a20 },
+ { 0x0000a244, 0x00007bb6 },
+ { 0x0000a248, 0x0fff3ffc },
+ { 0x0000a24c, 0x00000001 },
+ { 0x0000a250, 0x001da000 },
+ { 0x0000a254, 0x00000000 },
+ { 0x0000a258, 0x0cdbd380 },
+ { 0x0000a25c, 0x0f0f0f01 },
+ { 0x0000a260, 0xdfa91f01 },
+ { 0x0000a268, 0x00000000 },
+ { 0x0000a26c, 0x0ebae9c6 },
+ { 0x0000b26c, 0x0ebae9c6 },
+ { 0x0000d270, 0x00820820 },
+ { 0x0000a278, 0x1ce739ce },
+ { 0x0000a27c, 0x050701ce },
+ { 0x0000a358, 0x7999aa0f },
+ { 0x0000d35c, 0x07ffffef },
+ { 0x0000d360, 0x0fffffe7 },
+ { 0x0000d364, 0x17ffffe5 },
+ { 0x0000d368, 0x1fffffe4 },
+ { 0x0000d36c, 0x37ffffe3 },
+ { 0x0000d370, 0x3fffffe3 },
+ { 0x0000d374, 0x57ffffe3 },
+ { 0x0000d378, 0x5fffffe2 },
+ { 0x0000d37c, 0x7fffffe2 },
+ { 0x0000d380, 0x7f3c7bba },
+ { 0x0000d384, 0xf3307ff0 },
+ { 0x0000a388, 0x0c000000 },
+ { 0x0000a38c, 0x20202020 },
+ { 0x0000a390, 0x20202020 },
+ { 0x0000a394, 0x1ce739ce },
+ { 0x0000a398, 0x000001ce },
+ { 0x0000a39c, 0x00000001 },
+ { 0x0000a3a0, 0x00000000 },
+ { 0x0000a3a4, 0x00000000 },
+ { 0x0000a3a8, 0x00000000 },
+ { 0x0000a3ac, 0x00000000 },
+ { 0x0000a3b0, 0x00000000 },
+ { 0x0000a3b4, 0x00000000 },
+ { 0x0000a3b8, 0x00000000 },
+ { 0x0000a3bc, 0x00000000 },
+ { 0x0000a3c0, 0x00000000 },
+ { 0x0000a3c4, 0x00000000 },
+ { 0x0000a3c8, 0x00000246 },
+ { 0x0000a3cc, 0x20202020 },
+ { 0x0000a3d0, 0x20202020 },
+ { 0x0000a3d4, 0x20202020 },
+ { 0x0000a3dc, 0x1ce739ce },
+ { 0x0000a3e0, 0x000001ce },
+ { 0x0000a3e4, 0x00000000 },
+ { 0x0000a3e8, 0x18c43433 },
+ { 0x0000a3ec, 0x00f38081 },
+ { 0x00007800, 0x00040000 },
+ { 0x00007804, 0xdb005012 },
+ { 0x00007808, 0x04924914 },
+ { 0x0000780c, 0x21084210 },
+ { 0x00007810, 0x6d801300 },
+ { 0x00007814, 0x0019beff },
+ { 0x00007818, 0x07e40000 },
+ { 0x0000781c, 0x00492000 },
+ { 0x00007820, 0x92492480 },
+ { 0x00007824, 0x00040000 },
+ { 0x00007828, 0xdb005012 },
+ { 0x0000782c, 0x04924914 },
+ { 0x00007830, 0x21084210 },
+ { 0x00007834, 0x6d801300 },
+ { 0x00007838, 0x0019beff },
+ { 0x0000783c, 0x07e40000 },
+ { 0x00007840, 0x00492000 },
+ { 0x00007844, 0x92492480 },
+ { 0x00007848, 0x00120000 },
+ { 0x00007850, 0x54214514 },
+ { 0x00007858, 0x92592692 },
+ { 0x00007860, 0x52802000 },
+ { 0x00007864, 0x0a8e370e },
+ { 0x00007868, 0xc0102850 },
+ { 0x0000786c, 0x812d4000 },
+ { 0x00007874, 0x001b6db0 },
+ { 0x00007878, 0x00376b63 },
+ { 0x0000787c, 0x06db6db6 },
+ { 0x00007880, 0x006d8000 },
+ { 0x00007884, 0xffeffffe },
+ { 0x00007888, 0xffeffffe },
+ { 0x00007890, 0x00060aeb },
+ { 0x00007894, 0x5a108000 },
+ { 0x00007898, 0x2a850160 },
+};
+
+/* hand-crafted from code that does explicit register writes */
+static const uint32_t ar9280PciePhy_v1[][2] = {
+ { AR_PCIE_SERDES, 0x9248fd00 },
+ { AR_PCIE_SERDES, 0x24924924 },
+ { AR_PCIE_SERDES, 0xa8000019 },
+ { AR_PCIE_SERDES, 0x13160820 },
+ { AR_PCIE_SERDES, 0xe5980560 },
+ { AR_PCIE_SERDES, 0x401deffd },
+ { AR_PCIE_SERDES, 0x1aaabe40 },
+ { AR_PCIE_SERDES, 0xbe105554 },
+ { AR_PCIE_SERDES, 0x00043007 },
+ { AR_PCIE_SERDES2, 0x00000000 },
+};
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9280v2.ini b/sys/external/isc/atheros_hal/dist/ar5416/ar9280v2.ini
new file mode 100644
index 0000000..aa8e524
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9280v2.ini
@@ -0,0 +1,941 @@
+/*
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+/* Auto Generated PCI Register Writes. Created: 10/15/08 */
+
+static const uint32_t ar9280Modes_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+ { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+ { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+ { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
+ { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
+ { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
+ { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
+ { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+ { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+ { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+ { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+ { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
+ { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
+ { 0x00009850, 0x6c4000e2, 0x6c4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
+ { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
+ { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x3139605e, 0x31395d5e, 0x31395d5e },
+ { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
+ { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+ { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
+ { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
+ { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
+ { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
+ { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
+ { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
+ { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
+ { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
+ { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
+ { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
+ { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
+ { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
+ { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+ { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
+ { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+ { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+ { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
+ { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
+ { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
+ { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+ { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+ { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
+ { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
+ { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
+ { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
+};
+
+static const uint32_t ar9280Common_v2[][2] = {
+ { 0x0000000c, 0x00000000 },
+ { 0x00000030, 0x00020015 },
+ { 0x00000034, 0x00000005 },
+ { 0x00000040, 0x00000000 },
+ { 0x00000044, 0x00000008 },
+ { 0x00000048, 0x00000008 },
+ { 0x0000004c, 0x00000010 },
+ { 0x00000050, 0x00000000 },
+ { 0x00000054, 0x0000001f },
+ { 0x00000800, 0x00000000 },
+ { 0x00000804, 0x00000000 },
+ { 0x00000808, 0x00000000 },
+ { 0x0000080c, 0x00000000 },
+ { 0x00000810, 0x00000000 },
+ { 0x00000814, 0x00000000 },
+ { 0x00000818, 0x00000000 },
+ { 0x0000081c, 0x00000000 },
+ { 0x00000820, 0x00000000 },
+ { 0x00000824, 0x00000000 },
+ { 0x00001040, 0x002ffc0f },
+ { 0x00001044, 0x002ffc0f },
+ { 0x00001048, 0x002ffc0f },
+ { 0x0000104c, 0x002ffc0f },
+ { 0x00001050, 0x002ffc0f },
+ { 0x00001054, 0x002ffc0f },
+ { 0x00001058, 0x002ffc0f },
+ { 0x0000105c, 0x002ffc0f },
+ { 0x00001060, 0x002ffc0f },
+ { 0x00001064, 0x002ffc0f },
+ { 0x00001230, 0x00000000 },
+ { 0x00001270, 0x00000000 },
+ { 0x00001038, 0x00000000 },
+ { 0x00001078, 0x00000000 },
+ { 0x000010b8, 0x00000000 },
+ { 0x000010f8, 0x00000000 },
+ { 0x00001138, 0x00000000 },
+ { 0x00001178, 0x00000000 },
+ { 0x000011b8, 0x00000000 },
+ { 0x000011f8, 0x00000000 },
+ { 0x00001238, 0x00000000 },
+ { 0x00001278, 0x00000000 },
+ { 0x000012b8, 0x00000000 },
+ { 0x000012f8, 0x00000000 },
+ { 0x00001338, 0x00000000 },
+ { 0x00001378, 0x00000000 },
+ { 0x000013b8, 0x00000000 },
+ { 0x000013f8, 0x00000000 },
+ { 0x00001438, 0x00000000 },
+ { 0x00001478, 0x00000000 },
+ { 0x000014b8, 0x00000000 },
+ { 0x000014f8, 0x00000000 },
+ { 0x00001538, 0x00000000 },
+ { 0x00001578, 0x00000000 },
+ { 0x000015b8, 0x00000000 },
+ { 0x000015f8, 0x00000000 },
+ { 0x00001638, 0x00000000 },
+ { 0x00001678, 0x00000000 },
+ { 0x000016b8, 0x00000000 },
+ { 0x000016f8, 0x00000000 },
+ { 0x00001738, 0x00000000 },
+ { 0x00001778, 0x00000000 },
+ { 0x000017b8, 0x00000000 },
+ { 0x000017f8, 0x00000000 },
+ { 0x0000103c, 0x00000000 },
+ { 0x0000107c, 0x00000000 },
+ { 0x000010bc, 0x00000000 },
+ { 0x000010fc, 0x00000000 },
+ { 0x0000113c, 0x00000000 },
+ { 0x0000117c, 0x00000000 },
+ { 0x000011bc, 0x00000000 },
+ { 0x000011fc, 0x00000000 },
+ { 0x0000123c, 0x00000000 },
+ { 0x0000127c, 0x00000000 },
+ { 0x000012bc, 0x00000000 },
+ { 0x000012fc, 0x00000000 },
+ { 0x0000133c, 0x00000000 },
+ { 0x0000137c, 0x00000000 },
+ { 0x000013bc, 0x00000000 },
+ { 0x000013fc, 0x00000000 },
+ { 0x0000143c, 0x00000000 },
+ { 0x0000147c, 0x00000000 },
+ { 0x00004030, 0x00000002 },
+ { 0x0000403c, 0x00000002 },
+ { 0x00004024, 0x0000001f },
+ { 0x00004060, 0x00000000 },
+ { 0x00004064, 0x00000000 },
+ { 0x00007010, 0x00000033 },
+ { 0x00007034, 0x00000002 },
+ { 0x00007038, 0x000004c2 },
+ { 0x00008004, 0x00000000 },
+ { 0x00008008, 0x00000000 },
+ { 0x0000800c, 0x00000000 },
+ { 0x00008018, 0x00000700 },
+ { 0x00008020, 0x00000000 },
+ { 0x00008038, 0x00000000 },
+ { 0x0000803c, 0x00000000 },
+ { 0x00008048, 0x40000000 },
+ { 0x00008054, 0x00000000 },
+ { 0x00008058, 0x00000000 },
+ { 0x0000805c, 0x000fc78f },
+ { 0x00008060, 0x0000000f },
+ { 0x00008064, 0x00000000 },
+ { 0x00008070, 0x00000000 },
+ { 0x000080c0, 0x2a80001a },
+ { 0x000080c4, 0x05dc01e0 },
+ { 0x000080c8, 0x1f402710 },
+ { 0x000080cc, 0x01f40000 },
+ { 0x000080d0, 0x00001e00 },
+ { 0x000080d4, 0x00000000 },
+ { 0x000080d8, 0x00400000 },
+ { 0x000080e0, 0xffffffff },
+ { 0x000080e4, 0x0000ffff },
+ { 0x000080e8, 0x003f3f3f },
+ { 0x000080ec, 0x00000000 },
+ { 0x000080f0, 0x00000000 },
+ { 0x000080f4, 0x00000000 },
+ { 0x000080f8, 0x00000000 },
+ { 0x000080fc, 0x00020000 },
+ { 0x00008100, 0x00020000 },
+ { 0x00008104, 0x00000001 },
+ { 0x00008108, 0x00000052 },
+ { 0x0000810c, 0x00000000 },
+ { 0x00008110, 0x00000168 },
+ { 0x00008118, 0x000100aa },
+ { 0x0000811c, 0x00003210 },
+ { 0x00008120, 0x08f04800 },
+ { 0x00008124, 0x00000000 },
+ { 0x00008128, 0x00000000 },
+ { 0x0000812c, 0x00000000 },
+ { 0x00008130, 0x00000000 },
+ { 0x00008134, 0x00000000 },
+ { 0x00008138, 0x00000000 },
+ { 0x0000813c, 0x00000000 },
+ { 0x00008144, 0xffffffff },
+ { 0x00008168, 0x00000000 },
+ { 0x0000816c, 0x00000000 },
+ { 0x00008170, 0x32143320 },
+ { 0x00008174, 0xfaa4fa50 },
+ { 0x00008178, 0x00000100 },
+ { 0x0000817c, 0x00000000 },
+ { 0x000081c0, 0x00000000 },
+ { 0x000081d0, 0x00003210 },
+ { 0x000081ec, 0x00000000 },
+ { 0x000081f0, 0x00000000 },
+ { 0x000081f4, 0x00000000 },
+ { 0x000081f8, 0x00000000 },
+ { 0x000081fc, 0x00000000 },
+ { 0x00008200, 0x00000000 },
+ { 0x00008204, 0x00000000 },
+ { 0x00008208, 0x00000000 },
+ { 0x0000820c, 0x00000000 },
+ { 0x00008210, 0x00000000 },
+ { 0x00008214, 0x00000000 },
+ { 0x00008218, 0x00000000 },
+ { 0x0000821c, 0x00000000 },
+ { 0x00008220, 0x00000000 },
+ { 0x00008224, 0x00000000 },
+ { 0x00008228, 0x00000000 },
+ { 0x0000822c, 0x00000000 },
+ { 0x00008230, 0x00000000 },
+ { 0x00008234, 0x00000000 },
+ { 0x00008238, 0x00000000 },
+ { 0x0000823c, 0x00000000 },
+ { 0x00008240, 0x00100000 },
+ { 0x00008244, 0x0010f400 },
+ { 0x00008248, 0x00000100 },
+ { 0x0000824c, 0x0001e800 },
+ { 0x00008250, 0x00000000 },
+ { 0x00008254, 0x00000000 },
+ { 0x00008258, 0x00000000 },
+ { 0x0000825c, 0x400000ff },
+ { 0x00008260, 0x00080922 },
+ { 0x00008264, 0xa8a00010 },
+ { 0x00008270, 0x00000000 },
+ { 0x00008274, 0x40000000 },
+ { 0x00008278, 0x003e4180 },
+ { 0x0000827c, 0x00000000 },
+ { 0x00008284, 0x0000002c },
+ { 0x00008288, 0x0000002c },
+ { 0x0000828c, 0x00000000 },
+ { 0x00008294, 0x00000000 },
+ { 0x00008298, 0x00000000 },
+ { 0x0000829c, 0x00000000 },
+ { 0x00008300, 0x00000040 },
+ { 0x00008314, 0x00000000 },
+ { 0x00008328, 0x00000000 },
+ { 0x0000832c, 0x00000007 },
+ { 0x00008330, 0x00000302 },
+ { 0x00008334, 0x00000e00 },
+ { 0x00008338, 0x00ff0000 },
+ { 0x0000833c, 0x00000000 },
+ { 0x00008340, 0x000107ff },
+ { 0x00008344, 0x00581043 },
+ { 0x00009808, 0x00000000 },
+ { 0x0000980c, 0xafa68e30 },
+ { 0x00009810, 0xfd14e000 },
+ { 0x00009814, 0x9c0a9f6b },
+ { 0x0000981c, 0x00000000 },
+ { 0x0000982c, 0x0000a000 },
+ { 0x00009830, 0x00000000 },
+ { 0x0000983c, 0x00200400 },
+ { 0x0000984c, 0x0040233c },
+ { 0x0000a84c, 0x0040233c },
+ { 0x00009854, 0x00000044 },
+ { 0x00009900, 0x00000000 },
+ { 0x00009904, 0x00000000 },
+ { 0x00009908, 0x00000000 },
+ { 0x0000990c, 0x00000000 },
+ { 0x00009910, 0x01002310 },
+ { 0x0000991c, 0x10000fff },
+ { 0x00009920, 0x04900000 },
+ { 0x0000a920, 0x04900000 },
+ { 0x00009928, 0x00000001 },
+ { 0x0000992c, 0x00000004 },
+ { 0x00009934, 0x1e1f2022 },
+ { 0x00009938, 0x0a0b0c0d },
+ { 0x0000993c, 0x00000000 },
+ { 0x00009948, 0x9280c00a },
+ { 0x0000994c, 0x00020028 },
+ { 0x00009954, 0x5f3ca3de },
+ { 0x00009958, 0x2108ecff },
+ { 0x00009940, 0x14750604 },
+ { 0x0000c95c, 0x004b6a8e },
+ { 0x00009968, 0x000003ce },
+ { 0x00009970, 0x190fb515 },
+ { 0x00009974, 0x00000000 },
+ { 0x00009978, 0x00000001 },
+ { 0x0000997c, 0x00000000 },
+ { 0x00009980, 0x00000000 },
+ { 0x00009984, 0x00000000 },
+ { 0x00009988, 0x00000000 },
+ { 0x0000998c, 0x00000000 },
+ { 0x00009990, 0x00000000 },
+ { 0x00009994, 0x00000000 },
+ { 0x00009998, 0x00000000 },
+ { 0x0000999c, 0x00000000 },
+ { 0x000099a0, 0x00000000 },
+ { 0x000099a4, 0x00000001 },
+ { 0x000099a8, 0x201fff00 },
+ { 0x000099ac, 0x006f0000 },
+ { 0x000099b0, 0x03051000 },
+ { 0x000099b4, 0x00000820 },
+ { 0x000099dc, 0x00000000 },
+ { 0x000099e0, 0x00000000 },
+ { 0x000099e4, 0xaaaaaaaa },
+ { 0x000099e8, 0x3c466478 },
+ { 0x000099ec, 0x0cc80caa },
+ { 0x000099f0, 0x00000000 },
+ { 0x000099fc, 0x00001042 },
+ { 0x0000a208, 0x803e4788 },
+ { 0x0000a210, 0x4080a333 },
+ { 0x0000a214, 0x40206c10 },
+ { 0x0000a218, 0x009c4060 },
+ { 0x0000a220, 0x01834061 },
+ { 0x0000a224, 0x00000400 },
+ { 0x0000a228, 0x000003b5 },
+ { 0x0000a22c, 0x233f7180 },
+ { 0x0000a234, 0x20202020 },
+ { 0x0000a238, 0x20202020 },
+ { 0x0000a23c, 0x13c88000 },
+ { 0x0000a240, 0x38490a20 },
+ { 0x0000a244, 0x00007bb6 },
+ { 0x0000a248, 0x0fff3ffc },
+ { 0x0000a24c, 0x00000000 },
+ { 0x0000a254, 0x00000000 },
+ { 0x0000a258, 0x0cdbd380 },
+ { 0x0000a25c, 0x0f0f0f01 },
+ { 0x0000a260, 0xdfa91f01 },
+ { 0x0000a268, 0x00000000 },
+ { 0x0000a26c, 0x0ebae9c6 },
+ { 0x0000b26c, 0x0ebae9c6 },
+ { 0x0000d270, 0x00820820 },
+ { 0x0000a278, 0x1ce739ce },
+ { 0x0000d35c, 0x07ffffef },
+ { 0x0000d360, 0x0fffffe7 },
+ { 0x0000d364, 0x17ffffe5 },
+ { 0x0000d368, 0x1fffffe4 },
+ { 0x0000d36c, 0x37ffffe3 },
+ { 0x0000d370, 0x3fffffe3 },
+ { 0x0000d374, 0x57ffffe3 },
+ { 0x0000d378, 0x5fffffe2 },
+ { 0x0000d37c, 0x7fffffe2 },
+ { 0x0000d380, 0x7f3c7bba },
+ { 0x0000d384, 0xf3307ff0 },
+ { 0x0000a388, 0x0c000000 },
+ { 0x0000a38c, 0x20202020 },
+ { 0x0000a390, 0x20202020 },
+ { 0x0000a394, 0x1ce739ce },
+ { 0x0000a398, 0x000001ce },
+ { 0x0000a39c, 0x00000001 },
+ { 0x0000a3a0, 0x00000000 },
+ { 0x0000a3a4, 0x00000000 },
+ { 0x0000a3a8, 0x00000000 },
+ { 0x0000a3ac, 0x00000000 },
+ { 0x0000a3b0, 0x00000000 },
+ { 0x0000a3b4, 0x00000000 },
+ { 0x0000a3b8, 0x00000000 },
+ { 0x0000a3bc, 0x00000000 },
+ { 0x0000a3c0, 0x00000000 },
+ { 0x0000a3c4, 0x00000000 },
+ { 0x0000a3c8, 0x00000246 },
+ { 0x0000a3cc, 0x20202020 },
+ { 0x0000a3d0, 0x20202020 },
+ { 0x0000a3d4, 0x20202020 },
+ { 0x0000a3dc, 0x1ce739ce },
+ { 0x0000a3e0, 0x000001ce },
+ { 0x0000a3e4, 0x00000000 },
+ { 0x0000a3e8, 0x18c43433 },
+ { 0x0000a3ec, 0x00f70081 },
+ { 0x00007800, 0x00040000 },
+ { 0x00007804, 0xdb005012 },
+ { 0x00007808, 0x04924914 },
+ { 0x0000780c, 0x21084210 },
+ { 0x00007810, 0x6d801300 },
+ { 0x00007818, 0x07e41000 },
+ { 0x0000781c, 0x00392000 },
+ { 0x00007820, 0x92592480 },
+ { 0x00007824, 0x00040000 },
+ { 0x00007828, 0xdb005012 },
+ { 0x0000782c, 0x04924914 },
+ { 0x00007830, 0x21084210 },
+ { 0x00007834, 0x6d801300 },
+ { 0x0000783c, 0x07e40000 },
+ { 0x00007840, 0x00392000 },
+ { 0x00007844, 0x92592480 },
+ { 0x00007848, 0x00100000 },
+ { 0x0000784c, 0x773f0567 },
+ { 0x00007850, 0x54214514 },
+ { 0x00007854, 0x12035828 },
+ { 0x00007858, 0x9259269a },
+ { 0x00007860, 0x52802000 },
+ { 0x00007864, 0x0a8e370e },
+ { 0x00007868, 0xc0102850 },
+ { 0x0000786c, 0x812d4000 },
+ { 0x00007870, 0x807ec400 },
+ { 0x00007874, 0x001b6db0 },
+ { 0x00007878, 0x00376b63 },
+ { 0x0000787c, 0x06db6db6 },
+ { 0x00007880, 0x006d8000 },
+ { 0x00007884, 0xffeffffe },
+ { 0x00007888, 0xffeffffe },
+ { 0x0000788c, 0x00010000 },
+ { 0x00007890, 0x02060aeb },
+ { 0x00007898, 0x2a850160 },
+};
+
+static const uint32_t ar9280Modes_fast_clock_v2[][3] = {
+ /* Address 5G-HT20 5G-HT40 */
+ { 0x00001030, 0x00000268, 0x000004d0 },
+ { 0x00001070, 0x0000018c, 0x00000318 },
+ { 0x000010b0, 0x00000fd0, 0x00001fa0 },
+ { 0x00008014, 0x044c044c, 0x08980898 },
+ { 0x0000801c, 0x148ec02b, 0x148ec057 },
+ { 0x00008318, 0x000044c0, 0x00008980 },
+ { 0x00009820, 0x02020200, 0x02020200 },
+ { 0x00009824, 0x00000f0f, 0x00000f0f },
+ { 0x00009828, 0x0b020001, 0x0b020001 },
+ { 0x00009834, 0x00000f0f, 0x00000f0f },
+ { 0x00009844, 0x03721821, 0x03721821 },
+ { 0x00009914, 0x00000898, 0x00001130 },
+ { 0x00009918, 0x0000000b, 0x00000016 },
+ { 0x00009944, 0xdfbc1210, 0xdfbc1210 },
+};
+
+static const uint32_t ar9280Modes_backoff_23db_rxgain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
+ { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
+ { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
+ { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
+ { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
+ { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
+ { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
+ { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
+ { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
+ { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
+ { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
+ { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
+ { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
+ { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
+ { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
+ { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
+ { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
+ { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
+ { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
+ { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
+ { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
+ { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
+ { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
+ { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
+ { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
+ { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
+ { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
+ { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
+ { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
+ { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
+ { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
+ { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
+ { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
+ { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
+ { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
+ { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
+ { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
+ { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
+ { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
+ { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
+ { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
+ { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
+ { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
+ { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
+ { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
+ { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
+ { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
+ { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
+ { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
+ { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
+ { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
+ { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
+ { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
+ { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
+ { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
+ { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
+ { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
+ { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
+ { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
+ { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
+ { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
+ { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
+ { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
+ { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
+ { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
+ { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
+ { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
+ { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
+ { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
+ { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
+ { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
+ { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
+ { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
+ { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
+ { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
+ { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
+ { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
+ { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
+ { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
+ { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
+ { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
+ { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
+ { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
+};
+
+static const uint32_t ar9280Modes_original_rxgain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
+ { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
+ { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
+ { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
+ { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
+ { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
+ { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
+ { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
+ { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
+ { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
+ { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
+ { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
+ { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
+ { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
+ { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
+ { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
+ { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
+ { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
+ { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
+ { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
+ { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
+ { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
+ { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
+ { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
+ { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
+ { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
+ { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
+ { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
+ { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
+ { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
+ { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
+ { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
+ { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
+ { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
+ { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
+ { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
+ { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
+ { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
+ { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
+ { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
+ { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
+ { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
+ { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
+ { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
+ { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
+ { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
+ { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
+ { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
+ { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
+ { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
+ { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
+ { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
+ { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
+ { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
+ { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
+ { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
+ { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
+ { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
+ { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
+ { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
+ { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
+ { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
+ { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
+ { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
+ { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
+ { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
+ { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
+ { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
+ { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
+ { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
+ { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
+ { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
+ { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
+ { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
+ { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
+ { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
+ { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
+ { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
+ { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
+ { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
+ { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
+ { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
+ { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
+ { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
+ { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
+ { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
+ { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
+ { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
+ { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
+ { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
+ { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
+ { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
+ { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
+ { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
+ { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
+ { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
+ { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
+ { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
+ { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
+ { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
+ { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
+ { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
+};
+
+static const uint32_t ar9280Modes_backoff_13db_rxgain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
+ { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
+ { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
+ { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
+ { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
+ { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
+ { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
+ { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
+ { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
+ { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
+ { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
+ { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
+ { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
+ { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
+ { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
+ { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
+ { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
+ { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
+ { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
+ { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
+ { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
+ { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
+ { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
+ { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
+ { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
+ { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
+ { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
+ { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
+ { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
+ { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
+ { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
+ { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
+ { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
+ { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
+ { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
+ { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
+ { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
+ { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
+ { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
+ { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
+ { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
+ { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
+ { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
+ { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
+ { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
+ { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
+ { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
+ { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
+ { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
+ { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
+ { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
+ { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
+ { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
+ { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
+ { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
+ { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
+ { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
+ { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
+ { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
+ { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
+ { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
+ { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
+ { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
+ { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
+ { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
+ { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
+ { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
+ { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
+ { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
+ { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
+ { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
+ { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
+ { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
+ { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
+ { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
+ { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
+ { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
+ { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
+ { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
+ { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
+ { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
+ { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
+ { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
+ { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
+ { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
+ { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
+ { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
+ { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
+ { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
+ { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
+ { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
+ { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
+ { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
+};
+
+static const uint32_t ar9280Modes_high_power_tx_gain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
+ { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
+ { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
+ { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
+ { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
+ { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
+ { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
+ { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
+ { 0x0000a324, 0x00020092, 0x00020092, 0x00022411, 0x00022411, 0x00022411 },
+ { 0x0000a328, 0x0002410a, 0x0002410a, 0x00025413, 0x00025413, 0x00025413 },
+ { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00029811, 0x00029811, 0x00029811 },
+ { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002c813, 0x0002c813, 0x0002c813 },
+ { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
+ { 0x0000a338, 0x000321ec, 0x000321ec, 0x00035a50, 0x00035a50, 0x00035a50 },
+ { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
+ { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
+ { 0x0000a344, 0x000321ec, 0x000321ec, 0x00042e92, 0x00042e92, 0x00042e92 },
+ { 0x0000a348, 0x000321ec, 0x000321ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
+ { 0x0000a34c, 0x000321ec, 0x000321ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
+ { 0x0000a350, 0x000321ec, 0x000321ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
+ { 0x0000a354, 0x000321ec, 0x000321ec, 0x00053fd5, 0x00053fd5, 0x00053fd5 },
+ { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
+ { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
+ { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
+};
+
+static const uint32_t ar9280Modes_original_tx_gain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
+ { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
+ { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
+ { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
+ { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
+ { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
+ { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
+ { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
+ { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
+ { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
+ { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
+ { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
+ { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
+ { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
+ { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
+ { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
+ { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
+ { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
+ { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
+ { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
+ { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
+ { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
+ { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
+ { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
+};
+
+/* Auto generated PCI-E PHY config for Merlin with CLKREQ de-asserted in L1 mode. */
+/* In L1 mode, deassert CLKREQ, power consumption will be lower than leaving CLKREQ asserted. */
+static const uint32_t ar9280PciePhy_clkreq_off_L1_v2[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01dcffc },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
+
+/* Auto generated PCI-E PHY config for Merlin with CLKREQ always asserted in L1 mode */
+/* In L1 mode leave CLKREQ asserted, power consumption will be little high. */
+static const uint32_t ar9280PciePhy_clkreq_always_on_L1_v2[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01dcffd },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
+
+/* Auto generated PCI-E PHY config for Merlin with WOW */
+static const uint32_t ar9280PciePhy_AWOW_merlin[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01ddffd },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
+
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9285.c b/sys/external/isc/atheros_hal/dist/ar5416/ar9285.c
new file mode 100644
index 0000000..800c92f
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9285.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v14.h"
+
+#include "ar5416/ar9280.h"
+#include "ar5416/ar9285.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+static void
+ar9285GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
+{
+ int16_t nf;
+
+ nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
+ if (nf & 0x100)
+ nf = 0 - ((nf ^ 0x1ff) + 1);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "NF calibrated [ctl] [chain 0] is %d\n", nf);
+ nfarray[0] = nf;
+
+ nfarray[1] = 0;
+
+ nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
+ if (nf & 0x100)
+ nf = 0 - ((nf ^ 0x1ff) + 1);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "NF calibrated [ext] [chain 0] is %d\n", nf);
+ nfarray[3] = nf;
+
+ nfarray[4] = 0;
+}
+
+HAL_BOOL
+ar9285RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+ if (ar9280RfAttach(ah, status) == AH_FALSE)
+ return AH_FALSE;
+
+ AH_PRIVATE(ah)->ah_getNoiseFloor = ar9285GetNoiseFloor;
+
+ return AH_TRUE;
+}
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9285.h b/sys/external/isc/atheros_hal/dist/ar5416/ar9285.h
new file mode 100644
index 0000000..1ee058b
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9285.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#ifndef _ATH_AR9285_H_
+#define _ATH_AR9285_H_
+
+#include "ar5416/ar5416.h"
+
+struct ath_hal_9285 {
+ struct ath_hal_5416 ah_5416;
+
+ HAL_INI_ARRAY ah_ini_txgain;
+ HAL_INI_ARRAY ah_ini_rxgain;
+};
+#define AH9285(_ah) ((struct ath_hal_9285 *)(_ah))
+
+#define AR9285_DEFAULT_RXCHAINMASK 1
+#define AR9285_DEFAULT_TXCHAINMASK 1
+
+
+HAL_BOOL ar9285SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
+HAL_BOOL ar9285RfAttach(struct ath_hal *, HAL_STATUS *);
+
+extern HAL_BOOL ar9285SetTransmitPower(struct ath_hal *,
+ const struct ieee80211_channel *, uint16_t *);
+extern HAL_BOOL ar9285SetBoardValues(struct ath_hal *,
+ const struct ieee80211_channel *);
+
+#endif /* _ATH_AR9285_H_ */
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9285.ini b/sys/external/isc/atheros_hal/dist/ar5416/ar9285.ini
new file mode 100644
index 0000000..ef0ff2d
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9285.ini
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+/* AR9285 Revsion 10 */
+static const u_int32_t ar9285Modes[][6] = {
+ { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+ { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+ { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+ { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
+ { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
+ { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
+ { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
+ { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+ { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+ { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+ { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+ { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
+ { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
+ { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
+ { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
+ { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
+ { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
+ { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
+ { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+ { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
+ { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
+ { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
+ { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
+ { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
+ { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
+ { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
+ { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
+ { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
+ { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+ { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
+ { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+ { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+ { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
+ { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
+ { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
+ { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
+ { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
+ { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
+ { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
+ { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
+ { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
+ { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
+ { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
+ { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
+ { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
+ { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
+ { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
+ { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
+ { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
+ { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
+ { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
+ { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
+ { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
+ { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
+ { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
+ { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
+ { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
+ { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
+ { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
+ { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
+ { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
+ { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
+ { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
+ { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
+ { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
+ { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
+ { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
+ { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
+ { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
+ { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
+ { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
+ { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
+ { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
+ { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
+ { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
+ { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
+ { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
+ { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
+ { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
+ { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
+ { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
+ { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
+ { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
+ { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
+ { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
+ { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
+ { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
+ { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
+ { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
+ { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
+ { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
+ { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
+ { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
+ { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
+ { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
+ { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
+ { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
+ { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
+ { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
+ { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
+ { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
+ { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
+ { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
+ { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
+ { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
+ { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
+ { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
+ { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
+ { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
+ { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
+ { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
+ { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
+ { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
+ { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
+ { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
+ { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
+ { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
+ { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
+ { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
+ { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
+ { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
+ { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
+ { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
+ { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
+ { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
+ { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
+ { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
+ { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
+ { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
+ { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
+ { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
+ { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
+ { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
+ { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
+ { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
+ { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
+ { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
+ { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
+ { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
+ { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
+ { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
+ { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
+ { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
+ { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
+ { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
+ { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
+ { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
+ { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
+ { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
+ { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
+ { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
+ { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
+ { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
+ { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
+ { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
+ { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
+ { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
+ { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
+ { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
+ { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
+ { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
+ { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
+ { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
+ { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
+ { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
+ { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
+ { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
+ { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
+ { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
+ { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
+ { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
+ { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
+ { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
+ { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
+ { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
+ { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
+ { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
+ { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
+ { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
+ { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
+ { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
+ { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
+ { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
+ { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
+ { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
+ { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
+ { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
+ { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
+ { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
+ { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
+ { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
+ { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
+ { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
+ { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
+ { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
+ { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
+ { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
+ { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
+ { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
+ { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
+ { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
+ { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
+ { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
+ { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
+ { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
+ { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
+ { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
+ { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
+ { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
+ { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
+ { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
+ { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
+ { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
+ { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
+ { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+ { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+ { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
+ { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
+ { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
+ { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
+ { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
+ { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
+ { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
+ { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
+ { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
+ { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
+ { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
+ { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
+ { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
+ { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
+ { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
+ { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
+ { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
+ { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
+ { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
+};
+
+static const u_int32_t ar9285Common[][2] = {
+ { 0x0000000c, 0x00000000 },
+ { 0x00000030, 0x00020045 },
+ { 0x00000034, 0x00000005 },
+ { 0x00000040, 0x00000000 },
+ { 0x00000044, 0x00000008 },
+ { 0x00000048, 0x00000008 },
+ { 0x0000004c, 0x00000010 },
+ { 0x00000050, 0x00000000 },
+ { 0x00000054, 0x0000001f },
+ { 0x00000800, 0x00000000 },
+ { 0x00000804, 0x00000000 },
+ { 0x00000808, 0x00000000 },
+ { 0x0000080c, 0x00000000 },
+ { 0x00000810, 0x00000000 },
+ { 0x00000814, 0x00000000 },
+ { 0x00000818, 0x00000000 },
+ { 0x0000081c, 0x00000000 },
+ { 0x00000820, 0x00000000 },
+ { 0x00000824, 0x00000000 },
+ { 0x00001040, 0x002ffc0f },
+ { 0x00001044, 0x002ffc0f },
+ { 0x00001048, 0x002ffc0f },
+ { 0x0000104c, 0x002ffc0f },
+ { 0x00001050, 0x002ffc0f },
+ { 0x00001054, 0x002ffc0f },
+ { 0x00001058, 0x002ffc0f },
+ { 0x0000105c, 0x002ffc0f },
+ { 0x00001060, 0x002ffc0f },
+ { 0x00001064, 0x002ffc0f },
+ { 0x00001230, 0x00000000 },
+ { 0x00001270, 0x00000000 },
+ { 0x00001038, 0x00000000 },
+ { 0x00001078, 0x00000000 },
+ { 0x000010b8, 0x00000000 },
+ { 0x000010f8, 0x00000000 },
+ { 0x00001138, 0x00000000 },
+ { 0x00001178, 0x00000000 },
+ { 0x000011b8, 0x00000000 },
+ { 0x000011f8, 0x00000000 },
+ { 0x00001238, 0x00000000 },
+ { 0x00001278, 0x00000000 },
+ { 0x000012b8, 0x00000000 },
+ { 0x000012f8, 0x00000000 },
+ { 0x00001338, 0x00000000 },
+ { 0x00001378, 0x00000000 },
+ { 0x000013b8, 0x00000000 },
+ { 0x000013f8, 0x00000000 },
+ { 0x00001438, 0x00000000 },
+ { 0x00001478, 0x00000000 },
+ { 0x000014b8, 0x00000000 },
+ { 0x000014f8, 0x00000000 },
+ { 0x00001538, 0x00000000 },
+ { 0x00001578, 0x00000000 },
+ { 0x000015b8, 0x00000000 },
+ { 0x000015f8, 0x00000000 },
+ { 0x00001638, 0x00000000 },
+ { 0x00001678, 0x00000000 },
+ { 0x000016b8, 0x00000000 },
+ { 0x000016f8, 0x00000000 },
+ { 0x00001738, 0x00000000 },
+ { 0x00001778, 0x00000000 },
+ { 0x000017b8, 0x00000000 },
+ { 0x000017f8, 0x00000000 },
+ { 0x0000103c, 0x00000000 },
+ { 0x0000107c, 0x00000000 },
+ { 0x000010bc, 0x00000000 },
+ { 0x000010fc, 0x00000000 },
+ { 0x0000113c, 0x00000000 },
+ { 0x0000117c, 0x00000000 },
+ { 0x000011bc, 0x00000000 },
+ { 0x000011fc, 0x00000000 },
+ { 0x0000123c, 0x00000000 },
+ { 0x0000127c, 0x00000000 },
+ { 0x000012bc, 0x00000000 },
+ { 0x000012fc, 0x00000000 },
+ { 0x0000133c, 0x00000000 },
+ { 0x0000137c, 0x00000000 },
+ { 0x000013bc, 0x00000000 },
+ { 0x000013fc, 0x00000000 },
+ { 0x0000143c, 0x00000000 },
+ { 0x0000147c, 0x00000000 },
+ { 0x00004030, 0x00000002 },
+ { 0x0000403c, 0x00000002 },
+ { 0x00004024, 0x0000001f },
+ { 0x00004060, 0x00000000 },
+ { 0x00004064, 0x00000000 },
+ { 0x00007010, 0x00000031 },
+ { 0x00007034, 0x00000002 },
+ { 0x00007038, 0x000004c2 },
+ { 0x00008004, 0x00000000 },
+ { 0x00008008, 0x00000000 },
+ { 0x0000800c, 0x00000000 },
+ { 0x00008018, 0x00000700 },
+ { 0x00008020, 0x00000000 },
+ { 0x00008038, 0x00000000 },
+ { 0x0000803c, 0x00000000 },
+ { 0x00008048, 0x00000000 },
+ { 0x00008054, 0x00000000 },
+ { 0x00008058, 0x00000000 },
+ { 0x0000805c, 0x000fc78f },
+ { 0x00008060, 0x0000000f },
+ { 0x00008064, 0x00000000 },
+ { 0x00008070, 0x00000000 },
+ { 0x000080c0, 0x2a80001a },
+ { 0x000080c4, 0x05dc01e0 },
+ { 0x000080c8, 0x1f402710 },
+ { 0x000080cc, 0x01f40000 },
+ { 0x000080d0, 0x00001e00 },
+ { 0x000080d4, 0x00000000 },
+ { 0x000080d8, 0x00400000 },
+ { 0x000080e0, 0xffffffff },
+ { 0x000080e4, 0x0000ffff },
+ { 0x000080e8, 0x003f3f3f },
+ { 0x000080ec, 0x00000000 },
+ { 0x000080f0, 0x00000000 },
+ { 0x000080f4, 0x00000000 },
+ { 0x000080f8, 0x00000000 },
+ { 0x000080fc, 0x00020000 },
+ { 0x00008100, 0x00020000 },
+ { 0x00008104, 0x00000001 },
+ { 0x00008108, 0x00000052 },
+ { 0x0000810c, 0x00000000 },
+ { 0x00008110, 0x00000168 },
+ { 0x00008118, 0x000100aa },
+ { 0x0000811c, 0x00003210 },
+ { 0x00008120, 0x08f04800 },
+ { 0x00008124, 0x00000000 },
+ { 0x00008128, 0x00000000 },
+ { 0x0000812c, 0x00000000 },
+ { 0x00008130, 0x00000000 },
+ { 0x00008134, 0x00000000 },
+ { 0x00008138, 0x00000000 },
+ { 0x0000813c, 0x00000000 },
+ { 0x00008144, 0x00000000 },
+ { 0x00008168, 0x00000000 },
+ { 0x0000816c, 0x00000000 },
+ { 0x00008170, 0x32143320 },
+ { 0x00008174, 0xfaa4fa50 },
+ { 0x00008178, 0x00000100 },
+ { 0x0000817c, 0x00000000 },
+ { 0x000081c0, 0x00000000 },
+ { 0x000081d0, 0x00003210 },
+ { 0x000081ec, 0x00000000 },
+ { 0x000081f0, 0x00000000 },
+ { 0x000081f4, 0x00000000 },
+ { 0x000081f8, 0x00000000 },
+ { 0x000081fc, 0x00000000 },
+ { 0x00008200, 0x00000000 },
+ { 0x00008204, 0x00000000 },
+ { 0x00008208, 0x00000000 },
+ { 0x0000820c, 0x00000000 },
+ { 0x00008210, 0x00000000 },
+ { 0x00008214, 0x00000000 },
+ { 0x00008218, 0x00000000 },
+ { 0x0000821c, 0x00000000 },
+ { 0x00008220, 0x00000000 },
+ { 0x00008224, 0x00000000 },
+ { 0x00008228, 0x00000000 },
+ { 0x0000822c, 0x00000000 },
+ { 0x00008230, 0x00000000 },
+ { 0x00008234, 0x00000000 },
+ { 0x00008238, 0x00000000 },
+ { 0x0000823c, 0x00000000 },
+ { 0x00008240, 0x00100000 },
+ { 0x00008244, 0x0010f400 },
+ { 0x00008248, 0x00000100 },
+ { 0x0000824c, 0x0001e800 },
+ { 0x00008250, 0x00000000 },
+ { 0x00008254, 0x00000000 },
+ { 0x00008258, 0x00000000 },
+ { 0x0000825c, 0x400000ff },
+ { 0x00008260, 0x00080922 },
+ { 0x00008264, 0xa8a00010 },
+ { 0x00008270, 0x00000000 },
+ { 0x00008274, 0x40000000 },
+ { 0x00008278, 0x003e4180 },
+ { 0x0000827c, 0x00000000 },
+ { 0x00008284, 0x0000002c },
+ { 0x00008288, 0x0000002c },
+ { 0x0000828c, 0x00000000 },
+ { 0x00008294, 0x00000000 },
+ { 0x00008298, 0x00000000 },
+ { 0x0000829c, 0x00000000 },
+ { 0x00008300, 0x00000040 },
+ { 0x00008314, 0x00000000 },
+ { 0x00008328, 0x00000000 },
+ { 0x0000832c, 0x00000001 },
+ { 0x00008330, 0x00000302 },
+ { 0x00008334, 0x00000e00 },
+ { 0x00008338, 0x00000000 },
+ { 0x0000833c, 0x00000000 },
+ { 0x00008340, 0x00010380 },
+ { 0x00008344, 0x00481043 },
+ { 0x00009808, 0x00000000 },
+ { 0x0000980c, 0xafe68e30 },
+ { 0x00009810, 0xfd14e000 },
+ { 0x00009814, 0x9c0a9f6b },
+ { 0x0000981c, 0x00000000 },
+ { 0x0000982c, 0x0000a000 },
+ { 0x00009830, 0x00000000 },
+ { 0x0000983c, 0x00200400 },
+ { 0x0000984c, 0x0040233c },
+ { 0x00009854, 0x00000044 },
+ { 0x00009900, 0x00000000 },
+ { 0x00009904, 0x00000000 },
+ { 0x00009908, 0x00000000 },
+ { 0x0000990c, 0x00000000 },
+ { 0x00009910, 0x01002310 },
+ { 0x0000991c, 0x10000fff },
+ { 0x00009920, 0x04900000 },
+ { 0x00009928, 0x00000001 },
+ { 0x0000992c, 0x00000004 },
+ { 0x00009934, 0x1e1f2022 },
+ { 0x00009938, 0x0a0b0c0d },
+ { 0x0000993c, 0x00000000 },
+ { 0x00009940, 0x14750604 },
+ { 0x00009948, 0x9280c00a },
+ { 0x0000994c, 0x00020028 },
+ { 0x00009954, 0x5f3ca3de },
+ { 0x00009958, 0x2108ecff },
+ { 0x00009968, 0x000003ce },
+ { 0x00009970, 0x1927b515 },
+ { 0x00009974, 0x00000000 },
+ { 0x00009978, 0x00000001 },
+ { 0x0000997c, 0x00000000 },
+ { 0x00009980, 0x00000000 },
+ { 0x00009984, 0x00000000 },
+ { 0x00009988, 0x00000000 },
+ { 0x0000998c, 0x00000000 },
+ { 0x00009990, 0x00000000 },
+ { 0x00009994, 0x00000000 },
+ { 0x00009998, 0x00000000 },
+ { 0x0000999c, 0x00000000 },
+ { 0x000099a0, 0x00000000 },
+ { 0x000099a4, 0x00000001 },
+ { 0x000099a8, 0x201fff00 },
+ { 0x000099ac, 0x2def0a00 },
+ { 0x000099b0, 0x03051000 },
+ { 0x000099b4, 0x00000820 },
+ { 0x000099dc, 0x00000000 },
+ { 0x000099e0, 0x00000000 },
+ { 0x000099e4, 0xaaaaaaaa },
+ { 0x000099e8, 0x3c466478 },
+ { 0x000099ec, 0x0cc80caa },
+ { 0x000099f0, 0x00000000 },
+ { 0x0000a208, 0x803e6788 },
+ { 0x0000a210, 0x4080a333 },
+ { 0x0000a214, 0x00206c10 },
+ { 0x0000a218, 0x009c4060 },
+ { 0x0000a220, 0x01834061 },
+ { 0x0000a224, 0x00000400 },
+ { 0x0000a228, 0x000003b5 },
+ { 0x0000a22c, 0x00000000 },
+ { 0x0000a234, 0x20202020 },
+ { 0x0000a238, 0x20202020 },
+ { 0x0000a244, 0x00000000 },
+ { 0x0000a248, 0xfffffffc },
+ { 0x0000a24c, 0x00000000 },
+ { 0x0000a254, 0x00000000 },
+ { 0x0000a258, 0x0ccb5380 },
+ { 0x0000a25c, 0x15151501 },
+ { 0x0000a260, 0xdfa90f01 },
+ { 0x0000a268, 0x00000000 },
+ { 0x0000a26c, 0x0ebae9e6 },
+ { 0x0000d270, 0x0d820820 },
+ { 0x0000a278, 0x39ce739c },
+ { 0x0000a27c, 0x050e039c },
+ { 0x0000d35c, 0x07ffffef },
+ { 0x0000d360, 0x0fffffe7 },
+ { 0x0000d364, 0x17ffffe5 },
+ { 0x0000d368, 0x1fffffe4 },
+ { 0x0000d36c, 0x37ffffe3 },
+ { 0x0000d370, 0x3fffffe3 },
+ { 0x0000d374, 0x57ffffe3 },
+ { 0x0000d378, 0x5fffffe2 },
+ { 0x0000d37c, 0x7fffffe2 },
+ { 0x0000d380, 0x7f3c7bba },
+ { 0x0000d384, 0xf3307ff0 },
+ { 0x0000a388, 0x0c000000 },
+ { 0x0000a38c, 0x20202020 },
+ { 0x0000a390, 0x20202020 },
+ { 0x0000a394, 0x39ce739c },
+ { 0x0000a398, 0x0000039c },
+ { 0x0000a39c, 0x00000001 },
+ { 0x0000a3a0, 0x00000000 },
+ { 0x0000a3a4, 0x00000000 },
+ { 0x0000a3a8, 0x00000000 },
+ { 0x0000a3ac, 0x00000000 },
+ { 0x0000a3b0, 0x00000000 },
+ { 0x0000a3b4, 0x00000000 },
+ { 0x0000a3b8, 0x00000000 },
+ { 0x0000a3bc, 0x00000000 },
+ { 0x0000a3c0, 0x00000000 },
+ { 0x0000a3c4, 0x00000000 },
+ { 0x0000a3cc, 0x20202020 },
+ { 0x0000a3d0, 0x20202020 },
+ { 0x0000a3d4, 0x20202020 },
+ { 0x0000a3dc, 0x39ce739c },
+ { 0x0000a3e0, 0x0000039c },
+ { 0x0000a3e4, 0x00000000 },
+ { 0x0000a3e8, 0x18c43433 },
+ { 0x0000a3ec, 0x00f70081 },
+ { 0x00007800, 0x00140000 },
+ { 0x00007804, 0x0e4548d8 },
+ { 0x00007808, 0x54214514 },
+ { 0x0000780c, 0x02025820 },
+ { 0x00007810, 0x71c0d388 },
+ { 0x00007814, 0x924934a8 },
+ { 0x0000781c, 0x00000000 },
+ { 0x00007820, 0x00000c04 },
+ { 0x00007824, 0x00d86fff },
+ { 0x00007828, 0x26d2491b },
+ { 0x0000782c, 0x6e36d97b },
+ { 0x00007830, 0xedb6d96c },
+ { 0x00007834, 0x71400086 },
+ { 0x00007838, 0xfac68800 },
+ { 0x0000783c, 0x0001fffe },
+ { 0x00007840, 0xffeb1a20 },
+ { 0x00007844, 0x000c0db6 },
+ { 0x00007848, 0x6db61b6f },
+ { 0x0000784c, 0x6d9b66db },
+ { 0x00007850, 0x6d8c6dba },
+ { 0x00007854, 0x00040000 },
+ { 0x00007858, 0xdb003012 },
+ { 0x0000785c, 0x04924914 },
+ { 0x00007860, 0x21084210 },
+ { 0x00007864, 0xf7d7ffde },
+ { 0x00007868, 0xc2034080 },
+ { 0x0000786c, 0x48609eb4 },
+ { 0x00007870, 0x10142c00 },
+};
+
+static const u_int32_t ar9285PciePhy_clkreq_always_on_L1[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01dcffd },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
+
+static const u_int32_t ar9285PciePhy_clkreq_off_L1[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01dcffc },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9285_attach.c b/sys/external/isc/atheros_hal/dist/ar5416/ar9285_attach.c
new file mode 100644
index 0000000..ef8c955
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9285_attach.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
+
+#include "ar5416/ar9280.h"
+#include "ar5416/ar9285.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#include "ar5416/ar9285.ini"
+#include "ar5416/ar9285v2.ini"
+#include "ar5416/ar9280v2.ini" /* XXX ini for tx/rx gain */
+
+static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
+ .calName = "IQ", .calType = IQ_MISMATCH_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = PER_MAX_LOG_COUNT,
+ .calCollect = ar5416IQCalCollect,
+ .calPostProc = ar5416IQCalibration
+};
+static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
+ .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = PER_MIN_LOG_COUNT,
+ .calCollect = ar5416AdcGainCalCollect,
+ .calPostProc = ar5416AdcGainCalibration
+};
+static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
+ .calName = "ADC DC", .calType = ADC_DC_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = PER_MIN_LOG_COUNT,
+ .calCollect = ar5416AdcDcCalCollect,
+ .calPostProc = ar5416AdcDcCalibration
+};
+static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
+ .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
+ .calNumSamples = MIN_CAL_SAMPLES,
+ .calCountMax = INIT_LOG_COUNT,
+ .calCollect = ar5416AdcDcCalCollect,
+ .calPostProc = ar5416AdcDcCalibration
+};
+
+static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
+static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
+static void ar9285WriteIni(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
+
+static void
+ar9285AniSetup(struct ath_hal *ah)
+{
+ /* NB: disable ANI for reliable RIFS rx */
+ ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
+}
+
+/*
+ * Attach for an AR9285 part.
+ */
+static struct ath_hal *
+ar9285Attach(uint16_t devid, HAL_SOFTC sc,
+ HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+ struct ath_hal_9285 *ahp9285;
+ struct ath_hal_5212 *ahp;
+ struct ath_hal *ah;
+ uint32_t val;
+ HAL_STATUS ecode;
+ HAL_BOOL rfStatus;
+
+ HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+ __func__, sc, (void*) st, (void*) sh);
+
+ /* NB: memory is returned zero'd */
+ ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
+ if (ahp9285 == AH_NULL) {
+ HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+ "%s: cannot allocate memory for state block\n", __func__);
+ *status = HAL_ENOMEM;
+ return AH_NULL;
+ }
+ ahp = AH5212(ahp9285);
+ ah = &ahp->ah_priv.h;
+
+ ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
+
+ /* XXX override with 9285 specific state */
+ /* override 5416 methods for our needs */
+ ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
+ ah->ah_configPCIE = ar9285ConfigPCIE;
+ ah->ah_setTxPower = ar9285SetTransmitPower;
+ ah->ah_setBoardValues = ar9285SetBoardValues;
+
+ AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
+ AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
+ AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
+ AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
+ AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
+
+ AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
+ AH5416(ah)->ah_writeIni = ar9285WriteIni;
+ AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
+ AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
+
+ ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
+
+ if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
+ /* reset chip */
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
+ __func__);
+ ecode = HAL_EIO;
+ goto bad;
+ }
+
+ if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
+ __func__);
+ ecode = HAL_EIO;
+ goto bad;
+ }
+ /* Read Revisions from Chips before taking out of reset */
+ val = OS_REG_READ(ah, AR_SREV);
+ HALDEBUG(ah, HAL_DEBUG_ATTACH,
+ "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
+ __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
+ MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
+ /* NB: include chip type to differentiate from pre-Sowl versions */
+ AH_PRIVATE(ah)->ah_macVersion =
+ (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
+ AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
+ AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
+
+ /* setup common ini data; rf backends handle remainder */
+ if (AR_SREV_KITE_12_OR_LATER(ah)) {
+ HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
+ HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
+ HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
+ ar9285PciePhy_clkreq_always_on_L1_v2, 2);
+ } else {
+ HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
+ HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
+ HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
+ ar9285PciePhy_clkreq_always_on_L1, 2);
+ }
+ ar5416AttachPCIE(ah);
+
+ ecode = ath_hal_v4kEepromAttach(ah);
+ if (ecode != HAL_OK)
+ goto bad;
+
+ if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
+ __func__);
+ ecode = HAL_EIO;
+ goto bad;
+ }
+
+ AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+ if (!ar5212ChipTest(ah)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+ __func__);
+ ecode = HAL_ESELFTEST;
+ goto bad;
+ }
+
+ /*
+ * Set correct Baseband to analog shift
+ * setting to access analog chips.
+ */
+ OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+ /* Read Radio Chip Rev Extract */
+ AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
+ switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+ case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
+ case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
+ break;
+ default:
+ if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
+ AH_PRIVATE(ah)->ah_analog5GhzRev =
+ AR_RAD5133_SREV_MAJOR;
+ break;
+ }
+#ifdef AH_DEBUG
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: 5G Radio Chip Rev 0x%02X is not supported by "
+ "this driver\n", __func__,
+ AH_PRIVATE(ah)->ah_analog5GhzRev);
+ ecode = HAL_ENOTSUPP;
+ goto bad;
+#endif
+ }
+ rfStatus = ar9285RfAttach(ah, &ecode);
+ if (!rfStatus) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+ __func__, ecode);
+ goto bad;
+ }
+
+ HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
+ 6);
+ /* setup txgain table */
+ switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
+ case AR5416_EEP_TXGAIN_HIGH_POWER:
+ HAL_INI_INIT(&ahp9285->ah_ini_txgain,
+ ar9285Modes_high_power_tx_gain_v2, 6);
+ break;
+ case AR5416_EEP_TXGAIN_ORIG:
+ HAL_INI_INIT(&ahp9285->ah_ini_txgain,
+ ar9285Modes_original_tx_gain_v2, 6);
+ break;
+ default:
+ HALASSERT(AH_FALSE);
+ goto bad; /* XXX ? try to continue */
+ }
+
+ /*
+ * Got everything we need now to setup the capabilities.
+ */
+ if (!ar9285FillCapabilityInfo(ah)) {
+ ecode = HAL_EEREAD;
+ goto bad;
+ }
+
+ ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+ if (ecode != HAL_OK) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: error getting mac address from EEPROM\n", __func__);
+ goto bad;
+ }
+ /* XXX How about the serial number ? */
+ /* Read Reg Domain */
+ AH_PRIVATE(ah)->ah_currentRD =
+ ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
+
+ /*
+ * ah_miscMode is populated by ar5416FillCapabilityInfo()
+ * starting from griffin. Set here to make sure that
+ * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
+ * placed into hardware.
+ */
+ if (ahp->ah_miscMode != 0)
+ OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+
+ ar9285AniSetup(ah); /* Anti Noise Immunity */
+ ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
+
+ HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+ return ah;
+bad:
+ if (ah != AH_NULL)
+ ah->ah_detach(ah);
+ if (status)
+ *status = ecode;
+ return AH_NULL;
+}
+
+static void
+ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
+{
+ if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
+ ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
+ OS_DELAY(1000);
+ OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+ OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
+ }
+}
+
+static void
+ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ u_int modesIndex, freqIndex;
+ int regWrites = 0;
+
+ /* Setup the indices for the next set of register array writes */
+ /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
+ freqIndex = 2;
+ if (IEEE80211_IS_CHAN_HT40(chan))
+ modesIndex = 3;
+ else if (IEEE80211_IS_CHAN_108G(chan))
+ modesIndex = 5;
+ else
+ modesIndex = 4;
+
+ /* Set correct Baseband to analog shift setting to access analog chips. */
+ OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+ OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
+ regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
+ modesIndex, regWrites);
+ if (AR_SREV_KITE_12_OR_LATER(ah)) {
+ regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
+ modesIndex, regWrites);
+ }
+ regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
+ 1, regWrites);
+
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ * Return failure if capabilities are to come from EEPROM and
+ * cannot be read.
+ */
+static HAL_BOOL
+ar9285FillCapabilityInfo(struct ath_hal *ah)
+{
+ HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+ if (!ar5416FillCapabilityInfo(ah))
+ return AH_FALSE;
+ pCap->halNumGpioPins = 12;
+ pCap->halWowSupport = AH_TRUE;
+ pCap->halWowMatchPatternExact = AH_TRUE;
+#if 0
+ pCap->halWowMatchPatternDword = AH_TRUE;
+#endif
+ pCap->halCSTSupport = AH_TRUE;
+ pCap->halRifsRxSupport = AH_TRUE;
+ pCap->halRifsTxSupport = AH_TRUE;
+ pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
+ pCap->halExtChanDfsSupport = AH_TRUE;
+#if 0
+ /* XXX bluetooth */
+ pCap->halBtCoexSupport = AH_TRUE;
+#endif
+ pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
+#if 0
+ pCap->hal4kbSplitTransSupport = AH_FALSE;
+#endif
+ pCap->halRxStbcSupport = 1;
+ pCap->halTxStbcSupport = 1;
+
+ return AH_TRUE;
+}
+
+HAL_BOOL
+ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
+{
+#define ANTENNA0_CHAINMASK 0x1
+#define ANTENNA1_CHAINMASK 0x2
+ struct ath_hal_5416 *ahp = AH5416(ah);
+
+ /* Antenna selection is done by setting the tx/rx chainmasks approp. */
+ switch (settings) {
+ case HAL_ANT_FIXED_A:
+ /* Enable first antenna only */
+ ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
+ ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
+ break;
+ case HAL_ANT_FIXED_B:
+ /* Enable second antenna only, after checking capability */
+ if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
+ ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
+ ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
+ break;
+ case HAL_ANT_VARIABLE:
+ /* Restore original chainmask settings */
+ /* XXX */
+ ahp->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
+ ahp->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
+ break;
+ }
+ return AH_TRUE;
+#undef ANTENNA0_CHAINMASK
+#undef ANTENNA1_CHAINMASK
+}
+
+static const char*
+ar9285Probe(uint16_t vendorid, uint16_t devid)
+{
+ if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
+ return "Atheros 9285";
+ return AH_NULL;
+}
+AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9285_reset.c b/sys/external/isc/atheros_hal/dist/ar5416/ar9285_reset.c
new file mode 100644
index 0000000..8c2de10
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9285_reset.c
@@ -0,0 +1,951 @@
+/*
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and
+ * supports only 2Ghz operation.
+ */
+
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ah_eeprom_v14.h"
+#include "ah_eeprom_v4k.h"
+
+#include "ar5416/ar9285.h"
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
+#define EEP_MINOR(_ah) \
+ (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
+#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
+#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
+
+/* Additional Time delay to wait after activiting the Base band */
+#define BASE_ACTIVATE_DELAY 100 /* 100 usec */
+#define PLL_SETTLE_DELAY 300 /* 300 usec */
+#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
+
+static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah,
+ struct ar5416eeprom_4k *pEepData,
+ const struct ieee80211_channel *chan, int16_t *ratesArray,
+ uint16_t cfgCtl, uint16_t AntennaReduction,
+ uint16_t twiceMaxRegulatoryPower,
+ uint16_t powerLimit);
+static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah,
+ struct ar5416eeprom_4k *pEepData,
+ const struct ieee80211_channel *chan,
+ int16_t *pTxPowerIndexOffset);
+static int16_t interpolate(uint16_t target, uint16_t srcLeft,
+ uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
+static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *,
+ uint16_t, uint8_t *);
+static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet,
+ uint8_t * bChans, uint16_t availPiers,
+ uint16_t tPdGainOverlap, int16_t *pMinCalPower,
+ uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
+ uint16_t numXpdGains);
+static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
+ uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
+static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *);
+
+/* XXX gag, this is sick */
+typedef enum Ar5416_Rates {
+ rate6mb, rate9mb, rate12mb, rate18mb,
+ rate24mb, rate36mb, rate48mb, rate54mb,
+ rate1l, rate2l, rate2s, rate5_5l,
+ rate5_5s, rate11l, rate11s, rateXr,
+ rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
+ rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
+ rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
+ rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
+ rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
+ Ar5416RateSize
+} AR5416_RATES;
+
+HAL_BOOL
+ar9285SetTransmitPower(struct ath_hal *ah,
+ const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
+{
+#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
+#define N(a) (sizeof (a) / sizeof (a[0]))
+
+ MODAL_EEP4K_HEADER *pModal;
+ struct ath_hal_5212 *ahp = AH5212(ah);
+ int16_t ratesArray[Ar5416RateSize];
+ int16_t txPowerIndexOffset = 0;
+ uint8_t ht40PowerIncForPdadc = 2;
+ int i;
+
+ uint16_t cfgCtl;
+ uint16_t powerLimit;
+ uint16_t twiceAntennaReduction;
+ uint16_t twiceMaxRegulatoryPower;
+ int16_t maxPower;
+ HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+ struct ar5416eeprom_4k *pEepData = &ee->ee_base;
+
+ HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
+
+ /* Setup info for the actual eeprom */
+ OS_MEMZERO(ratesArray, sizeof(ratesArray));
+ cfgCtl = ath_hal_getctl(ah, chan);
+ powerLimit = chan->ic_maxregpower * 2;
+ twiceAntennaReduction = chan->ic_maxantgain;
+ twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
+ pModal = &pEepData->modalHeader;
+ HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
+ __func__,chan->ic_freq, cfgCtl );
+
+ if (IS_EEP_MINOR_V2(ah)) {
+ ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
+ }
+
+ if (!ar9285SetPowerPerRateTable(ah, pEepData, chan,
+ &ratesArray[0],cfgCtl,
+ twiceAntennaReduction,
+ twiceMaxRegulatoryPower, powerLimit)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: unable to set tx power per rate table\n", __func__);
+ return AH_FALSE;
+ }
+
+ if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
+ __func__);
+ return AH_FALSE;
+ }
+
+ maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
+ maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
+
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
+ }
+
+ ahp->ah_tx6PowerInHalfDbm = maxPower;
+ AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
+ ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
+
+ /*
+ * txPowerIndexOffset is set by the SetPowerTable() call -
+ * adjust the rate table (0 offset if rates EEPROM not loaded)
+ */
+ for (i = 0; i < N(ratesArray); i++) {
+ ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
+ if (ratesArray[i] > AR5416_MAX_RATE_POWER)
+ ratesArray[i] = AR5416_MAX_RATE_POWER;
+ ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
+ }
+
+#ifdef AH_EEPROM_DUMP
+ ar5416PrintPowerPerRate(ah, ratesArray);
+#endif
+
+ /* Write the OFDM power per rate set */
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
+ POW_SM(ratesArray[rate18mb], 24)
+ | POW_SM(ratesArray[rate12mb], 16)
+ | POW_SM(ratesArray[rate9mb], 8)
+ | POW_SM(ratesArray[rate6mb], 0)
+ );
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
+ POW_SM(ratesArray[rate54mb], 24)
+ | POW_SM(ratesArray[rate48mb], 16)
+ | POW_SM(ratesArray[rate36mb], 8)
+ | POW_SM(ratesArray[rate24mb], 0)
+ );
+
+ /* Write the CCK power per rate set */
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
+ POW_SM(ratesArray[rate2s], 24)
+ | POW_SM(ratesArray[rate2l], 16)
+ | POW_SM(ratesArray[rateXr], 8) /* XR target power */
+ | POW_SM(ratesArray[rate1l], 0)
+ );
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
+ POW_SM(ratesArray[rate11s], 24)
+ | POW_SM(ratesArray[rate11l], 16)
+ | POW_SM(ratesArray[rate5_5s], 8)
+ | POW_SM(ratesArray[rate5_5l], 0)
+ );
+ HALDEBUG(ah, HAL_DEBUG_RESET,
+ "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
+ __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
+ OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));
+
+ /* Write the HT20 power per rate set */
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
+ POW_SM(ratesArray[rateHt20_3], 24)
+ | POW_SM(ratesArray[rateHt20_2], 16)
+ | POW_SM(ratesArray[rateHt20_1], 8)
+ | POW_SM(ratesArray[rateHt20_0], 0)
+ );
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
+ POW_SM(ratesArray[rateHt20_7], 24)
+ | POW_SM(ratesArray[rateHt20_6], 16)
+ | POW_SM(ratesArray[rateHt20_5], 8)
+ | POW_SM(ratesArray[rateHt20_4], 0)
+ );
+
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ /* Write the HT40 power per rate set */
+ /* Correct PAR difference between HT40 and HT20/LEGACY */
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
+ POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
+ | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
+ | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
+ | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
+ );
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
+ POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
+ | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
+ | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
+ | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
+ );
+ /* Write the Dup/Ext 40 power per rate set */
+ OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
+ POW_SM(ratesArray[rateExtOfdm], 24)
+ | POW_SM(ratesArray[rateExtCck], 16)
+ | POW_SM(ratesArray[rateDupOfdm], 8)
+ | POW_SM(ratesArray[rateDupCck], 0)
+ );
+ }
+
+ return AH_TRUE;
+#undef POW_SM
+#undef N
+}
+
+HAL_BOOL
+ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
+ const struct ar5416eeprom_4k *eep = &ee->ee_base;
+ const MODAL_EEP4K_HEADER *pModal;
+ int i, regChainOffset;
+ uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
+
+ HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
+ pModal = &eep->modalHeader;
+
+ /* NB: workaround for eeprom versions <= 14.2 */
+ txRxAttenLocal = 23;
+
+ OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
+ for (i = 0; i < AR5416_4K_MAX_CHAINS; i++) {
+ if (AR_SREV_MERLIN(ah)) {
+ if (i >= 2) break;
+ }
+ if (AR_SREV_OWL_20_OR_LATER(ah) &&
+ (AH5416(ah)->ah_rx_chainmask == 0x5 ||
+ AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
+ /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
+ * only chains 0 and 2 populated
+ */
+ regChainOffset = (i == 1) ? 0x2000 : 0x1000;
+ } else {
+ regChainOffset = i * 0x1000;
+ }
+
+ OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
+ OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
+ (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
+ ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
+ SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
+ SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
+
+ /*
+ * Large signal upgrade.
+ * XXX update
+ */
+
+ if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
+ OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
+ (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
+ SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
+ AR_PHY_RXGAIN_TXRX_ATTEN));
+
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
+ (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
+ SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
+ }
+ }
+
+ OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
+ OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
+ OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
+ OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
+ SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
+ | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
+ | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
+ | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
+
+ OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
+
+ OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
+ pModal->thresh62);
+ OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
+ pModal->thresh62);
+
+ /* Minor Version Specific application */
+ if (IS_EEP_MINOR_V2(ah)) {
+ OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
+ OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
+ }
+
+ if (IS_EEP_MINOR_V3(ah)) {
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ /* Overwrite switch settling with HT40 value */
+ OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
+ }
+
+ if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
+ ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
+ /* Reg Offsets are swapped for logical mapping */
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+ SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+ SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+ SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+ SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+ } else {
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+ SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+ SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+ SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+ OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+ SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+ }
+ OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
+ OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
+ }
+ return AH_TRUE;
+}
+
+/*
+ * Helper functions common for AP/CB/XB
+ */
+
+static HAL_BOOL
+ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
+ const struct ieee80211_channel *chan,
+ int16_t *ratesArray, uint16_t cfgCtl,
+ uint16_t AntennaReduction,
+ uint16_t twiceMaxRegulatoryPower,
+ uint16_t powerLimit)
+{
+#define N(a) (sizeof(a)/sizeof(a[0]))
+/* Local defines to distinguish between extension and control CTL's */
+#define EXT_ADDITIVE (0x8000)
+#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
+#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
+
+ uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+ int i;
+ int16_t twiceLargestAntenna;
+ CAL_CTL_DATA_4K *rep;
+ CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
+ CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
+ CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
+ int16_t scaledPower, minCtlPower;
+
+#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
+ static const uint16_t ctlModesFor11g[] = {
+ CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+ };
+ const uint16_t *pCtlMode;
+ uint16_t numCtlModes, ctlMode, freq;
+ CHAN_CENTERS centers;
+
+ ar5416GetChannelCenters(ah, chan, &centers);
+
+ /* Compute TxPower reduction due to Antenna Gain */
+
+ twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
+ twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
+
+ /* XXX setup for 5212 use (really used?) */
+ ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);
+
+ /*
+ * scaledPower is the minimum of the user input power level and
+ * the regulatory allowed power level
+ */
+ scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
+
+ /* Get target powers from EEPROM - our baseline for TX Power */
+ /* Setup for CTL modes */
+ numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
+ pCtlMode = ctlModesFor11g;
+
+ ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
+ AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
+ ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
+ AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
+ ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
+ AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
+
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
+
+ ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
+ AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
+ /* Get target powers for extension channels */
+ ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
+ AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
+ ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
+ AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
+ }
+
+ /*
+ * For MIMO, need to apply regulatory caps individually across dynamically
+ * running modes: CCK, OFDM, HT20, HT40
+ *
+ * The outer loop walks through each possible applicable runtime mode.
+ * The inner loop walks through each ctlIndex entry in EEPROM.
+ * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
+ *
+ */
+ for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
+ HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
+ (pCtlMode[ctlMode] == CTL_2GHT40);
+ if (isHt40CtlMode) {
+ freq = centers.ctl_center;
+ } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
+ freq = centers.ext_center;
+ } else {
+ freq = centers.ctl_center;
+ }
+
+ /* walk through each CTL index stored in EEPROM */
+ for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
+ uint16_t twiceMinEdgePower;
+
+ /* compare test group from regulatory channel list with test mode from pCtlMode list */
+ if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
+ (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
+ ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
+ rep = &(pEepData->ctlData[i]);
+ twiceMinEdgePower = ar9285GetMaxEdgePower(freq,
+ rep->ctlEdges[
+ owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]);
+ if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
+ /* Find the minimum of all CTL edge powers that apply to this channel */
+ twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
+ } else {
+ /* specific */
+ twiceMaxEdgePower = twiceMinEdgePower;
+ break;
+ }
+ }
+ }
+ minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
+ /* Apply ctl mode to correct target power set */
+ switch(pCtlMode[ctlMode]) {
+ case CTL_11B:
+ for (i = 0; i < N(targetPowerCck.tPow2x); i++) {
+ targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
+ }
+ break;
+ case CTL_11A:
+ case CTL_11G:
+ for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) {
+ targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
+ }
+ break;
+ case CTL_5GHT20:
+ case CTL_2GHT20:
+ for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
+ targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
+ }
+ break;
+ case CTL_11B_EXT:
+ targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
+ break;
+ case CTL_11G_EXT:
+ targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
+ break;
+ case CTL_5GHT40:
+ case CTL_2GHT40:
+ for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
+ targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
+ }
+ break;
+ default:
+ return AH_FALSE;
+ break;
+ }
+ } /* end ctl mode checking */
+
+ /* Set rates Array from collected data */
+ ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
+ ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
+ ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
+ ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
+ ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
+
+ for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
+ ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
+ }
+
+ ratesArray[rate1l] = targetPowerCck.tPow2x[0];
+ ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
+ ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
+ ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
+ if (IEEE80211_IS_CHAN_HT40(chan)) {
+ for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
+ ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
+ }
+ ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
+ ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
+ ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
+ ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
+ }
+ }
+ return AH_TRUE;
+#undef EXT_ADDITIVE
+#undef CTL_11G_EXT
+#undef CTL_11B_EXT
+#undef SUB_NUM_CTL_MODES_AT_2G_40
+#undef N
+}
+
+/**************************************************************************
+ * fbin2freq
+ *
+ * Get channel value from binary representation held in eeprom
+ * RETURNS: the frequency in MHz
+ */
+static uint16_t
+fbin2freq(uint8_t fbin)
+{
+ /*
+ * Reserved value 0xFF provides an empty definition both as
+ * an fbin and as a frequency - do not convert
+ */
+ if (fbin == AR5416_BCHAN_UNUSED) {
+ return fbin;
+ }
+
+ return (uint16_t)(2300 + fbin);
+}
+
+/*
+ * XXX almost the same as ar5416GetMaxEdgePower.
+ */
+static uint16_t
+ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower)
+{
+ uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+ int i;
+
+ /* Get the edge power */
+ for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
+ /*
+ * If there's an exact channel match or an inband flag set
+ * on the lower channel use the given rdEdgePower
+ */
+ if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) {
+ twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
+ break;
+ } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) {
+ if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
+ twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
+ }
+ /* Leave loop - no more affecting edges possible in this monotonic increasing list */
+ break;
+ }
+ }
+ HALASSERT(twiceMaxEdgePower > 0);
+ return twiceMaxEdgePower;
+}
+
+
+
+static HAL_BOOL
+ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
+ const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
+{
+ CAL_DATA_PER_FREQ_4K *pRawDataset;
+ uint8_t *pCalBChans = AH_NULL;
+ uint16_t pdGainOverlap_t2;
+ static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
+ uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
+ uint16_t numPiers, i, j;
+ int16_t tMinCalPower;
+ uint16_t numXpdGain, xpdMask;
+ uint16_t xpdGainValues[AR5416_4K_NUM_PD_GAINS];
+ uint32_t reg32, regOffset, regChainOffset;
+
+ OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
+
+ xpdMask = pEepData->modalHeader.xpdGain;
+
+ if (IS_EEP_MINOR_V2(ah)) {
+ pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
+ } else {
+ pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
+ }
+
+ pCalBChans = pEepData->calFreqPier2G;
+ numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
+ numXpdGain = 0;
+ /* Calculate the value of xpdgains from the xpdGain Mask */
+ for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+ if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
+ if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) {
+ HALASSERT(0);
+ break;
+ }
+ xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
+ numXpdGain++;
+ }
+ }
+
+ /* Write the detector gain biases and their number */
+ OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
+ ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
+ SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
+ SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
+
+ for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+
+ if (AR_SREV_OWL_20_OR_LATER(ah) &&
+ ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
+ /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
+ * only chains 0 and 2 populated
+ */
+ regChainOffset = (i == 1) ? 0x2000 : 0x1000;
+ } else {
+ regChainOffset = i * 0x1000;
+ }
+
+ if (pEepData->baseEepHeader.txMask & (1 << i)) {
+ pRawDataset = pEepData->calPierData2G[i];
+
+ ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
+ pCalBChans, numPiers,
+ pdGainOverlap_t2,
+ &tMinCalPower, gainBoundaries,
+ pdadcValues, numXpdGain);
+
+ if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
+ /*
+ * Note the pdadc table may not start at 0 dBm power, could be
+ * negative or greater than 0. Need to offset the power
+ * values by the amount of minPower for griffin
+ */
+
+ OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
+ SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
+ SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
+ SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
+ SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
+ SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+ }
+
+ /* Write the power values into the baseband power table */
+ regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
+
+ for (j = 0; j < 32; j++) {
+ reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) |
+ ((pdadcValues[4*j + 1] & 0xFF) << 8) |
+ ((pdadcValues[4*j + 2] & 0xFF) << 16) |
+ ((pdadcValues[4*j + 3] & 0xFF) << 24) ;
+ OS_REG_WRITE(ah, regOffset, reg32);
+
+#ifdef PDADC_DUMP
+ ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
+ i,
+ 4*j, pdadcValues[4*j],
+ 4*j+1, pdadcValues[4*j + 1],
+ 4*j+2, pdadcValues[4*j + 2],
+ 4*j+3, pdadcValues[4*j + 3]);
+#endif
+ regOffset += 4;
+ }
+ }
+ }
+ *pTxPowerIndexOffset = 0;
+
+ return AH_TRUE;
+}
+
+static void
+ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
+ const struct ieee80211_channel *chan,
+ CAL_DATA_PER_FREQ_4K *pRawDataSet,
+ uint8_t * bChans, uint16_t availPiers,
+ uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
+ uint8_t * pPDADCValues, uint16_t numXpdGains)
+{
+
+ int i, j, k;
+ int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
+ uint16_t idxL, idxR, numPiers; /* Pier indexes */
+
+ /* filled out Vpd table for all pdGains (chanL) */
+ static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+ /* filled out Vpd table for all pdGains (chanR) */
+ static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+ /* filled out Vpd table for all pdGains (interpolated) */
+ static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+ uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+ uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS];
+ uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS];
+ int16_t vpdStep;
+ int16_t tmpVal;
+ uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
+ HAL_BOOL match;
+ int16_t minDelta = 0;
+ CHAN_CENTERS centers;
+
+ ar5416GetChannelCenters(ah, chan, &centers);
+
+ /* Trim numPiers for the number of populated channel Piers */
+ for (numPiers = 0; numPiers < availPiers; numPiers++) {
+ if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
+ break;
+ }
+ }
+
+ /* Find pier indexes around the current channel */
+ match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
+ bChans, numPiers, &idxL, &idxR);
+
+ if (match) {
+ /* Directly fill both vpd tables from the matching index */
+ for (i = 0; i < numXpdGains; i++) {
+ minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
+ maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
+ ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i],
+ pRawDataSet[idxL].pwrPdg[i],
+ pRawDataSet[idxL].vpdPdg[i],
+ AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
+ }
+ } else {
+ for (i = 0; i < numXpdGains; i++) {
+ pVpdL = pRawDataSet[idxL].vpdPdg[i];
+ pPwrL = pRawDataSet[idxL].pwrPdg[i];
+ pVpdR = pRawDataSet[idxR].vpdPdg[i];
+ pPwrR = pRawDataSet[idxR].pwrPdg[i];
+
+ /* Start Vpd interpolation from the max of the minimum powers */
+ minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
+
+ /* End Vpd interpolation from the min of the max powers */
+ maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
+ HALASSERT(maxPwrT4[i] > minPwrT4[i]);
+
+ /* Fill pier Vpds */
+ ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL,
+ AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
+ ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR,
+ AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
+
+ /* Interpolate the final vpd */
+ for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
+ vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
+ bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
+ }
+ }
+ }
+ *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
+
+ k = 0; /* index for the final table */
+ for (i = 0; i < numXpdGains; i++) {
+ if (i == (numXpdGains - 1)) {
+ pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
+ } else {
+ pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
+ }
+
+ pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
+
+ /* NB: only applies to owl 1.0 */
+ if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
+ /*
+ * fix the gain delta, but get a delta that can be applied to min to
+ * keep the upper power values accurate, don't think max needs to
+ * be adjusted because should not be at that area of the table?
+ */
+ minDelta = pPdGainBoundaries[0] - 23;
+ pPdGainBoundaries[0] = 23;
+ }
+ else {
+ minDelta = 0;
+ }
+
+ /* Find starting index for this pdGain */
+ if (i == 0) {
+ ss = 0; /* for the first pdGain, start from index 0 */
+ } else {
+ /* need overlap entries extrapolated below. */
+ ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
+ }
+ vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
+ vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+ /*
+ *-ve ss indicates need to extrapolate data below for this pdGain
+ */
+ while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+ tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
+ pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
+ ss++;
+ }
+
+ sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
+ tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
+ maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+ while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+ pPDADCValues[k++] = vpdTableI[i][ss++];
+ }
+
+ vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
+ vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+ /*
+ * for last gain, pdGainBoundary == Pmax_t2, so will
+ * have to extrapolate
+ */
+ if (tgtIndex > maxIndex) { /* need to extrapolate above */
+ while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+ tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
+ (ss - maxIndex +1) * vpdStep));
+ pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
+ ss++;
+ }
+ } /* extrapolated above */
+ } /* for all pdGainUsed */
+
+ /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
+ while (i < AR5416_PD_GAINS_IN_MASK) {
+ pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
+ i++;
+ }
+
+ while (k < AR5416_NUM_PDADC_VALUES) {
+ pPDADCValues[k] = pPDADCValues[k-1];
+ k++;
+ }
+ return;
+}
+/*
+ * XXX same as ar5416FillVpdTable
+ */
+static HAL_BOOL
+ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
+ uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
+{
+ uint16_t i, k;
+ uint8_t currPwr = pwrMin;
+ uint16_t idxL, idxR;
+
+ HALASSERT(pwrMax > pwrMin);
+ for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
+ getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
+ &(idxL), &(idxR));
+ if (idxR < 1)
+ idxR = 1; /* extrapolate below */
+ if (idxL == numIntercepts - 1)
+ idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */
+ if (pPwrList[idxL] == pPwrList[idxR])
+ k = pVpdList[idxL];
+ else
+ k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
+ (pPwrList[idxR] - pPwrList[idxL]) );
+ HALASSERT(k < 256);
+ pRetVpdList[i] = (uint8_t)k;
+ currPwr += 2; /* half dB steps */
+ }
+
+ return AH_TRUE;
+}
+static int16_t
+interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+ int16_t targetLeft, int16_t targetRight)
+{
+ int16_t rv;
+
+ if (srcRight == srcLeft) {
+ rv = targetLeft;
+ } else {
+ rv = (int16_t)( ((target - srcLeft) * targetRight +
+ (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
+ }
+ return rv;
+}
+
+HAL_BOOL
+getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
+ uint16_t *indexL, uint16_t *indexR)
+{
+ uint16_t i;
+
+ /*
+ * Check first and last elements for beyond ordered array cases.
+ */
+ if (target <= pList[0]) {
+ *indexL = *indexR = 0;
+ return AH_TRUE;
+ }
+ if (target >= pList[listSize-1]) {
+ *indexL = *indexR = (uint16_t)(listSize - 1);
+ return AH_TRUE;
+ }
+
+ /* look for value being near or between 2 values in list */
+ for (i = 0; i < listSize - 1; i++) {
+ /*
+ * If value is close to the current value of the list
+ * then target is not between values, it is one of the values
+ */
+ if (pList[i] == target) {
+ *indexL = *indexR = i;
+ return AH_TRUE;
+ }
+ /*
+ * Look for value being between current value and next value
+ * if so return these 2 values
+ */
+ if (target < pList[i + 1]) {
+ *indexL = i;
+ *indexR = (uint16_t)(i + 1);
+ return AH_FALSE;
+ }
+ }
+ HALASSERT(0);
+ *indexL = *indexR = 0;
+ return AH_FALSE;
+}
diff --git a/sys/external/isc/atheros_hal/dist/ar5416/ar9285v2.ini b/sys/external/isc/atheros_hal/dist/ar5416/ar9285v2.ini
new file mode 100644
index 0000000..2a9de1d
--- /dev/null
+++ b/sys/external/isc/atheros_hal/dist/ar5416/ar9285v2.ini
@@ -0,0 +1,746 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
+static const u_int32_t ar9285Modes_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+ { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+ { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+ { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
+ { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
+ { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
+ { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
+ { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+ { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+ { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
+ { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+ { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+ { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+ { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
+ { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
+ { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
+ { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
+ { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
+ { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
+ { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
+ { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
+ { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+ { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
+ { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
+ { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
+ { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
+ { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
+ { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
+ { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
+ { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
+ { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
+ { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+ { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
+ { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+ { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+ { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
+ { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
+ { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
+ { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
+ { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
+ { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
+ { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
+ { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
+ { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
+ { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
+ { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
+ { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
+ { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
+ { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
+ { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
+ { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
+ { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
+ { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
+ { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
+ { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
+ { 0x00009a50, 0x00000000, 0x00000000, 0x00058220, 0x00058220, 0x00000000 },
+ { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
+ { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
+ { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
+ { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
+ { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
+ { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
+ { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
+ { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
+ { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
+ { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
+ { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
+ { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
+ { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
+ { 0x00009a88, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
+ { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
+ { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
+ { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
+ { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
+ { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
+ { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
+ { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
+ { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
+ { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
+ { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
+ { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
+ { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
+ { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
+ { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
+ { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
+ { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
+ { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
+ { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
+ { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
+ { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
+ { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
+ { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
+ { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
+ { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
+ { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
+ { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
+ { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
+ { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
+ { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
+ { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
+ { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
+ { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
+ { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
+ { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
+ { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
+ { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
+ { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
+ { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
+ { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
+ { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
+ { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
+ { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
+ { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
+ { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
+ { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
+ { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
+ { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
+ { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
+ { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
+ { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
+ { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
+ { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
+ { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
+ { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
+ { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
+ { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
+ { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
+ { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
+ { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
+ { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
+ { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
+ { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
+ { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
+ { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
+ { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
+ { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
+ { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
+ { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
+ { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
+ { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
+ { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
+ { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
+ { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
+ { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
+ { 0x0000aa50, 0x00000000, 0x00000000, 0x00058220, 0x00058220, 0x00000000 },
+ { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
+ { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
+ { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
+ { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
+ { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
+ { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
+ { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
+ { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
+ { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
+ { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
+ { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
+ { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
+ { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
+ { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
+ { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
+ { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
+ { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
+ { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
+ { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
+ { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
+ { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
+ { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
+ { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
+ { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
+ { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
+ { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
+ { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
+ { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
+ { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
+ { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
+ { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
+ { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
+ { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
+ { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
+ { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
+ { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
+ { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
+ { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
+ { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
+ { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
+ { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
+ { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
+ { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
+ { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
+ { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
+ { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
+ { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
+ { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
+ { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
+ { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
+ { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
+ { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
+ { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
+ { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
+ { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
+ { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
+ { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
+ { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
+ { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
+ { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
+ { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
+ { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
+ { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
+ { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
+ { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
+ { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
+ { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
+ { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
+ { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
+ { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
+ { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
+ { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
+ { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+ { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+ { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
+ { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
+};
+
+static const u_int32_t ar9285Common_v2[][2] = {
+ { 0x0000000c, 0x00000000 },
+ { 0x00000030, 0x00020045 },
+ { 0x00000034, 0x00000005 },
+ { 0x00000040, 0x00000000 },
+ { 0x00000044, 0x00000008 },
+ { 0x00000048, 0x00000008 },
+ { 0x0000004c, 0x00000010 },
+ { 0x00000050, 0x00000000 },
+ { 0x00000054, 0x0000001f },
+ { 0x00000800, 0x00000000 },
+ { 0x00000804, 0x00000000 },
+ { 0x00000808, 0x00000000 },
+ { 0x0000080c, 0x00000000 },
+ { 0x00000810, 0x00000000 },
+ { 0x00000814, 0x00000000 },
+ { 0x00000818, 0x00000000 },
+ { 0x0000081c, 0x00000000 },
+ { 0x00000820, 0x00000000 },
+ { 0x00000824, 0x00000000 },
+ { 0x00001040, 0x002ffc0f },
+ { 0x00001044, 0x002ffc0f },
+ { 0x00001048, 0x002ffc0f },
+ { 0x0000104c, 0x002ffc0f },
+ { 0x00001050, 0x002ffc0f },
+ { 0x00001054, 0x002ffc0f },
+ { 0x00001058, 0x002ffc0f },
+ { 0x0000105c, 0x002ffc0f },
+ { 0x00001060, 0x002ffc0f },
+ { 0x00001064, 0x002ffc0f },
+ { 0x00001230, 0x00000000 },
+ { 0x00001270, 0x00000000 },
+ { 0x00001038, 0x00000000 },
+ { 0x00001078, 0x00000000 },
+ { 0x000010b8, 0x00000000 },
+ { 0x000010f8, 0x00000000 },
+ { 0x00001138, 0x00000000 },
+ { 0x00001178, 0x00000000 },
+ { 0x000011b8, 0x00000000 },
+ { 0x000011f8, 0x00000000 },
+ { 0x00001238, 0x00000000 },
+ { 0x00001278, 0x00000000 },
+ { 0x000012b8, 0x00000000 },
+ { 0x000012f8, 0x00000000 },
+ { 0x00001338, 0x00000000 },
+ { 0x00001378, 0x00000000 },
+ { 0x000013b8, 0x00000000 },
+ { 0x000013f8, 0x00000000 },
+ { 0x00001438, 0x00000000 },
+ { 0x00001478, 0x00000000 },
+ { 0x000014b8, 0x00000000 },
+ { 0x000014f8, 0x00000000 },
+ { 0x00001538, 0x00000000 },
+ { 0x00001578, 0x00000000 },
+ { 0x000015b8, 0x00000000 },
+ { 0x000015f8, 0x00000000 },
+ { 0x00001638, 0x00000000 },
+ { 0x00001678, 0x00000000 },
+ { 0x000016b8, 0x00000000 },
+ { 0x000016f8, 0x00000000 },
+ { 0x00001738, 0x00000000 },
+ { 0x00001778, 0x00000000 },
+ { 0x000017b8, 0x00000000 },
+ { 0x000017f8, 0x00000000 },
+ { 0x0000103c, 0x00000000 },
+ { 0x0000107c, 0x00000000 },
+ { 0x000010bc, 0x00000000 },
+ { 0x000010fc, 0x00000000 },
+ { 0x0000113c, 0x00000000 },
+ { 0x0000117c, 0x00000000 },
+ { 0x000011bc, 0x00000000 },
+ { 0x000011fc, 0x00000000 },
+ { 0x0000123c, 0x00000000 },
+ { 0x0000127c, 0x00000000 },
+ { 0x000012bc, 0x00000000 },
+ { 0x000012fc, 0x00000000 },
+ { 0x0000133c, 0x00000000 },
+ { 0x0000137c, 0x00000000 },
+ { 0x000013bc, 0x00000000 },
+ { 0x000013fc, 0x00000000 },
+ { 0x0000143c, 0x00000000 },
+ { 0x0000147c, 0x00000000 },
+ { 0x00004030, 0x00000002 },
+ { 0x0000403c, 0x00000002 },
+ { 0x00004024, 0x0000001f },
+ { 0x00004060, 0x00000000 },
+ { 0x00004064, 0x00000000 },
+ { 0x00007010, 0x00000031 },
+ { 0x00007034, 0x00000002 },
+ { 0x00007038, 0x000004c2 },
+ { 0x00008004, 0x00000000 },
+ { 0x00008008, 0x00000000 },
+ { 0x0000800c, 0x00000000 },
+ { 0x00008018, 0x00000700 },
+ { 0x00008020, 0x00000000 },
+ { 0x00008038, 0x00000000 },
+ { 0x0000803c, 0x00000000 },
+ { 0x00008048, 0x00000000 },
+ { 0x00008054, 0x00000000 },
+ { 0x00008058, 0x00000000 },
+ { 0x0000805c, 0x000fc78f },
+ { 0x00008060, 0x0000000f },
+ { 0x00008064, 0x00000000 },
+ { 0x00008070, 0x00000000 },
+ { 0x000080c0, 0x2a80001a },
+ { 0x000080c4, 0x05dc01e0 },
+ { 0x000080c8, 0x1f402710 },
+ { 0x000080cc, 0x01f40000 },
+ { 0x000080d0, 0x00001e00 },
+ { 0x000080d4, 0x00000000 },
+ { 0x000080d8, 0x00400000 },
+ { 0x000080e0, 0xffffffff },
+ { 0x000080e4, 0x0000ffff },
+ { 0x000080e8, 0x003f3f3f },
+ { 0x000080ec, 0x00000000 },
+ { 0x000080f0, 0x00000000 },
+ { 0x000080f4, 0x00000000 },
+ { 0x000080f8, 0x00000000 },
+ { 0x000080fc, 0x00020000 },
+ { 0x00008100, 0x00020000 },
+ { 0x00008104, 0x00000001 },
+ { 0x00008108, 0x00000052 },
+ { 0x0000810c, 0x00000000 },
+ { 0x00008110, 0x00000168 },
+ { 0x00008118, 0x000100aa },
+ { 0x0000811c, 0x00003210 },
+ { 0x00008120, 0x08f04810 },
+ { 0x00008124, 0x00000000 },
+ { 0x00008128, 0x00000000 },
+ { 0x0000812c, 0x00000000 },
+ { 0x00008130, 0x00000000 },
+ { 0x00008134, 0x00000000 },
+ { 0x00008138, 0x00000000 },
+ { 0x0000813c, 0x00000000 },
+ { 0x00008144, 0xffffffff },
+ { 0x00008168, 0x00000000 },
+ { 0x0000816c, 0x00000000 },
+ { 0x00008170, 0x32143320 },
+ { 0x00008174, 0xfaa4fa50 },
+ { 0x00008178, 0x00000100 },
+ { 0x0000817c, 0x00000000 },
+ { 0x000081c0, 0x00000000 },
+ { 0x000081d0, 0x0000320a },
+ { 0x000081ec, 0x00000000 },
+ { 0x000081f0, 0x00000000 },
+ { 0x000081f4, 0x00000000 },
+ { 0x000081f8, 0x00000000 },
+ { 0x000081fc, 0x00000000 },
+ { 0x00008200, 0x00000000 },
+ { 0x00008204, 0x00000000 },
+ { 0x00008208, 0x00000000 },
+ { 0x0000820c, 0x00000000 },
+ { 0x00008210, 0x00000000 },
+ { 0x00008214, 0x00000000 },
+ { 0x00008218, 0x00000000 },
+ { 0x0000821c, 0x00000000 },
+ { 0x00008220, 0x00000000 },
+ { 0x00008224, 0x00000000 },
+ { 0x00008228, 0x00000000 },
+ { 0x0000822c, 0x00000000 },
+ { 0x00008230, 0x00000000 },
+ { 0x00008234, 0x00000000 },
+ { 0x00008238, 0x00000000 },
+ { 0x0000823c, 0x00000000 },
+ { 0x00008240, 0x00100000 },
+ { 0x00008244, 0x0010f400 },
+ { 0x00008248, 0x00000100 },
+ { 0x0000824c, 0x0001e800 },
+ { 0x00008250, 0x00000000 },
+ { 0x00008254, 0x00000000 },
+ { 0x00008258, 0x00000000 },
+ { 0x0000825c, 0x400000ff },
+ { 0x00008260, 0x00080922 },
+ { 0x00008264, 0x88a00010 },
+ { 0x00008270, 0x00000000 },
+ { 0x00008274, 0x40000000 },
+ { 0x00008278, 0x003e4180 },
+ { 0x0000827c, 0x00000000 },
+ { 0x00008284, 0x0000002c },
+ { 0x00008288, 0x0000002c },
+ { 0x0000828c, 0x00000000 },
+ { 0x00008294, 0x00000000 },
+ { 0x00008298, 0x00000000 },
+ { 0x0000829c, 0x00000000 },
+ { 0x00008300, 0x00000040 },
+ { 0x00008314, 0x00000000 },
+ { 0x00008328, 0x00000000 },
+ { 0x0000832c, 0x00000001 },
+ { 0x00008330, 0x00000302 },
+ { 0x00008334, 0x00000e00 },
+ { 0x00008338, 0x00ff0000 },
+ { 0x0000833c, 0x00000000 },
+ { 0x00008340, 0x00010380 },
+ { 0x00008344, 0x00481043 },
+ { 0x00009808, 0x00000000 },
+ { 0x0000980c, 0xafe68e30 },
+ { 0x00009810, 0xfd14e000 },
+ { 0x00009814, 0x9c0a9f6b },
+ { 0x0000981c, 0x00000000 },
+ { 0x0000982c, 0x0000a000 },
+ { 0x00009830, 0x00000000 },
+ { 0x0000983c, 0x00200400 },
+ { 0x0000984c, 0x0040233c },
+ { 0x00009854, 0x00000044 },
+ { 0x00009900, 0x00000000 },
+ { 0x00009904, 0x00000000 },
+ { 0x00009908, 0x00000000 },
+ { 0x0000990c, 0x00000000 },
+ { 0x00009910, 0x01002310 },
+ { 0x0000991c, 0x10000fff },
+ { 0x00009920, 0x04900000 },
+ { 0x00009928, 0x00000001 },
+ { 0x0000992c, 0x00000004 },
+ { 0x00009934, 0x1e1f2022 },
+ { 0x00009938, 0x0a0b0c0d },
+ { 0x0000993c, 0x00000000 },
+ { 0x00009940, 0x14750604 },
+ { 0x00009948, 0x9280c00a },
+ { 0x0000994c, 0x00020028 },
+ { 0x00009954, 0x5f3ca3de },
+ { 0x00009958, 0x2108ecff },
+ { 0x00009968, 0x000003ce },
+ { 0x00009970, 0x192bb514 },
+ { 0x00009974, 0x00000000 },
+ { 0x00009978, 0x00000001 },
+ { 0x0000997c, 0x00000000 },
+ { 0x00009980, 0x00000000 },
+ { 0x00009984, 0x00000000 },
+ { 0x00009988, 0x00000000 },
+ { 0x0000998c, 0x00000000 },
+ { 0x00009990, 0x00000000 },
+ { 0x00009994, 0x00000000 },
+ { 0x00009998, 0x00000000 },
+ { 0x0000999c, 0x00000000 },
+ { 0x000099a0, 0x00000000 },
+ { 0x000099a4, 0x00000001 },
+ { 0x000099a8, 0x201fff00 },
+ { 0x000099ac, 0x2def0400 },
+ { 0x000099b0, 0x03051000 },
+ { 0x000099b4, 0x00000820 },
+ { 0x000099dc, 0x00000000 },
+ { 0x000099e0, 0x00000000 },
+ { 0x000099e4, 0xaaaaaaaa },
+ { 0x000099e8, 0x3c466478 },
+ { 0x000099ec, 0x0cc80caa },
+ { 0x000099f0, 0x00000000 },
+ { 0x0000a208, 0x803e68c8 },
+ { 0x0000a210, 0x4080a333 },
+ { 0x0000a214, 0x00206c10 },
+ { 0x0000a218, 0x009c4060 },
+ { 0x0000a220, 0x01834061 },
+ { 0x0000a224, 0x00000400 },
+ { 0x0000a228, 0x000003b5 },
+ { 0x0000a22c, 0x00000000 },
+ { 0x0000a234, 0x20202020 },
+ { 0x0000a238, 0x20202020 },
+ { 0x0000a244, 0x00000000 },
+ { 0x0000a248, 0xfffffffc },
+ { 0x0000a24c, 0x00000000 },
+ { 0x0000a254, 0x00000000 },
+ { 0x0000a258, 0x0ccb5380 },
+ { 0x0000a25c, 0x15151501 },
+ { 0x0000a260, 0xdfa90f01 },
+ { 0x0000a268, 0x00000000 },
+ { 0x0000a26c, 0x0ebae9e6 },
+ { 0x0000d270, 0x0d820820 },
+ { 0x0000d35c, 0x07ffffef },
+ { 0x0000d360, 0x0fffffe7 },
+ { 0x0000d364, 0x17ffffe5 },
+ { 0x0000d368, 0x1fffffe4 },
+ { 0x0000d36c, 0x37ffffe3 },
+ { 0x0000d370, 0x3fffffe3 },
+ { 0x0000d374, 0x57ffffe3 },
+ { 0x0000d378, 0x5fffffe2 },
+ { 0x0000d37c, 0x7fffffe2 },
+ { 0x0000d380, 0x7f3c7bba },
+ { 0x0000d384, 0xf3307ff0 },
+ { 0x0000a388, 0x0c000000 },
+ { 0x0000a38c, 0x20202020 },
+ { 0x0000a390, 0x20202020 },
+ { 0x0000a39c, 0x00000001 },
+ { 0x0000a3a0, 0x00000000 },
+ { 0x0000a3a4, 0x00000000 },
+ { 0x0000a3a8, 0x00000000 },
+ { 0x0000a3ac, 0x00000000 },
+ { 0x0000a3b0, 0x00000000 },
+ { 0x0000a3b4, 0x00000000 },
+ { 0x0000a3b8, 0x00000000 },
+ { 0x0000a3bc, 0x00000000 },
+ { 0x0000a3c0, 0x00000000 },
+ { 0x0000a3c4, 0x00000000 },
+ { 0x0000a3cc, 0x20202020 },
+ { 0x0000a3d0, 0x20202020 },
+ { 0x0000a3d4, 0x20202020 },
+ { 0x0000a3e4, 0x00000000 },
+ { 0x0000a3e8, 0x18c43433 },
+ { 0x0000a3ec, 0x00f70081 },
+ { 0x00007800, 0x00140000 },
+ { 0x00007804, 0x0e4548d8 },
+ { 0x00007808, 0x54214514 },
+ { 0x0000780c, 0x02025830 },
+ { 0x00007810, 0x71c0d388 },
+ { 0x00007814, 0x924934a8 },
+ { 0x0000781c, 0x00000000 },
+ { 0x00007824, 0x00d86fff },
+ { 0x00007828, 0x26d2491b },
+ { 0x0000782c, 0x6e36d97b },
+ { 0x00007830, 0xedb6d96e },
+ { 0x00007834, 0x71400087 },
+ { 0x0000783c, 0x0001fffe },
+ { 0x00007840, 0xffeb1a20 },
+ { 0x00007844, 0x000c0db6 },
+ { 0x00007848, 0x6db61b6f },
+ { 0x0000784c, 0x6d9b66db },
+ { 0x00007850, 0x6d8c6dba },
+ { 0x00007854, 0x00040000 },
+ { 0x00007858, 0xdb003012 },
+ { 0x0000785c, 0x04924914 },
+ { 0x00007860, 0x21084210 },
+ { 0x00007864, 0xf7d7ffde },
+ { 0x00007868, 0xc2034080 },
+ { 0x00007870, 0x10142c00 },
+};
+
+static const u_int32_t ar9285Modes_high_power_tx_gain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
+ { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
+ { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
+ { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
+ { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
+ { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
+ { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
+ { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
+ { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
+ { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
+ { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
+ { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
+ { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
+ { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
+ { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
+ { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
+ { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
+ { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
+ { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
+ { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
+ { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
+ { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
+ { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
+ { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
+ { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
+};
+
+static const u_int32_t ar9285Modes_original_tx_gain_v2[][6] = {
+ /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
+ { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
+ { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
+ { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
+ { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
+ { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
+ { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
+ { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
+ { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
+ { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
+ { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
+ { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
+ { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
+ { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
+ { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
+ { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
+ { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
+ { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
+ { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
+ { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
+ { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
+ { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
+ { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
+ { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
+ { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
+ { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
+ { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
+};
+
+static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_v2[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01dcffd },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
+
+static const u_int32_t ar9285PciePhy_clkreq_off_L1_v2[][2] = {
+ {0x00004040, 0x9248fd00 },
+ {0x00004040, 0x24924924 },
+ {0x00004040, 0xa8000019 },
+ {0x00004040, 0x13160820 },
+ {0x00004040, 0xe5980560 },
+ {0x00004040, 0xc01dcffc },
+ {0x00004040, 0x1aaabe41 },
+ {0x00004040, 0xbe105554 },
+ {0x00004040, 0x00043007 },
+ {0x00004044, 0x00000000 },
+};
--
1.7.1.rc0.7.g02125bc