------------------------------------------------------------------
000:00:0: Intel Sandy Bridge (mobile) Host Bridge (host bridge, revision 0x09)
000:02:0: Intel Sandy Bridge (mobile) GT2+ Integrated Graphics Device (VGA display, revision 0x09)
000:22:0: Intel 6 Series Chipset Family MEI (miscellaneous communications, revision 0x04)
000:25:0: Intel 82579LM Gigabit Network Connection (ethernet network, revision 0x04)
000:26:0: Intel 6 Series Chipset Family USB (USB serial bus, EHCI, revision 0x04)
000:27:0: Intel 6 Series Chipset Family HD Audio (mixed mode multimedia, revision 0x04)
000:28:0: Intel 6 Series Chipset Family PCIe Root Port 1 (PCI bridge, revision 0xb4)
000:28:1: Intel 6 Series Chipset Family PCIe Root Port 2 (PCI bridge, revision 0xb4)
000:28:3: Intel 6 Series Chipset Family PCIe Root Port 4 (PCI bridge, revision 0xb4)
000:28:4: Intel 6 Series Chipset Family PCIe Root Port 5 (PCI bridge, revision 0xb4)
000:29:0: Intel 6 Series Chipset Family USB (USB serial bus, EHCI, revision 0x04)
000:31:0: Intel QM67 LPC (ISA bridge, revision 0x04)
000:31:2: Intel 6 Series Chipset Family AHCI 2 (SATA mass storage, AHCI 1.0, revision 0x04)
000:31:3: Intel 6 Series Chipset Family SMBus Controller (SMBus serial bus, revision 0x04)
003:00:0: Intel Centrino Advanced-N 6205 WiFi (miscellaneous network, revision 0x34)
005:00:0: Ricoh 5U823 SD/MMC Controller (miscellaneous system, revision 0x04)
013:00:0: NEC Renesas Electronics USB 3.0 Host Controller (USB serial bus, xHCI, revision 0x04)
------------------------------------------------------------------
pcictl pci0 dump -b 0 -d 0 -f 0
PCI configuration registers:
Common header:
0x00: 0x01048086 0x20900006 0x06000009 0x00000000
Vendor Name: Intel (0x8086)
Device Name: Sandy Bridge (mobile) Host Bridge (0x0104)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x2090
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: on
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x09
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
not implemented
Base address register at 0x14
not implemented
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0xe0
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Capability register at 0xe0
type: 0x09 (Vendor-specific)
PCI Vendor Specific Capabilities Register
Capabilities length: 0x0c
Vendor Name: Intel (0x8086)
Device Name: Sandy Bridge (mobile) GT2+ Integrated Graphics Device (0x0126)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0090
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: display (0x03)
Subclass Name: VGA (0x00)
Interface: 0x00
Revision ID: 0x09
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 64-bit nonprefetchable memory
base: 0x00000000f0000000
Base address register at 0x18
type: 64-bit prefetchable memory
base: 0x00000000e0000000
Base address register at 0x20
type: I/O
base: 0x00004000
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x90
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0b
Capability register at 0x90
type: 0x05 (MSI)
Capability register at 0xd0
type: 0x01 (Power Management)
Capability register at 0xa4
type: 0x13 (Advanced Features)
PCI Power Management Capabilities Register
Capabilities register: 0x0022
Version: 1.1
PME# clock: off
Device specific initialization: on
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: off
PME# support D1: off
PME# support D2: off
PME# support D3 hot: off
PME# support D3 cold: off
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0000
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: off
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address register: 0x00000000
Message Data register: 0x0000
Advanced Features Capability Register
AF Capabilities register: 0x03
AF Structure Length: 0x06
Transaction Pending: on
Function Level Reset: on
AF Control register: 0x00
AF Status register: 0x00
Transaction Pending: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family MEI (0x1c3a)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0018
Immediate Readiness: off
Interrupt status: active
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: communications (0x07)
Subclass Name: miscellaneous (0x80)
Interface: 0x00
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 64-bit nonprefetchable memory
base: 0x00000000fed0a000
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x00
Capability register at 0x50
type: 0x01 (Power Management)
Capability register at 0x8c
type: 0x05 (MSI)
PCI Power Management Capabilities Register
Capabilities register: 0xc803
Version: 1.2
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000008
Power state: D0
PCI Express reserved: off
No soft reset: on
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0080
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: on
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address (lower) register: 0x00000000
Message Address (upper) register: 0x00000000
Message Data register: 0x0000
Vendor Name: Intel (0x8086)
Device Name: 82579LM Gigabit Network Connection (0x1502)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: ethernet (0x00)
Interface: 0x00
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xf1600000
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0xf162b000
Base address register at 0x18
type: I/O
base: 0x00004080
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21ce
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0xc8
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0a
Capability register at 0xc8
type: 0x01 (Power Management)
Capability register at 0xd0
type: 0x05 (MSI)
Capability register at 0xe0
type: 0x13 (Advanced Features)
PCI Power Management Capabilities Register
Capabilities register: 0xc822
Version: 1.1
PME# clock: off
Device specific initialization: on
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00002100
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: enabled
Data Select: 0
Data Scale: 1
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0080
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: on
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address (lower) register: 0x00000000
Message Address (upper) register: 0x00000000
Message Data register: 0x0000
Advanced Features Capability Register
AF Capabilities register: 0x03
AF Structure Length: 0x06
Transaction Pending: on
Function Level Reset: on
AF Control register: 0x00
AF Status register: 0x00
Transaction Pending: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family USB (0x1c2d)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0290
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface Name: EHCI (0x20)
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xf162a000
Base address register at 0x14
not implemented
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0b
Capability register at 0x50
type: 0x01 (Power Management)
Capability register at 0x58
type: 0x0a (Debug Port)
Capability register at 0x98
type: 0x13 (Advanced Features)
PCI Power Management Capabilities Register
Capabilities register: 0xc9c2
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: 375 mA
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
Debugport Capability Register
Debug base Register: 0x20a0
port offset: 0x00a0
BAR number: 1
Advanced Features Capability Register
AF Capabilities register: 0x03
AF Structure Length: 0x06
Transaction Pending: on
Function Level Reset: on
AF Control register: 0x00
AF Status register: 0x00
Transaction Pending: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family HD Audio (0x1c20)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: multimedia (0x04)
Subclass Name: mixed mode (0x03)
Interface: 0x00
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
type: 64-bit nonprefetchable memory
base: 0x00000000f1620000
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x07
Capability register at 0x50
type: 0x01 (Power Management)
Capability register at 0x60
type: 0x05 (MSI)
Capability register at 0x70
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xc842
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: 55 mA
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0080
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: on
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address (lower) register: 0x00000000
Message Address (upper) register: 0x00000000
Message Data register: 0x0000
PCI Express Capabilities Register
Capability register: 0x0091
Capability version: 1
Device type: Root Complex Integrated Endpoint
Slot implemented: off
Interrupt Message Number: 0x00
Device Capabilities Register: 0x10000000
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: Less than 64ns
Endpoint L1 Acceptable Latency: Less than 1us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: off
Function-Level Reset Capability: on
Device Control Register: 0x0800
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: off
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: on
Max Read Request Size: 128 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Extended Capability Register at 0x100
type: 0x0002 (Virtual Channel)
version: 1
Extended Capability Register at 0x130
type: 0x0005 (Root Complex Link Declaration)
version: 1
Virtual Channel Register
Port VC Capability register 1: 0x00000001
Extended VC Count: 1
Low Priority Extended VC Count: 0
Reference Clock: 100ns
Port Arbitration Table Entry Size: 1bit
Port VC Capability register 2: 0x00000000
Hardware fixed arbitration scheme: off
WRR arbitration with 32 phases: off
WRR arbitration with 64 phases: off
WRR arbitration with 128 phases: off
VC Arbitration Table Offset: 0x0
Port VC Control register: 0x0000
VC Arbitration Select: 0x0
Port VC Status register: 0x0000
VC Arbitration Table Status: off
VC number 0
VC Resource Capability Register: 0x00000000
Non-configurable Hardware fixed arbitration scheme: off
WRR arbitration with 32 phases: off
WRR arbitration with 64 phases: off
WRR arbitration with 128 phases: off
Time-based WRR arbitration with 128 phases: off
WRR arbitration with 256 phases: off
Advanced Packet Switching: off
Reject Snoop Transaction: off
Maximum Time Slots: 1
Port Arbitration Table offset: 0x00
VC Resource Control Register: 0x80000001
TC/VC Map: 0x01
Port Arbitration Select: 0x0
VC ID: 0
VC Enable: on
VC Resource Status Register: 0x00000000
Port Arbitration Table Status: off
VC Negotiation Pending: off
VC number 1
VC Resource Capability Register: 0x00000000
Non-configurable Hardware fixed arbitration scheme: off
WRR arbitration with 32 phases: off
WRR arbitration with 64 phases: off
WRR arbitration with 128 phases: off
Time-based WRR arbitration with 128 phases: off
WRR arbitration with 256 phases: off
Advanced Packet Switching: off
Reject Snoop Transaction: off
Maximum Time Slots: 1
Port Arbitration Table offset: 0x00
VC Resource Control Register: 0x81000022
TC/VC Map: 0x22
Port Arbitration Select: 0x0
VC ID: 1
VC Enable: on
VC Resource Status Register: 0x00000000
Port Arbitration Table Status: off
VC Negotiation Pending: off
Root Complex Link Declaration
Element Self Description Register: 0x0f000100
Element Type: Configuration Space Element
Number of Link Entries: 1
Component ID: 0
Port Number: 15
Link Entry 1:
Link Description Register: 0x00000001
Link Valid: on
Link Type: Memory-Mapped Space
Associated RCRB Header: off
Target Component ID: 0
Target Port Number: 0
Link Address Low Register: 0xfed1c000
Link Address High Register: 0x00000000
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family PCIe Root Port 1 (0x1c10)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xb4
BIST: 0x00
Header Type: 0x01+multifunction (0x81)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
not implemented
Base address register at 0x14
not implemented
Primary bus number: 0x00
Secondary bus number: 0x02
Subordinate bus number: 0x02
Secondary bus latency timer: 0x00
Secondary status register: 0x2000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signalled target abort: off
Received target abort: off
Received master abort: on
Received system error: off
Detected parity error: off
I/O region:
base register: 0xf0
limit register: 0x00
32bit I/O: off
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
range: not set
Memory region:
base register: 0xfff0
limit register: 0x0000
range: not set
Prefetchable memory region:
base register: 0xfff1
limit register: 0x0001
base upper 32 bits register: 0xffffffff
limit upper 32 bits register: 0x00000000
64bit memory address: on
range: not set
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0x0b
Interrupt pin: 0x01 (pin A)
Bridge control register: 0x0000
Parity error response: off
Secondary SERR forwarding: off
ISA enable: off
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x10 (PCI Express)
Capability register at 0x80
type: 0x05 (MSI)
Capability register at 0x90
type: 0x0d (Subsystem vendor ID)
Capability register at 0xa0
type: 0x01 (Power Management)
PCI Power Management Capabilities Register
Capabilities register: 0xc802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0000
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: off
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address register: 0x00000000
Message Data register: 0x0000
Subsystem ID Capability Register
Subsystem ID : 0x21d217aa
PCI Express Capabilities Register
Capability register: 0x0142
Capability version: 2
Device type: Root Port of PCI Express Root Complex
Slot implemented: on
Interrupt Message Number: 0x00
Device Capabilities Register: 0x00008000
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: Less than 64ns
Endpoint L1 Acceptable Latency: Less than 1us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: on
Function-Level Reset Capability: off
Device Control Register: 0x0000
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: off
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: off
Max Read Request Size: 128 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x01114c12
Maximum Link Speed: 5.0GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 512ns to less than 1us
L1 Exit Latency: 2us to less than 4us
Port Number: 1
Clock Power Management: off
Surprise Down Error Report: off
Data Link Layer Link Active: on
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0003
Active State PM Control: L0s and L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: off
Extended Synch: off
Enable Clock Power Management: off
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x1001
Negotiated Link Speed: 2.5GT/s
Negotiated Link Width: x0 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: off
Link Bandwidth Management Status: off
Link Autonomous Bandwidth Status: off
Slot Capability Register: 0x00040060
Attention Button Present: off
Power Controller Present: off
MRL Sensor Present: off
Attention Indicator Present: off
Power Indicator Present: off
Hot-Plug Surprise: on
Hot-Plug Capable: on
Slot Power Limit Value: 0W
Electromechanical Interlock Present: off
No Command Completed Support: on
Physical Slot Number: 0
Slot Control Register: 0x0000
Attention Button Pressed Enabled: off
Power Fault Detected Enabled: off
MRL Sensor Changed Enabled: off
Presence Detect Changed Enabled: off
Command Completed Interrupt Enabled: off
Hot-Plug Interrupt Enabled: off
Power Controller Control: Power on
Electromechanical Interlock Control: off
Data Link Layer State Changed Enable: off
Auto Slot Power Limit Disable: off
Slot Status Register: 0x0000
Attention Button Pressed: off
Power Fault Detected: off
MRL Sensor Changed: off
Presence Detect Changed: off
Command Completed: off
MRL Open: off
Card Present in slot: off
Electromechanical Interlock engaged: off
Data Link Layer State Changed: off
Root Control Register: 0x0000
SERR on Correctable Error Enable: off
SERR on Non-Fatal Error Enable: off
SERR on Fatal Error Enable: off
PME Interrupt Enable: off
CRS Software Visibility Enable: off
Root Capability Register: 0x0000
CRS Software Visibility: off
Root Status Register: 0x00000000
PME Requester ID: 0x0000
PME was asserted: off
another PME is pending: off
Device Capabilities 2: 0x00000016
Completion Timeout Ranges Supported: BC
Completion Timeout Disable Supported: on
ARI Forwarding Supported: off
AtomicOp Routing Supported: off
32bit AtomicOp Completer Supported: off
64bit AtomicOp Completer Supported: off
128-bit CAS Completer Supported: off
No RO-enabled PR-PR passing: off
LTR Mechanism Supported: off
TPH Completer Supported: Not supported
LN System CLS: Not supported or not in effect
OBFF Supported: Not supported
Extended Fmt Field Supported: off
End-End TLP Prefix Supported: off
Max End-End TLP Prefixes: 4
Emergency Power Reduction Supported: Not supported
Emergency Power Reduction Initialization Required: off
FRS Supported: off
Device Control 2: 0x0000
Completion Timeout Value: 50us to 50ms
Completion Timeout Disabled: off
ARI Forwarding Enabled: off
AtomicOp Requester Enabled: off
AtomicOp Egress Blocking: off
IDO Request Enabled: off
IDO Completion Enabled: off
LTR Mechanism Enabled: off
Emergency Power Reduction Request: off
OBFF: Disabled
End-End TLP Prefix Blocking on: off
Link Control 2: 0x0002
Target Link Speed: 5.0GT/s
Enter Compliance Enabled: off
HW Autonomous Speed Disabled: off
Selectable De-emphasis: -6dB
Transmit Margin: 0
Enter Modified Compliance: off
Compliance SOS: off
Compliance Present/De-emphasis: -6dB
Link Status 2: 0x0001
Current De-emphasis Level: -3.5dB
Equalization Complete: off
Equalization Phase 1 Successful: off
Equalization Phase 2 Successful: off
Equalization Phase 3 Successful: off
Link Equalization Request: off
Retimer Presence Detected: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family PCIe Root Port 2 (0x1c12)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xb4
BIST: 0x00
Header Type: 0x01+multifunction (0x81)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
not implemented
Base address register at 0x14
not implemented
Primary bus number: 0x00
Secondary bus number: 0x03
Subordinate bus number: 0x03
Secondary bus latency timer: 0x00
Secondary status register: 0x0000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signalled target abort: off
Received target abort: off
Received master abort: off
Received system error: off
Detected parity error: off
I/O region:
base register: 0xf0
limit register: 0x00
32bit I/O: off
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
range: not set
Memory region:
base register: 0xf150
limit register: 0xf150
range: 0xf1500000-0xf15fffff
Prefetchable memory region:
base register: 0xfff1
limit register: 0x0001
base upper 32 bits register: 0xffffffff
limit upper 32 bits register: 0x00000000
64bit memory address: on
range: not set
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0x07
Interrupt pin: 0x02 (pin B)
Bridge control register: 0x0000
Parity error response: off
Secondary SERR forwarding: off
ISA enable: off
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x10 (PCI Express)
Capability register at 0x80
type: 0x05 (MSI)
Capability register at 0x90
type: 0x0d (Subsystem vendor ID)
Capability register at 0xa0
type: 0x01 (Power Management)
PCI Power Management Capabilities Register
Capabilities register: 0xc802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0000
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: off
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address register: 0x00000000
Message Data register: 0x0000
Subsystem ID Capability Register
Subsystem ID : 0x21d217aa
PCI Express Capabilities Register
Capability register: 0x0142
Capability version: 2
Device type: Root Port of PCI Express Root Complex
Slot implemented: on
Interrupt Message Number: 0x00
Device Capabilities Register: 0x00008000
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: Less than 64ns
Endpoint L1 Acceptable Latency: Less than 1us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: on
Function-Level Reset Capability: off
Device Control Register: 0x0000
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: off
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: off
Max Read Request Size: 128 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x02123c12
Maximum Link Speed: 5.0GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 256ns to less than 512ns
L1 Exit Latency: 8us to less than 16us
Port Number: 2
Clock Power Management: off
Surprise Down Error Report: off
Data Link Layer Link Active: on
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0042
Active State PM Control: L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: on
Extended Synch: off
Enable Clock Power Management: off
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x7011
Negotiated Link Speed: 2.5GT/s
Negotiated Link Width: x1 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: on
Link Bandwidth Management Status: on
Link Autonomous Bandwidth Status: off
Slot Capability Register: 0x000cb200
Attention Button Present: off
Power Controller Present: off
MRL Sensor Present: off
Attention Indicator Present: off
Power Indicator Present: off
Hot-Plug Surprise: off
Hot-Plug Capable: off
Slot Power Limit Value: 10.0W
Electromechanical Interlock Present: off
No Command Completed Support: on
Physical Slot Number: 1
Slot Control Register: 0x0000
Attention Button Pressed Enabled: off
Power Fault Detected Enabled: off
MRL Sensor Changed Enabled: off
Presence Detect Changed Enabled: off
Command Completed Interrupt Enabled: off
Hot-Plug Interrupt Enabled: off
Power Controller Control: Power on
Electromechanical Interlock Control: off
Data Link Layer State Changed Enable: off
Auto Slot Power Limit Disable: off
Slot Status Register: 0x0140
Attention Button Pressed: off
Power Fault Detected: off
MRL Sensor Changed: off
Presence Detect Changed: off
Command Completed: off
MRL Open: off
Card Present in slot: on
Electromechanical Interlock engaged: off
Data Link Layer State Changed: on
Root Control Register: 0x0000
SERR on Correctable Error Enable: off
SERR on Non-Fatal Error Enable: off
SERR on Fatal Error Enable: off
PME Interrupt Enable: off
CRS Software Visibility Enable: off
Root Capability Register: 0x0000
CRS Software Visibility: off
Root Status Register: 0x00000000
PME Requester ID: 0x0000
PME was asserted: off
another PME is pending: off
Device Capabilities 2: 0x00000016
Completion Timeout Ranges Supported: BC
Completion Timeout Disable Supported: on
ARI Forwarding Supported: off
AtomicOp Routing Supported: off
32bit AtomicOp Completer Supported: off
64bit AtomicOp Completer Supported: off
128-bit CAS Completer Supported: off
No RO-enabled PR-PR passing: off
LTR Mechanism Supported: off
TPH Completer Supported: Not supported
LN System CLS: Not supported or not in effect
OBFF Supported: Not supported
Extended Fmt Field Supported: off
End-End TLP Prefix Supported: off
Max End-End TLP Prefixes: 4
Emergency Power Reduction Supported: Not supported
Emergency Power Reduction Initialization Required: off
FRS Supported: off
Device Control 2: 0x0000
Completion Timeout Value: 50us to 50ms
Completion Timeout Disabled: off
ARI Forwarding Enabled: off
AtomicOp Requester Enabled: off
AtomicOp Egress Blocking: off
IDO Request Enabled: off
IDO Completion Enabled: off
LTR Mechanism Enabled: off
Emergency Power Reduction Request: off
OBFF: Disabled
End-End TLP Prefix Blocking on: off
Link Control 2: 0x0002
Target Link Speed: 5.0GT/s
Enter Compliance Enabled: off
HW Autonomous Speed Disabled: off
Selectable De-emphasis: -6dB
Transmit Margin: 0
Enter Modified Compliance: off
Compliance SOS: off
Compliance Present/De-emphasis: -6dB
Link Status 2: 0x0001
Current De-emphasis Level: -3.5dB
Equalization Complete: off
Equalization Phase 1 Successful: off
Equalization Phase 2 Successful: off
Equalization Phase 3 Successful: off
Link Equalization Request: off
Retimer Presence Detected: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family PCIe Root Port 4 (0x1c16)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xb4
BIST: 0x00
Header Type: 0x01+multifunction (0x81)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
not implemented
Base address register at 0x14
not implemented
Primary bus number: 0x00
Secondary bus number: 0x05
Subordinate bus number: 0x0c
Secondary bus latency timer: 0x00
Secondary status register: 0x2000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signalled target abort: off
Received target abort: off
Received master abort: on
Received system error: off
Detected parity error: off
I/O region:
base register: 0x30
limit register: 0x30
32bit I/O: off
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
range: 0x3000-0x3fff
Memory region:
base register: 0xf0d0
limit register: 0xf140
range: 0xf0d00000-0xf14fffff
Prefetchable memory region:
base register: 0xf041
limit register: 0xf0b1
base upper 32 bits register: 0x00000000
limit upper 32 bits register: 0x00000000
64bit memory address: on
range: 0x00000000f0400000-0x00000000f0bfffff
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0x0b
Interrupt pin: 0x04 (pin D)
Bridge control register: 0x0000
Parity error response: off
Secondary SERR forwarding: off
ISA enable: off
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x10 (PCI Express)
Capability register at 0x80
type: 0x05 (MSI)
Capability register at 0x90
type: 0x0d (Subsystem vendor ID)
Capability register at 0xa0
type: 0x01 (Power Management)
PCI Power Management Capabilities Register
Capabilities register: 0xc802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0000
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: off
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address register: 0x00000000
Message Data register: 0x0000
Subsystem ID Capability Register
Subsystem ID : 0x21d217aa
PCI Express Capabilities Register
Capability register: 0x0142
Capability version: 2
Device type: Root Port of PCI Express Root Complex
Slot implemented: on
Interrupt Message Number: 0x00
Device Capabilities Register: 0x00008000
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: Less than 64ns
Endpoint L1 Acceptable Latency: Less than 1us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: on
Function-Level Reset Capability: off
Device Control Register: 0x0000
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: off
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: off
Max Read Request Size: 128 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x04123c12
Maximum Link Speed: 5.0GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 256ns to less than 512ns
L1 Exit Latency: 8us to less than 16us
Port Number: 4
Clock Power Management: off
Surprise Down Error Report: off
Data Link Layer Link Active: on
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0042
Active State PM Control: L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: on
Extended Synch: off
Enable Clock Power Management: off
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x7011
Negotiated Link Speed: 2.5GT/s
Negotiated Link Width: x1 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: on
Link Bandwidth Management Status: on
Link Autonomous Bandwidth Status: off
Slot Capability Register: 0x001cb260
Attention Button Present: off
Power Controller Present: off
MRL Sensor Present: off
Attention Indicator Present: off
Power Indicator Present: off
Hot-Plug Surprise: on
Hot-Plug Capable: on
Slot Power Limit Value: 10.0W
Electromechanical Interlock Present: off
No Command Completed Support: on
Physical Slot Number: 3
Slot Control Register: 0x0000
Attention Button Pressed Enabled: off
Power Fault Detected Enabled: off
MRL Sensor Changed Enabled: off
Presence Detect Changed Enabled: off
Command Completed Interrupt Enabled: off
Hot-Plug Interrupt Enabled: off
Power Controller Control: Power on
Electromechanical Interlock Control: off
Data Link Layer State Changed Enable: off
Auto Slot Power Limit Disable: off
Slot Status Register: 0x0040
Attention Button Pressed: off
Power Fault Detected: off
MRL Sensor Changed: off
Presence Detect Changed: off
Command Completed: off
MRL Open: off
Card Present in slot: on
Electromechanical Interlock engaged: off
Data Link Layer State Changed: off
Root Control Register: 0x0000
SERR on Correctable Error Enable: off
SERR on Non-Fatal Error Enable: off
SERR on Fatal Error Enable: off
PME Interrupt Enable: off
CRS Software Visibility Enable: off
Root Capability Register: 0x0000
CRS Software Visibility: off
Root Status Register: 0x00000000
PME Requester ID: 0x0000
PME was asserted: off
another PME is pending: off
Device Capabilities 2: 0x00000016
Completion Timeout Ranges Supported: BC
Completion Timeout Disable Supported: on
ARI Forwarding Supported: off
AtomicOp Routing Supported: off
32bit AtomicOp Completer Supported: off
64bit AtomicOp Completer Supported: off
128-bit CAS Completer Supported: off
No RO-enabled PR-PR passing: off
LTR Mechanism Supported: off
TPH Completer Supported: Not supported
LN System CLS: Not supported or not in effect
OBFF Supported: Not supported
Extended Fmt Field Supported: off
End-End TLP Prefix Supported: off
Max End-End TLP Prefixes: 4
Emergency Power Reduction Supported: Not supported
Emergency Power Reduction Initialization Required: off
FRS Supported: off
Device Control 2: 0x0000
Completion Timeout Value: 50us to 50ms
Completion Timeout Disabled: off
ARI Forwarding Enabled: off
AtomicOp Requester Enabled: off
AtomicOp Egress Blocking: off
IDO Request Enabled: off
IDO Completion Enabled: off
LTR Mechanism Enabled: off
Emergency Power Reduction Request: off
OBFF: Disabled
End-End TLP Prefix Blocking on: off
Link Control 2: 0x0002
Target Link Speed: 5.0GT/s
Enter Compliance Enabled: off
HW Autonomous Speed Disabled: off
Selectable De-emphasis: -6dB
Transmit Margin: 0
Enter Modified Compliance: off
Compliance SOS: off
Compliance Present/De-emphasis: -6dB
Link Status 2: 0x0001
Current De-emphasis Level: -3.5dB
Equalization Complete: off
Equalization Phase 1 Successful: off
Equalization Phase 2 Successful: off
Equalization Phase 3 Successful: off
Link Equalization Request: off
Retimer Presence Detected: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family PCIe Root Port 5 (0x1c18)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xb4
BIST: 0x00
Header Type: 0x01+multifunction (0x81)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
not implemented
Base address register at 0x14
not implemented
Primary bus number: 0x00
Secondary bus number: 0x0d
Subordinate bus number: 0x0d
Secondary bus latency timer: 0x00
Secondary status register: 0x0000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signalled target abort: off
Received target abort: off
Received master abort: off
Received system error: off
Detected parity error: off
I/O region:
base register: 0xf0
limit register: 0x00
32bit I/O: off
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
range: not set
Memory region:
base register: 0xf0c0
limit register: 0xf0c0
range: 0xf0c00000-0xf0cfffff
Prefetchable memory region:
base register: 0xfff1
limit register: 0x0001
base upper 32 bits register: 0xffffffff
limit upper 32 bits register: 0x00000000
64bit memory address: on
range: not set
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0x0b
Interrupt pin: 0x01 (pin A)
Bridge control register: 0x0000
Parity error response: off
Secondary SERR forwarding: off
ISA enable: off
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x10 (PCI Express)
Capability register at 0x80
type: 0x05 (MSI)
Capability register at 0x90
type: 0x0d (Subsystem vendor ID)
Capability register at 0xa0
type: 0x01 (Power Management)
PCI Power Management Capabilities Register
Capabilities register: 0xc802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0000
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: off
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address register: 0x00000000
Message Data register: 0x0000
Subsystem ID Capability Register
Subsystem ID : 0x21d217aa
PCI Express Capabilities Register
Capability register: 0x0142
Capability version: 2
Device type: Root Port of PCI Express Root Complex
Slot implemented: on
Interrupt Message Number: 0x00
Device Capabilities Register: 0x00008000
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: Less than 64ns
Endpoint L1 Acceptable Latency: Less than 1us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: on
Function-Level Reset Capability: off
Device Control Register: 0x0000
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: off
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: off
Max Read Request Size: 128 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x05123c12
Maximum Link Speed: 5.0GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 256ns to less than 512ns
L1 Exit Latency: 8us to less than 16us
Port Number: 5
Clock Power Management: off
Surprise Down Error Report: off
Data Link Layer Link Active: on
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0042
Active State PM Control: L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: on
Extended Synch: off
Enable Clock Power Management: off
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x7012
Negotiated Link Speed: 5.0GT/s
Negotiated Link Width: x1 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: on
Link Bandwidth Management Status: on
Link Autonomous Bandwidth Status: off
Slot Capability Register: 0x0024b200
Attention Button Present: off
Power Controller Present: off
MRL Sensor Present: off
Attention Indicator Present: off
Power Indicator Present: off
Hot-Plug Surprise: off
Hot-Plug Capable: off
Slot Power Limit Value: 10.0W
Electromechanical Interlock Present: off
No Command Completed Support: on
Physical Slot Number: 4
Slot Control Register: 0x0000
Attention Button Pressed Enabled: off
Power Fault Detected Enabled: off
MRL Sensor Changed Enabled: off
Presence Detect Changed Enabled: off
Command Completed Interrupt Enabled: off
Hot-Plug Interrupt Enabled: off
Power Controller Control: Power on
Electromechanical Interlock Control: off
Data Link Layer State Changed Enable: off
Auto Slot Power Limit Disable: off
Slot Status Register: 0x0140
Attention Button Pressed: off
Power Fault Detected: off
MRL Sensor Changed: off
Presence Detect Changed: off
Command Completed: off
MRL Open: off
Card Present in slot: on
Electromechanical Interlock engaged: off
Data Link Layer State Changed: on
Root Control Register: 0x0000
SERR on Correctable Error Enable: off
SERR on Non-Fatal Error Enable: off
SERR on Fatal Error Enable: off
PME Interrupt Enable: off
CRS Software Visibility Enable: off
Root Capability Register: 0x0000
CRS Software Visibility: off
Root Status Register: 0x00000000
PME Requester ID: 0x0000
PME was asserted: off
another PME is pending: off
Device Capabilities 2: 0x00000016
Completion Timeout Ranges Supported: BC
Completion Timeout Disable Supported: on
ARI Forwarding Supported: off
AtomicOp Routing Supported: off
32bit AtomicOp Completer Supported: off
64bit AtomicOp Completer Supported: off
128-bit CAS Completer Supported: off
No RO-enabled PR-PR passing: off
LTR Mechanism Supported: off
TPH Completer Supported: Not supported
LN System CLS: Not supported or not in effect
OBFF Supported: Not supported
Extended Fmt Field Supported: off
End-End TLP Prefix Supported: off
Max End-End TLP Prefixes: 4
Emergency Power Reduction Supported: Not supported
Emergency Power Reduction Initialization Required: off
FRS Supported: off
Device Control 2: 0x0000
Completion Timeout Value: 50us to 50ms
Completion Timeout Disabled: off
ARI Forwarding Enabled: off
AtomicOp Requester Enabled: off
AtomicOp Egress Blocking: off
IDO Request Enabled: off
IDO Completion Enabled: off
LTR Mechanism Enabled: off
Emergency Power Reduction Request: off
OBFF: Disabled
End-End TLP Prefix Blocking on: off
Link Control 2: 0x0002
Target Link Speed: 5.0GT/s
Enter Compliance Enabled: off
HW Autonomous Speed Disabled: off
Selectable De-emphasis: -6dB
Transmit Margin: 0
Enter Modified Compliance: off
Compliance SOS: off
Compliance Present/De-emphasis: -6dB
Link Status 2: 0x0000
Current De-emphasis Level: -6dB
Equalization Complete: off
Equalization Phase 1 Successful: off
Equalization Phase 2 Successful: off
Equalization Phase 3 Successful: off
Link Equalization Request: off
Retimer Presence Detected: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family USB (0x1c26)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0290
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface Name: EHCI (0x20)
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xf1629000
Base address register at 0x14
not implemented
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0a
Capability register at 0x50
type: 0x01 (Power Management)
Capability register at 0x58
type: 0x0a (Debug Port)
Capability register at 0x98
type: 0x13 (Advanced Features)
PCI Power Management Capabilities Register
Capabilities register: 0xc9c2
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: 375 mA
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
Debugport Capability Register
Debug base Register: 0x20a0
port offset: 0x00a0
BAR number: 1
Advanced Features Capability Register
AF Capabilities register: 0x03
AF Structure Length: 0x06
Transaction Pending: on
Function Level Reset: on
AF Control register: 0x00
AF Status register: 0x00
Transaction Pending: off
Vendor Name: Intel (0x8086)
Device Name: QM67 LPC (0x1c4f)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0210
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: ISA (0x01)
Interface: 0x00
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
not implemented
Base address register at 0x14
not implemented
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0xe0
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Capability register at 0xe0
type: 0x09 (Vendor-specific)
PCI Vendor Specific Capabilities Register
Capabilities length: 0x0c
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family AHCI 2 (0x1c03)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x02b8
Immediate Readiness: off
Interrupt status: active
Capability List support: on
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: SATA (0x06)
Interface Name: AHCI 1.0 (0x01)
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: I/O
base: 0x000040a8
Base address register at 0x14
type: I/O
base: 0x000040b4
Base address register at 0x18
type: I/O
base: 0x000040a0
Base address register at 0x1c
type: I/O
base: 0x000040b0
Base address register at 0x20
type: I/O
base: 0x00004060
Base address register at 0x24
type: 32-bit nonprefetchable memory
base: 0xf1628000
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x80
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x02 (pin B)
Interrupt line: 0x0b
Capability register at 0x80
type: 0x05 (MSI)
Capability register at 0x70
type: 0x01 (Power Management)
Capability register at 0xa8
type: 0x12 (SATA)
Capability register at 0xb0
type: 0x13 (Advanced Features)
PCI Power Management Capabilities Register
Capabilities register: 0x4003
Version: 1.2
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: off
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: off
Control/status register: 0x00000008
Power state: D0
PCI Express reserved: off
No soft reset: on
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0000
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: off
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address register: 0x00000000
Message Data register: 0x0000
Serial ATA Capability Register
Revision register: 0x0010
Revision: 1.0
BAR Register: 0x00000048
Register location: BAR 4
BAR offset: 0x00000010
Advanced Features Capability Register
AF Capabilities register: 0x03
AF Structure Length: 0x06
Transaction Pending: on
Function Level Reset: on
AF Control register: 0x00
AF Status register: 0x00
Transaction Pending: off
Vendor Name: Intel (0x8086)
Device Name: 6 Series Chipset Family SMBus Controller (0x1c22)
Command register: 0x0003
I/O space accesses: on
Memory space accesses: on
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0280
Immediate Readiness: off
Interrupt status: inactive
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: serial bus (0x0c)
Subclass Name: SMBus (0x05)
Interface: 0x00
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 64-bit nonprefetchable memory
base: 0x00000000f1624000
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
type: I/O
base: 0x0000efa0
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x03 (pin C)
Interrupt line: 0x0b
Vendor Name: Intel (0x8086)
Device Name: Centrino Advanced-N 6205 WiFi (0x0085)
Command register: 0x0406
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: on
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: miscellaneous (0x80)
Interface: 0x00
Revision ID: 0x34
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
type: 64-bit nonprefetchable memory
base: 0x00000000f1500000
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x8086
Subsystem ID: 0x1311
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0xc8
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x07
Capability register at 0xc8
type: 0x01 (Power Management)
Capability register at 0xd0
type: 0x05 (MSI)
Capability register at 0xe0
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xc823
Version: 1.2
PME# clock: off
Device specific initialization: on
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0080
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: on
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address (lower) register: 0x00000000
Message Address (upper) register: 0x00000000
Message Data register: 0x0000
PCI Express Capabilities Register
Capability register: 0x0001
Capability version: 1
Device type: PCI Express Endpoint device
Slot implemented: off
Interrupt Message Number: 0x00
Device Capabilities Register: 0x10008ec0
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: 256ns to less than 512ns
Endpoint L1 Acceptable Latency: More than 64us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: on
Captured Slot Power Limit: 0W
Function-Level Reset Capability: on
Device Control Register: 0x0810
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: on
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: on
Max Read Request Size: 128 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x0006ec11
Maximum Link Speed: 2.5GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 2us - 4us
L1 Exit Latency: 16us to less than 32us
Port Number: 0
Clock Power Management: on
Surprise Down Error Report: off
Data Link Layer Link Active: off
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0142
Active State PM Control: L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: on
Extended Synch: off
Enable Clock Power Management: on
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x1011
Negotiated Link Speed: 2.5GT/s
Negotiated Link Width: x1 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: off
Link Bandwidth Management Status: off
Link Autonomous Bandwidth Status: off
Extended Capability Register at 0x100
type: 0x0001 (Advanced Error Reporting)
version: 1
Extended Capability Register at 0x140
type: 0x0003 (Device Serial Number)
version: 1
Advanced Error Reporting Register
Uncorrectable Error Status register: 0x00000000
Undefined: off
Data Link Protocol Error: off
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: off
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: off
Malformed TLP: off
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Uncorrectable Error Mask register: 0x00000000
Undefined: off
Data Link Protocol Error: off
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: off
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: off
Malformed TLP: off
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Uncorrectable Error Severity register: 0x00062011
Undefined: on
Data Link Protocol Error: on
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: on
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: on
Malformed TLP: on
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Correctable Error Status register: 0x00000000
Receiver Error: off
Bad TLP: off
Bad DLLP: off
REPLAY_NUM Rollover: off
Replay Timer Timeout: off
Advisory Non-Fatal Error: off
Corrected Internal Error: off
Header Log Overflow: off
Correctable Error Mask register: 0x00002000
Receiver Error: off
Bad TLP: off
Bad DLLP: off
REPLAY_NUM Rollover: off
Replay Timer Timeout: off
Advisory Non-Fatal Error: on
Corrected Internal Error: off
Header Log Overflow: off
Advanced Error Capabilities and Control register: 0x00000000
First Error Pointer: 0x0000
ECRC Generation Capable: off
ECRC Generation Enable: off
ECRC Check Capable: off
ECRC Check Enable: off
Multiple Header Recording Capable: off
Multiple Header Recording Enable: off
Completion Timeout Prefix/Header Log Capable: off
TLP Prefix Log Present: off
Header Log register:
0x11c: 0x00000000
0x120: 0x00000000 0x00000000 0x00000000
Device Serial Number Register
Serial Number: a0-88-b4-ff-ff-90-3b-c8
Vendor Name: Ricoh (0x1180)
Device Name: 5U823 SD/MMC Controller (0xe823)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: system (0x08)
Subclass Name: miscellaneous (0x80)
Interface: 0x00
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 64bytes (0x10)
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xf0d00000
Base address register at 0x14
not implemented
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0b
Capability register at 0x50
type: 0x05 (MSI)
Capability register at 0x78
type: 0x01 (Power Management)
Capability register at 0x80
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xfe03
Version: 1.2
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: on
D2 power management state support: on
PME# support D0: on
PME# support D1: on
PME# support D2: on
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00004000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion: disabled
Data Select: 0
Data Scale: 2
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0080
MSI Enabled: off
Multiple Message Capable: no (1 vector)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: on
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address (lower) register: 0x00000000
Message Address (upper) register: 0x00000000
Message Data register: 0x0000
PCI Express Capabilities Register
Capability register: 0x0001
Capability version: 1
Device type: PCI Express Endpoint device
Slot implemented: off
Interrupt Message Number: 0x00
Device Capabilities Register: 0x0590ffc0
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: More than 4us
Endpoint L1 Acceptable Latency: More than 64us
Attention Button Present: on
Attention Indicator Present: on
Power Indicator Present: on
Role-Based Error Report: on
Captured Slot Power Limit: 10.0W
Function-Level Reset Capability: off
Device Control Register: 0x2810
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: on
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: on
Max Read Request Size: 512 byte
Device Status Register: 0x0009
Correctable Error Detected: on
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: on
Aux Power Detected: off
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x0107ec11
Maximum Link Speed: 2.5GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 2us - 4us
L1 Exit Latency: More than 64us
Port Number: 1
Clock Power Management: on
Surprise Down Error Report: off
Data Link Layer Link Active: off
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0142
Active State PM Control: L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: on
Extended Synch: off
Enable Clock Power Management: on
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x1011
Negotiated Link Speed: 2.5GT/s
Negotiated Link Width: x1 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: off
Link Bandwidth Management Status: off
Link Autonomous Bandwidth Status: off
Advanced Error Reporting Register
Uncorrectable Error Status register: 0x00000000
Undefined: off
Data Link Protocol Error: off
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: off
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: off
Malformed TLP: off
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Uncorrectable Error Mask register: 0x00000000
Undefined: off
Data Link Protocol Error: off
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: off
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: off
Malformed TLP: off
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Uncorrectable Error Severity register: 0x00062031
Undefined: on
Data Link Protocol Error: on
Surprise Down Error: on
Poisoned TLP Received: off
Flow Control Protocol Error: on
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: on
Malformed TLP: on
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Correctable Error Status register: 0x00002000
Receiver Error: off
Bad TLP: off
Bad DLLP: off
REPLAY_NUM Rollover: off
Replay Timer Timeout: off
Advisory Non-Fatal Error: on
Corrected Internal Error: off
Header Log Overflow: off
Correctable Error Mask register: 0x00002000
Receiver Error: off
Bad TLP: off
Bad DLLP: off
REPLAY_NUM Rollover: off
Replay Timer Timeout: off
Advisory Non-Fatal Error: on
Corrected Internal Error: off
Header Log Overflow: off
Advanced Error Capabilities and Control register: 0x000000a0
First Error Pointer: 0x0000
ECRC Generation Capable: on
ECRC Generation Enable: off
ECRC Check Capable: on
ECRC Check Enable: off
Multiple Header Recording Capable: off
Multiple Header Recording Enable: off
Completion Timeout Prefix/Header Log Capable: off
TLP Prefix Log Present: off
Header Log register:
0x81c: 0x00000000
0x820: 0x00000000 0x00000000 0x00000000
Virtual Channel Register
Port VC Capability register 1: 0x00000000
Extended VC Count: 0
Low Priority Extended VC Count: 0
Reference Clock: 100ns
Port Arbitration Table Entry Size: 1bit
Port VC Capability register 2: 0x00000000
Hardware fixed arbitration scheme: off
WRR arbitration with 32 phases: off
WRR arbitration with 64 phases: off
WRR arbitration with 128 phases: off
VC Arbitration Table Offset: 0x0
Port VC Control register: 0x0000
VC Arbitration Select: 0x0
Port VC Status register: 0x0000
VC Arbitration Table Status: off
VC number 0
VC Resource Capability Register: 0x00000000
Non-configurable Hardware fixed arbitration scheme: off
WRR arbitration with 32 phases: off
WRR arbitration with 64 phases: off
WRR arbitration with 128 phases: off
Time-based WRR arbitration with 128 phases: off
WRR arbitration with 256 phases: off
Advanced Packet Switching: off
Reject Snoop Transaction: off
Maximum Time Slots: 1
Port Arbitration Table offset: 0x00
VC Resource Control Register: 0x800000ff
TC/VC Map: 0xff
Port Arbitration Select: 0x0
VC ID: 0
VC Enable: on
VC Resource Status Register: 0x00000000
Port Arbitration Table Status: off
VC Negotiation Pending: off
Vendor Name: NEC (0x1033)
Device Name: Renesas Electronics USB 3.0 Host Controller (0x0194)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Immediate Readiness: off
Interrupt status: inactive
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface Name: xHCI (0x30)
Revision ID: 0x04
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0bytes (0x00)
Base address register at 0x10
type: 64-bit nonprefetchable memory
base: 0x0000000000000000, disabled
Base address register at 0x18
not implemented
Base address register at 0x1c
not implemented
Base address register at 0x20
not implemented
Base address register at 0x24
not implemented
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x17aa
Subsystem ID: 0x21d2
Expansion ROM Base Address Register: 0x00000000
base: 0x00000000
Expansion ROM Enable: off
Validation Status: Validation not supported
Validation Details: 0x0
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x00
Capability register at 0x50
type: 0x01 (Power Management)
Capability register at 0x70
type: 0x05 (MSI)
Capability register at 0x90
type: 0x11 (MSI-X)
Capability register at 0xa0
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xc9c3
Version: 1.2
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: 375 mA
D1 power management state support: off
D2 power management state support: off
PME# support D0: on
PME# support D1: off
PME# support D2: off
PME# support D3 hot: on
PME# support D3 cold: on
Control/status register: 0x00000008
Power state: D0
PCI Express reserved: off
No soft reset: on
PME# assertion: disabled
Data Select: 0
Data Scale: 0
PME# status: off
Bridge Support Extensions register: 0x00
B2/B3 support: off
Bus Power/Clock Control Enable: off
Data register: 0x00
PCI Message Signaled Interrupt
Message Control register: 0x0086
MSI Enabled: off
Multiple Message Capable: yes (8 vectors)
Multiple Message Enabled: off (1 vector)
64 Bit Address Capable: on
Per-Vector Masking Capable: off
Extended Message Data Capable: off
Extended Message Data Enable: off
Message Address (lower) register: 0x00000000
Message Address (upper) register: 0x00000000
Message Data register: 0x0000
PCI Express Capabilities Register
Capability register: 0x0002
Capability version: 2
Device type: PCI Express Endpoint device
Slot implemented: off
Interrupt Message Number: 0x00
Device Capabilities Register: 0x00008fc0
Max Payload Size Supported: 128 bytes max
Phantom Functions Supported: not available
Extended Tag Field Supported: 5bit
Endpoint L0 Acceptable Latency: More than 4us
Endpoint L1 Acceptable Latency: More than 64us
Attention Button Present: off
Attention Indicator Present: off
Power Indicator Present: off
Role-Based Error Report: on
Captured Slot Power Limit: 0W
Function-Level Reset Capability: off
Device Control Register: 0x2810
Correctable Error Reporting Enable: off
Non Fatal Error Reporting Enable: off
Fatal Error Reporting Enable: off
Unsupported Request Reporting Enable: off
Enable Relaxed Ordering: on
Max Payload Size: 128 byte
Extended Tag Field Enable: off
Phantom Functions Enable: off
Aux Power PM Enable: off
Enable No Snoop: on
Max Read Request Size: 512 byte
Device Status Register: 0x0010
Correctable Error Detected: off
Non Fatal Error Detected: off
Fatal Error Detected: off
Unsupported Request Detected: off
Aux Power Detected: on
Transaction Pending: off
Emergency Power Reduction Detected: off
Link Capabilities Register: 0x0007ec12
Maximum Link Speed: 5.0GT/s
Maximum Link Width: x1 lanes
Active State PM Support: L0s and L1 supported
L0 Exit Latency: 2us - 4us
L1 Exit Latency: More than 64us
Port Number: 0
Clock Power Management: on
Surprise Down Error Report: off
Data Link Layer Link Active: off
Link BW Notification Capable: off
ASPM Optionally Compliance: off
Link Control Register: 0x0142
Active State PM Control: L1 Entry Enabled
Read Completion Boundary Control: 64bytes
Link Disable: off
Retrain Link: off
Common Clock Configuration: on
Extended Synch: off
Enable Clock Power Management: on
Hardware Autonomous Width Disable: off
Link Bandwidth Management Interrupt Enable: off
Link Autonomous Bandwidth Interrupt Enable: off
DRS Signaling Control: not reported
Link Status Register: 0x1012
Negotiated Link Speed: 5.0GT/s
Negotiated Link Width: x1 lanes
Training Error: off
Link Training: off
Slot Clock Configuration: on
Data Link Layer Link Active: off
Link Bandwidth Management Status: off
Link Autonomous Bandwidth Status: off
Device Capabilities 2: 0x00000810
Completion Timeout Ranges Supported: not supported
Completion Timeout Disable Supported: on
ARI Forwarding Supported: off
AtomicOp Routing Supported: off
32bit AtomicOp Completer Supported: off
64bit AtomicOp Completer Supported: off
128-bit CAS Completer Supported: off
No RO-enabled PR-PR passing: off
LTR Mechanism Supported: on
TPH Completer Supported: Not supported
LN System CLS: Not supported or not in effect
OBFF Supported: Not supported
Extended Fmt Field Supported: off
End-End TLP Prefix Supported: off
Max End-End TLP Prefixes: 4
Emergency Power Reduction Supported: Not supported
Emergency Power Reduction Initialization Required: off
FRS Supported: off
Device Control 2: 0x0000
Completion Timeout Value: 50us to 50ms
Completion Timeout Disabled: off
ARI Forwarding Enabled: off
AtomicOp Requester Enabled: off
AtomicOp Egress Blocking: off
IDO Request Enabled: off
IDO Completion Enabled: off
LTR Mechanism Enabled: off
Emergency Power Reduction Request: off
OBFF: Disabled
End-End TLP Prefix Blocking on: off
Link Control 2: 0x0002
Target Link Speed: 5.0GT/s
Enter Compliance Enabled: off
HW Autonomous Speed Disabled: off
Selectable De-emphasis: -6dB
Transmit Margin: 0
Enter Modified Compliance: off
Compliance SOS: off
Compliance Present/De-emphasis: -6dB
Link Status 2: 0x0000
Current De-emphasis Level: -6dB
Equalization Complete: off
Equalization Phase 1 Successful: off
Equalization Phase 2 Successful: off
Equalization Phase 3 Successful: off
Link Equalization Request: off
Retimer Presence Detected: off
MSI-X Capability Register
Message Control register: 0x0007
Table Size: 8
Function Mask: off
MSI-X Enable: off
Table offset register: 0x00001000
Table offset: 0x00001000
BIR: 0x0
Pending bit array register: 0x00001080
Pending bit array offset: 0x00001080
BIR: 0x0
Extended Capability Register at 0x100
type: 0x0001 (Advanced Error Reporting)
version: 1
Extended Capability Register at 0x140
type: 0x0003 (Device Serial Number)
version: 1
Extended Capability Register at 0x150
type: 0x0018 (Latency Tolerance Reporting)
version: 1
Advanced Error Reporting Register
Uncorrectable Error Status register: 0x00000000
Undefined: off
Data Link Protocol Error: off
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: off
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: off
Malformed TLP: off
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Uncorrectable Error Mask register: 0x00000000
Undefined: off
Data Link Protocol Error: off
Surprise Down Error: off
Poisoned TLP Received: off
Flow Control Protocol Error: off
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: off
Malformed TLP: off
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Uncorrectable Error Severity register: 0x00062030
Undefined: off
Data Link Protocol Error: on
Surprise Down Error: on
Poisoned TLP Received: off
Flow Control Protocol Error: on
Completion Timeout: off
Completer Abort: off
Unexpected Completion: off
Receiver Overflow: on
Malformed TLP: on
ECRC Error: off
Unsupported Request Error: off
ACS Violation: off
Uncorrectable Internal Error: off
MC Blocked TLP: off
AtomicOp Egress BLK: off
TLP Prefix Blocked Error: off
Poisoned TLP Egress Blocked: off
Correctable Error Status register: 0x00000000
Receiver Error: off
Bad TLP: off
Bad DLLP: off
REPLAY_NUM Rollover: off
Replay Timer Timeout: off
Advisory Non-Fatal Error: off
Corrected Internal Error: off
Header Log Overflow: off
Correctable Error Mask register: 0x00002000
Receiver Error: off
Bad TLP: off
Bad DLLP: off
REPLAY_NUM Rollover: off
Replay Timer Timeout: off
Advisory Non-Fatal Error: on
Corrected Internal Error: off
Header Log Overflow: off
Advanced Error Capabilities and Control register: 0x00000000
First Error Pointer: 0x0000
ECRC Generation Capable: off
ECRC Generation Enable: off
ECRC Check Capable: off
ECRC Check Enable: off
Multiple Header Recording Capable: off
Multiple Header Recording Enable: off
Completion Timeout Prefix/Header Log Capable: off
TLP Prefix Log Present: off
Header Log register:
0x11c: 0x00000000
0x120: 0x00000000 0x00000000 0x00000000
Device Serial Number Register
Serial Number: ff-ff-ff-ff-ff-ff-ff-ff
Latency Tolerance Reporting
Max Snoop Latency Register: 0x0000
Max Snoop Latency: 0ns
Max No-Snoop Latency Register: 0x0000
Max No-Snoop Latency: 0ns
