/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* When the Silicon Image 3112 retries a PCI memory read command,
* it may retry it as a memory read multiple command under some
* circumstances. This can totally confuse some PCI controllers,
* so ensure that it will never do this by making sure that the
* Read Threshold (FIFO Read Request Control) field of the FIFO
* Valid Byte Count and Control registers for both channels (BA5
* offset 0x40 and 0x44) are set to be at least as large as the
* cacheline size register.
* This may also happen on the 3114 (ragge 050527)
*/
static void
sii_fixup_cacheline(struct pciide_softc *sc, const struct pci_attach_args *pa,
int n)
{
pcireg_t cls, reg;
int i;
static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 };
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
/*
* Rev. <= 0x01 of the 3112 have a bug that can cause data
* corruption if DMA transfers cross an 8K boundary. This is
* apparently hard to tickle, but we'll go ahead and play it
* safe.
*/
if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_3112 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_AAR_1210SA) &&
PCI_REVISION(pa->pa_class) <= 0x01) {
sc->sc_dma_maxsegsz = 8192;
sc->sc_dma_boundary = 8192;
}
/*
* The 3112 either identifies itself as a RAID storage device
* or a Misc storage device. Fake up the interface bits for
* what our driver expects.
*/
if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCI_INTERFACE(pa->pa_class);
} else {
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
}
if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
PCIIDE_OPTIONS_NODMA) {
aprint_verbose(
", but unused (forced off by config file)");
sc->sc_dma_ok = 0;
return;
}
/*
* Slice off a subregion of BA5 for each of the channel's DMA
* registers.
*/
/*
* We must always keep the Interrupt Steering bit set in channel 2's
* IDEDMA_CMD register.
*/
if (channel == 2)
cp->idedma_cmd = IDEDMA_CMD_INT_STEER;
/*
* Reset everything and then unblock all of the interrupts.
*/
scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
scs_cmd | SII3114_RESET_BITS);
delay(50 * 1000);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
scs_cmd & SCS_CMD_M66EN);
delay(50 * 1000);
/*
* On the 3114, the BA5 register space is always enabled. In
* order to use the 3114 in any sane way, we must use this BA5
* register space, and so we consider it an error if we cannot
* map it.
*
* As a consequence of using BA5, our register mapping is different
* from a normal PCI IDE controller's, and so we are unable to use
* most of the common PCI IDE register mapping functions.
*/
if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
PCI_MAPREG_TYPE_MEM|
PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->sc_ba5_st, &sc->sc_ba5_sh,
NULL, &sc->sc_ba5_ss) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"unable to map SATALink BA5 register space\n");
return;
}
sc->sc_ba5_en = 1;
/*
* Set the Interrupt Steering bit in the IDEDMA_CMD register of
* channel 2. This is required at all times for proper operation
* when using the BA5 register space (otherwise interrupts from
* all 4 channels won't work).
*/
BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER);
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
sii3114_mapreg_dma(sc, pa);
aprint_verbose("\n");
/* Probe the drives using SATA registers.
* Note we can't use wdc_sataprobe as we may not be able to map ba5
*/
static void
sii3112_drv_probe(struct ata_channel *chp)
{
struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
uint32_t scontrol, sstatus;
uint8_t /* scnt, sn, */ cl, ch;
int s;
ata_channel_lock(chp);
/*
* The 3112 is a 2-port part, and only has one drive per channel
* (each port emulates a master drive).
*
* The 3114 is similar, but has 4 channels.
*/
/*
* Request communication initialization sequence, any speed.
* Performing this is the equivalent of an ATA Reset.
*/
scontrol = SControl_DET_INIT | SControl_SPD_ANY;
/*
* XXX We don't yet support SATA power management; disable all
* power management state transitions.
*/
scontrol |= SControl_IPM_NONE;
case SStatus_DET_DEV_NE:
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"port %d: device connected, but "
"communication not established\n", chp->ch_channel);
break;
case SStatus_DET_OFFLINE:
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"port %d: PHY offline\n", chp->ch_channel);
break;
case SStatus_DET_DEV:
/*
* XXX ATAPI detection doesn't currently work. Don't
* XXX know why. But, it's not like the standard method
* XXX can detect an ATAPI device connected via a SATA/PATA
* XXX bridge, so at least this is no worse. --thorpej
*/
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
WDSD_IBM | (0 << 4));
delay(10); /* 400ns delay */
/* Save register contents. */
#if 0
scnt = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_seccnt], 0);
sn = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_sector], 0);
#endif
cl = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_cyl_lo], 0);
ch = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_cyl_hi], 0);
#if 0
printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
device_xname(sc->sc_wdcdev.sc_atac.atac_dev), chp->ch_channel,
scnt, sn, cl, ch);
#endif
if (atabus_alloc_drives(chp, 1) != 0) {
ata_channel_unlock(chp);
return;
}
/*
* scnt and sn are supposed to be 0x1 for ATAPI, but in some
* cases we get wrong values here, so ignore it.
*/
s = splbio();
if (cl == 0x14 && ch == 0xeb)
chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI;
else
chp->ch_drive[0].drive_type = ATA_DRIVET_ATA;
splx(s);
/* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
dtm = 0;
for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
/* If no drive, skip */
if (drvp->drive_type == ATA_DRIVET_NONE)
continue;
if (drvp->drive_flags & ATA_DRIVE_UDMA) {
/* use Ultra/DMA */
s = splbio();
drvp->drive_flags &= ~ATA_DRIVE_DMA;
splx(s);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
dtm |= DTM_IDEx_DMA;
} else if (drvp->drive_flags & ATA_DRIVE_DMA) {
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
dtm |= DTM_IDEx_DMA;
} else {
dtm |= DTM_IDEx_PIO;
}
}
/*
* Nothing to do to setup modes; it is meaningless in S-ATA
* (but many S-ATA drives still want to get the SET_FEATURE
* command).
*/
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
idedma_ctl);
}
BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm);
}