/*
* Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PCI IDE controller driver.
*
* Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
* sys/dev/pci/ppb.c, revision 1.16).
*
* See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
* "Programming Interface for Bus Master IDE Controller, Revision 1.0
* 5/16/94" from the PCI SIG.
*
*/
#if NATA_DMA
static const char dmaerrfmt[] =
"%s:%d: unable to %s table DMA map for drive %d, error=%d\n";
#endif
/* Default product description for devices not known from this controller */
const struct pciide_product_desc default_product_desc = {
0,
0,
"Generic PCI IDE controller",
default_chip_map,
};
#if NATA_DMA
/* Set up DMA defaults; these might be adjusted by chip_map. */
sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
#endif
if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel),
PCI_MAPREG_TYPE_IO, 0,
&wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map %s channel ctl regs\n", cp->name);
bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
goto bad;
}
/*
* In native mode, 4 bytes of I/O space are mapped for the control
* register, the control register is at offset 2. Pass the generic
* code a handle for only one byte at the right offset.
*/
if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1,
&wdr->ctl_ioh) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"unable to subregion %s channel ctl regs\n", cp->name);
bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios);
goto bad;
}
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't subregion %s channel cmd regs\n",
cp->name);
goto bad;
}
}
wdc_init_shadow_regs(wdr);
wdr->data32iot = wdr->cmd_iot;
wdr->data32ioh = wdr->cmd_iohs[0];
return;
/*
* Map DMA registers
*
* Note that sc_dma_ok is the right variable to test to see if
* DMA can be done. If the interface doesn't support DMA,
* sc_dma_ok will never be non-zero. If the DMA regs couldn't
* be mapped, it'll be zero. I.e., sc_dma_ok will only be
* non-zero if the interface supports DMA and the registers
* could be mapped.
*
* XXX Note that despite the fact that the Bus Master IDE specs
* XXX say that "The bus master IDE function uses 16 bytes of IO
* XXX space," some controllers (at least the United
* XXX Microelectronics UM8886BF) place it in memory space.
*/
maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
PCIIDE_REG_BUS_MASTER_DMA);
switch (maptype) {
case PCI_MAPREG_TYPE_IO:
sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag,
PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO,
&addr, NULL, NULL) == 0);
if (sc->sc_dma_ok == 0) {
aprint_verbose(
", but unused (couldn't query registers)");
break;
}
if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE)
&& addr >= 0x10000) {
sc->sc_dma_ok = 0;
aprint_verbose(
", but unused (registers at unsafe address "
"%#lx)", (unsigned long)addr);
break;
}
/* FALLTHROUGH */
/*
* Set up the default handles for the DMA registers.
* Just reserve 32 bits for each handle, unless space
* doesn't permit it.
*/
for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) {
pc = &sc->pciide_channels[chan];
for (reg = 0; reg < IDEDMA_NREGS; reg++) {
size = 4;
if (size > (IDEDMA_SCH_OFFSET - reg))
size = IDEDMA_SCH_OFFSET - reg;
if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_SCH_OFFSET * chan + reg, size,
&pc->dma_iohs[reg]) != 0) {
sc->sc_dma_ok = 0;
aprint_verbose(", but can't subregion offset %d "
"size %lu", reg, (u_long)size);
return;
}
}
}
}
#endif /* NATA_DMA */
int
pciide_compat_intr(void *arg)
{
struct pciide_channel *cp = arg;
#ifdef DIAGNOSTIC
/* should only be called for a compat channel */
if (cp->compat == 0)
panic("pciide compat intr called for non-compat chan %p", cp);
#endif
return (wdcintr(&cp->ata_channel));
}
int
pciide_pci_intr(void *arg)
{
struct pciide_softc *sc = arg;
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
int i, rv, crv;
rv = 0;
for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->ata_channel;
/* If a compat channel skip. */
if (cp->compat)
continue;
/* if this channel not waiting for intr, skip */
if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0)
continue;
crv = wdcintr(wdc_cp);
if (crv == 0)
; /* leave rv alone */
else if (crv == 1)
rv = 1; /* claim the intr */
else if (rv == 0) /* crv should be -1 in this case */
rv = crv; /* if we've done no better, take it */
}
return (rv);
}
for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) {
bus_addr_t phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr;
bus_size_t len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len;
#ifdef DIAGNOSTIC
/* A segment must not cross a 64k boundary */
{
if ((phys & ~IDEDMA_BYTE_COUNT_MASK) !=
((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) {
printf("pciide_dma: seg %d addr 0x%" PRIx64
" len 0x%" PRIx64 " not properly aligned\n",
seg, (uint64_t)phys, (uint64_t)len);
panic("pciide_dma: buf align");
}
}
#endif
/*
* Some controllers get really upset if the length
* of any DMA segment is odd. This isn't something
* that's going to happen in normal steady-state
* operation (reading VM pages, etc.), but physio users
* don't have as many guard rails.
*
* Consider an 8K read request that starts at an odd
* offset within a page. At first blush, all of the
* checks pass because it's a sector-rounded size, but
* unless the buffer spans 2 physically contiguous pages,
* it's going to result in 2 odd-length DMA segments.
*
* Odd start addresses are also frowned upon, so we
* catch those here, too.
*
* Returning EINVAL here will cause the upper layers to
* fall back onto PIO.
*/
if ((phys & 1) != 0 || (len & 1) != 0) {
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"Invalid DMA segment: "
"seg %d addr 0x%" PRIx64 " len 0x%" PRIx64 "\n",
seg, (uint64_t)phys, (uint64_t)len);
bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
return EINVAL;
}
dma_maps->dma_table[seg].base_addr = htole32(phys);
dma_maps->dma_table[seg].byte_count =
htole32(len & IDEDMA_BYTE_COUNT_MASK);
ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n",
seg, le32toh(dma_maps->dma_table[seg].byte_count),
le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA);
if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
/* data underrun, may be a valid condition for ATAPI */
error |= WDC_DMAST_UNDER;
}
return error;
}
/* clear status bits in IDE DMA registers */
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
}
#endif /* NATA_DMA */
/* some common code used by several chip_map */
int
pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
{
struct pciide_channel *cp = &sc->pciide_channels[channel];
sc->wdc_chanarray[channel] = &cp->ata_channel;
cp->name = PCIIDE_CHANNEL_NAME(channel);
cp->ata_channel.ch_channel = channel;
cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
/* some common code used by several chip channel_map */
void
pciide_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp,
pcireg_t interface, int (*pci_intr)(void *))
{
struct ata_channel *wdc_cp = &cp->ata_channel;
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
wdr = CHAN_TO_WDC_REGS(&cp->ata_channel);
if (interface & PCIIDE_INTERFACE_PCI(channel))
pciide_mapregs_native(pa, cp, pciide_pci_intr);
else
pciide_mapregs_compat(pa, cp,
cp->ata_channel.ch_channel);
if (cp->ata_channel.ch_flags & ATACH_DISABLED)
continue;
/*
* Check to see if something appears to be there.
*/
failreason = NULL;
/*
* In native mode, always enable the controller. It's
* not possible to have an ISA board using the same address
* anyway.
*/
if (interface & PCIIDE_INTERFACE_PCI(channel)) {
wdcattach(&cp->ata_channel);
continue;
}
if (!wdcprobe(CHAN_TO_WDC_REGS(&cp->ata_channel))) {
failreason = "not responding; disabled or no drives?";
goto next;
}
/*
* Now, make sure it's actually attributable to this PCI IDE
* channel by trying to access the channel again while the
* PCI IDE controller's I/O space is disabled. (If the
* channel no longer appears to be there, it belongs to
* this controller.) YUCK!
*/
csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
csr & ~PCI_COMMAND_IO_ENABLE);
if (wdcprobe(CHAN_TO_WDC_REGS(&cp->ata_channel)))
failreason = "other hardware responding at addresses";
pci_conf_write(sc->sc_pc, sc->sc_tag,
PCI_COMMAND_STATUS_REG, csr);
next:
if (failreason) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"%s channel ignored (%s)\n", cp->name, failreason);
cp->ata_channel.ch_flags |= ATACH_DISABLED;
bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh,
wdr->cmd_ios);
bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh,
wdr->ctl_ios);
} else {
pciide_map_compat_intr(pa, cp,
cp->ata_channel.ch_channel);
wdcattach(&cp->ata_channel);
}
}
#if NATA_DMA
if (sc->sc_dma_ok == 0)
return;
/* Allocate DMA maps */
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
idedma_ctl = 0;
cp = &sc->pciide_channels[channel];
for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
/*
* we have not probed the drives yet, allocate
* resources for all of them.
*/
if (pciide_dma_table_setup(sc, channel, drive) != 0) {
/* Abort DMA setup */
aprint_error(
"%s:%d:%d: can't allocate DMA maps, "
"using PIO transfers\n",
device_xname(
sc->sc_wdcdev.sc_atac.atac_dev),
channel, drive);
sc->sc_dma_ok = 0;
sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = NULL;
break;
}
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
}
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot,
cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
}
}
#endif /* NATA_DMA */
}
/* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
KASSERT(cp->ata_channel.ch_ndrives != 0);
for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
drvp = &chp->ch_drive[drive];
/* If no drive, skip */
if (drvp->drive_type == ATA_DRIVET_NONE)
continue;
#if NATA_UDMA
if (drvp->drive_flags & ATA_DRIVE_UDMA) {
/* use Ultra/DMA */
s = splbio();
drvp->drive_flags &= ~ATA_DRIVE_DMA;
splx(s);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
} else
#endif /* NATA_UDMA */
if (drvp->drive_flags & ATA_DRIVE_DMA) {
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
}
}
/*
* Nothing to do to setup modes; it is meaningless in S-ATA
* (but many S-ATA drives still want to get the SET_FEATURE
* command).
*/
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
idedma_ctl);
}
#endif /* NATA_DMA */
}
