/*
* Copyright (c) 1998, 1999 and 2000
* HAYAKAWA Koichi. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* delay_ms() is wait in milliseconds. It should be used instead
* of delay() if you want to wait more than 1 ms.
*/
static inline void
delay_ms(int millis, struct pccbb_softc *sc)
{
if (cold)
delay(millis * 1000);
else
kpause("pccbb", false, mstohz(millis), NULL);
}
int pcicbbmatch(device_t, cfdata_t, void *);
void pccbbattach(device_t, device_t, void *);
void pccbbchilddet(device_t, device_t);
int pccbbdetach(device_t, int);
int pccbbintr(void *);
static void pci113x_insert(void *);
static int pccbbintr_function(struct pccbb_softc *);
static int pccbb_detect_card(struct pccbb_softc *);
#if 0
printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n",
pa->pa_memt, sc->sc_rbus_memt->rb_bt);
#endif
sc->sc_flags &= ~CBB_MEMHMAPPED;
/*
* MAP socket registers and ExCA registers on memory-space
* When no valid address is set on socket base registers (on pci
* config space), get it not polite way.
*/
sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);
if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 &&
PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {
/* The address must be valid. */
if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0,
&sc->sc_base_memt, &sc->sc_base_memh, &sockbase,
&sc->sc_base_size)) {
aprint_error_dev(self,
"can't map socket base address 0x%lx\n",
(unsigned long)sock_base);
/*
* I think it's funny: socket base registers must be
* mapped on memory space, but ...
*/
if (pci_mapreg_map(pa, PCI_SOCKBASE,
PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt,
&sc->sc_base_memh, &sockbase, &sc->sc_base_size)) {
aprint_error_dev(self,
"can't map socket base address"
" 0x%lx: io mode\n",
(unsigned long)sockbase);
/* give up... allocate reg space via rbus. */
pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0);
} else
sc->sc_flags |= CBB_MEMHMAPPED;
} else {
DPRINTF(("%s: socket base address 0x%lx\n",
device_xname(self), (unsigned long)sockbase));
sc->sc_flags |= CBB_MEMHMAPPED;
}
}
if (!TAILQ_EMPTY(&sc->sc_iowindow))
aprint_error_dev(self, "i/o windows not empty\n");
if (!TAILQ_EMPTY(&sc->sc_memwindow))
aprint_error_dev(self, "memory windows not empty\n");
/*
* static void pccbb_pci_callback(device_t self)
*
* The actual attach routine: get memory space for YENTA register
* space, setup YENTA register and route interrupt.
*
* This function should be deferred because this device may obtain
* memory space dynamically. This function must avoid obtaining
* memory area which has already kept for another device.
*/
static void
pccbb_pci_callback(device_t self)
{
struct pccbb_softc *sc = device_private(self);
pci_chipset_tag_t pc = sc->sc_pc;
bus_addr_t sockbase;
struct cbslot_attach_args cba;
struct pcmciabus_attach_args paa;
struct cardslot_attach_args caa;
device_t csc;
pccbb_pcmcia_attach_setup(sc, &paa);
caa.caa_cb_attach = NULL;
if (cba.cba_bus == 0)
aprint_error_dev(self,
"secondary bus number uninitialized; try PCI_BUS_FIXUP\n");
else
caa.caa_cb_attach = &cba;
caa.caa_16_attach = &paa;
pccbb_intrinit(sc);
if (NULL != (csc = config_found(self, &caa, cbbprint,
CFARGS(.iattr = "pcmciaslot")))) {
DPRINTF(("%s: found cardslot\n", __func__));
sc->sc_csc = device_private(csc);
}
return;
}
/*
* static void pccbb_chipinit(struct pccbb_softc *sc)
*
* This function initialize YENTA chip registers listed below:
* 1) PCI command reg,
* 2) PCI and CardBus latency timer,
* 3) route PCI interrupt,
* 4) close all memory and io windows.
* 5) turn off bus power.
* 6) card detect and power cycle interrupts on.
* 7) clear interrupt
*/
static void
pccbb_chipinit(struct pccbb_softc *sc)
{
pci_chipset_tag_t pc = sc->sc_pc;
pcitag_t tag = sc->sc_tag;
bus_space_tag_t bmt = sc->sc_base_memt;
bus_space_handle_t bmh = sc->sc_base_memh;
pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl,
sysctrl;
/*
* Set PCI command reg.
* Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.
*/
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
/* I believe it is harmless. */
csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_MASTER_ENABLE);
/* All O2 Micro chips have broken parity-error reporting
* until proven otherwise. The OZ6933 PCI-CardBus Bridge
* is known to have the defect---see PR kern/38698.
*/
if (sc->sc_chipset != CB_O2MICRO)
csr |= PCI_COMMAND_PARITY_ENABLE;
/* Route functional interrupts to PCI. */
bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG);
bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
/* assert reset */
bcr |= PCI_BRIDGE_CONTROL_SECBR;
/* Set master abort mode to 1, forward SERR# from secondary
* to primary, and detect parity errors on secondary.
*/
bcr |= PCI_BRIDGE_CONTROL_MABRT;
bcr |= PCI_BRIDGE_CONTROL_SERR;
bcr |= PCI_BRIDGE_CONTROL_PERE;
pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr);
switch (sc->sc_chipset) {
case CB_TI113X:
cbctl = pci_conf_read(pc, tag, PCI_CBCTRL);
/* This bit is shared, but may read as 0 on some chips, so set
it explicitly on both functions. */
cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA;
/* CSC intr enable */
cbctl |= PCI113X_CBCTRL_PCI_CSC;
/* functional intr prohibit | prohibit ISA routing */
cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
pci_conf_write(pc, tag, PCI_CBCTRL, cbctl);
break;
case CB_TI1420:
sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL);
mrburst = pccbb_burstup
? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN;
if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) {
printf("%s: %swrite bursts enabled\n",
device_xname(sc->sc_dev),
pccbb_burstup ? "read/" : "");
} else if (pccbb_burstup) {
printf("%s: enabling read/write bursts\n",
device_xname(sc->sc_dev));
sysctrl |= PCI1420_SYSCTRL_MRBURST;
pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
} else {
printf("%s: disabling read bursts, "
"enabling write bursts\n",
device_xname(sc->sc_dev));
sysctrl |= PCI1420_SYSCTRL_MRBURSTDN;
sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP;
pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
}
/*FALLTHROUGH*/
case CB_TI12XX:
/*
* Some TI 12xx (and [14][45]xx) based pci cards
* sometimes have issues with the MFUNC register not
* being initialized due to a bad EEPROM on board.
* Laptops that this matters on have this register
* properly initialized.
*
* The TI125X parts have a different register.
*/
mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC);
if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) {
/* Enable PCI interrupt /INTA */
mfunc |= PCI12XX_MFUNC_PIN0_INTA;
/* XXX this is TI1520 only */
if ((pci_conf_read(pc, tag, PCI_SYSCTRL) &
PCI12XX_SYSCTRL_INTRTIE) == 0)
/* Enable PCI interrupt /INTB */
mfunc |= PCI12XX_MFUNC_PIN1_INTB;
case CB_TI125X:
/*
* Disable zoom video. Some machines initialize this
* improperly and experience has shown that this helps
* prevent strange behavior.
*/
pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0);
/* Map and establish the interrupt. */
if (pci_intr_map(&sc->sc_pa, &ih)) {
aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
return;
}
intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
/*
* XXX pccbbintr should be called under the priority lower
* than any other hard interrupts.
*/
KASSERT(sc->sc_ih == NULL);
sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, pccbbintr, sc,
device_xname(sc->sc_dev));
if (sc->sc_ih == NULL) {
aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
if (intrstr != NULL)
aprint_error(" at %s\n", intrstr);
else
aprint_error("\n");
return;
}
aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
/*
* STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
* struct pcmciabus_attach_args *paa)
*
* This function attaches 16-bit PCcard bus.
*/
STATIC void
pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
struct pcmciabus_attach_args *paa)
{
/*
* We need to do a few things here:
* 1) Disable routing of CSC and functional interrupts to ISA IRQs by
* setting the IRQ numbers to 0.
* 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable
* routing of CSC interrupts (e.g. card removal) to PCI while in
* PCMCIA mode. We just leave this set all the time.
* 3) Enable card insertion/removal interrupts in case the chip also
* needs that while in PCMCIA mode.
* 4) Clear any pending CSC interrupt.
*/
Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE);
if (sc->sc_chipset == CB_TI113X) {
Pcic_write(sc, PCIC_CSC_INTR, 0);
} else {
Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE);
Pcic_read(sc, PCIC_CSC);
}
if (sockevent != 0) {
DPRINTF(("%s: enter sockevent %" PRIx32 "\n",
__func__, sockevent));
}
/* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER
* does occur in the wild. Check for a _POWER event before
* possibly exiting because of an _CSTS event.
*/
if (sockevent & CB_SOCKET_EVENT_POWER) {
DPRINTF(("Powercycling because of socket event\n"));
/* XXX: Does not happen when attaching a 16-bit card */
mutex_enter(&sc->sc_pwr_mtx);
sc->sc_pwrcycle++;
cv_signal(&sc->sc_pwr_cv);
mutex_exit(&sc->sc_pwr_mtx);
}
/* Sometimes a change of CSTSCHG# accompanies the first
* interrupt from an Atheros WLAN. That generates a
* CB_SOCKET_EVENT_CSTS event on the bridge. The event
* isn't interesting to pccbb(4), so we used to ignore the
* interrupt. Now, let the child devices try to handle
* the interrupt, instead. The Atheros NIC produces
* interrupts more reliably, now: used to be that it would
* only interrupt if the driver avoided powering down the
* NIC's cardslot, and then the NIC would only work after
* it was reset a second time.
*/
if (sockevent == 0 ||
(sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) {
/* This intr is not for me: it may be for my child devices. */
if (sc->sc_pil_intr_enable) {
return pccbbintr_function(sc);
} else {
return 0;
}
}
if (sockevent & CB_SOCKET_EVENT_CD) {
sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) {
/* A card should be removed. */
if (sc->sc_flags & CBB_CARDEXIST) {
DPRINTF(("%s: 0x%08x",
device_xname(sc->sc_dev), sockevent));
DPRINTF((" card removed, 0x%08x\n", sockstate));
sc->sc_flags &= ~CBB_CARDEXIST;
if ((csc = sc->sc_csc) == NULL)
;
else if (csc->sc_status &
CARDSLOT_STATUS_CARD_16) {
cardslot_event_throw(csc,
CARDSLOT_EVENT_REMOVAL_16);
} else if (csc->sc_status &
CARDSLOT_STATUS_CARD_CB) {
/* Cardbus intr removed */
cardslot_event_throw(csc,
CARDSLOT_EVENT_REMOVAL_CB);
}
} else if (sc->sc_flags & CBB_INSERTING) {
sc->sc_flags &= ~CBB_INSERTING;
callout_stop(&sc->sc_insert_ch);
}
} else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&
/*
* The pccbbintr may called from powerdown hook when
* the system resumed, to detect the card
* insertion/removal during suspension.
*/
(sc->sc_flags & CBB_CARDEXIST) == 0) {
if (sc->sc_flags & CBB_INSERTING) {
callout_stop(&sc->sc_insert_ch);
}
callout_schedule(&sc->sc_insert_ch, mstohz(200));
sc->sc_flags |= CBB_INSERTING;
}
}
return 1;
}
/*
* static int pccbbintr_function(struct pccbb_softc *sc)
*
* This function calls each interrupt handler registered at the
* bridge. The interrupt handlers are called in registered order.
*/
static int
pccbbintr_function(struct pccbb_softc *sc)
{
int retval = 0, val;
struct pccbb_intrhand_list *pil;
int s;
LIST_FOREACH(pil, &sc->sc_pil, pil_next) {
s = splraiseipl(pil->pil_icookie);
val = (*pil->pil_func)(pil->pil_arg);
splx(s);
retval = retval == 1 ? 1 :
retval == 0 ? val : val != 0 ? val : retval;
}
/*
* STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int)
*/
STATIC int
pccbb_ctrl(cardbus_chipset_tag_t ct, int command)
{
struct pccbb_softc *sc = (struct pccbb_softc *)ct;
switch (command) {
case CARDBUS_CD:
if (2 == pccbb_detect_card(sc)) {
int retval = 0;
int status = cb_detect_voltage(sc);
if (PCCARD_VCC_5V & status) {
retval |= CARDBUS_5V_CARD;
}
if (PCCARD_VCC_3V & status) {
retval |= CARDBUS_3V_CARD;
}
if (PCCARD_VCC_XV & status) {
retval |= CARDBUS_XV_CARD;
}
if (PCCARD_VCC_YV & status) {
retval |= CARDBUS_YV_CARD;
}
return retval;
} else {
return 0;
}
case CARDBUS_RESET:
return cb_reset(sc);
case CARDBUS_IO_ENABLE: /* fallthrough */
case CARDBUS_IO_DISABLE: /* fallthrough */
case CARDBUS_MEM_ENABLE: /* fallthrough */
case CARDBUS_MEM_DISABLE: /* fallthrough */
case CARDBUS_BM_ENABLE: /* fallthrough */
case CARDBUS_BM_DISABLE: /* fallthrough */
/* XXX: I think we don't need to call this function below. */
return pccbb_cardenable(sc, command);
}
return 0;
}
STATIC int
pccbb_power_ct(cardbus_chipset_tag_t ct, int command)
{
struct pccbb_softc *sc = (struct pccbb_softc *)ct;
return pccbb_power(sc, command);
}
/*
* STATIC int pccbb_power(cardbus_chipset_tag_t, int)
* This function returns true when it succeeds and returns false when
* it fails.
*/
STATIC int
pccbb_power(struct pccbb_softc *sc, int command)
{
uint32_t status, osock_ctrl, sock_ctrl, reg_ctrl;
bus_space_tag_t memt = sc->sc_base_memt;
bus_space_handle_t memh = sc->sc_base_memh;
int on = 0, pwrcycle, times;
struct timeval before, after, diff;
/*
* Wait as long as 200ms for a power-cycle interrupt. If
* interrupts are enabled, but the socket has already
* changed to the desired status, keep waiting for the
* interrupt. "Consuming" the interrupt in this way keeps
* the interrupt from prematurely waking some subsequent
* pccbb_power call.
*
* XXX Not every bridge interrupts on the ->OFF transition.
* XXX That's ok, we will time-out after 200ms.
*
* XXX The power cycle event will never happen when attaching
* XXX a 16-bit card. That's ok, we will time-out after
* XXX 200ms.
*/
for (times = 5; --times >= 0; ) {
if (cold)
DELAY(40 * 1000);
else {
(void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx,
mstohz(40));
if (pwrcycle == sc->sc_pwrcycle)
continue;
}
status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on)
break;
if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on)
break;
}
mutex_exit(&sc->sc_pwr_mtx);
microtime(&after);
timersub(&after, &before, &diff);
aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n",
(on && times < 0) ? " too long" : "", (long long)diff.tv_sec,
(long)diff.tv_usec);
/*
* Ok, wait a bit longer for things to settle.
*/
if (on && sc->sc_chipset == CB_TOPIC95B)
delay_ms(100, sc);
status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
if (on && sc->sc_chipset != CB_TOPIC95B) {
if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0)
aprint_error_dev(sc->sc_dev, "power on failed?\n");
}
/*
* STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function)
* This function enables and disables the card
*/
STATIC int
pccbb_cardenable(struct pccbb_softc *sc, int function)
{
uint32_t command =
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
DPRINTF(("pccbb_cardenable:"));
switch (function) {
case CARDBUS_IO_ENABLE:
command |= PCI_COMMAND_IO_ENABLE;
break;
case CARDBUS_IO_DISABLE:
command &= ~PCI_COMMAND_IO_ENABLE;
break;
case CARDBUS_MEM_ENABLE:
command |= PCI_COMMAND_MEM_ENABLE;
break;
case CARDBUS_MEM_DISABLE:
command &= ~PCI_COMMAND_MEM_ENABLE;
break;
case CARDBUS_BM_ENABLE:
command |= PCI_COMMAND_MASTER_ENABLE;
break;
case CARDBUS_BM_DISABLE:
command &= ~PCI_COMMAND_MASTER_ENABLE;
break;
default:
return 0;
}
/*
* int pccbb_io_close(cardbus_chipset_tag_t, int)
*/
static int
pccbb_io_close(cardbus_chipset_tag_t ct, int win)
{
struct pccbb_softc *sc = (struct pccbb_softc *)ct;
int basereg;
int limitreg;
if ((win < 0) || (win > 2)) {
#if defined DIAGNOSTIC
printf("cardbus_io_close: window out of range %d\n", win);
#endif
return 0;
}
/*
* static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct,
* int level,
* int (* func)(void *),
* void *arg)
*
* This function registers an interrupt handler at the bridge, in
* order not to call the interrupt handlers of child devices when
* a card-deletion interrupt occurs.
*
* The argument level is not used.
*/
static void *
pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level,
int (*func)(void *), void *arg)
{
struct pccbb_softc *sc = (struct pccbb_softc *)ct;
/*
* static void *pccbb_intr_establish(struct pccbb_softc *sc,
* int irq,
* int level,
* int (* func)(void *),
* void *arg)
*
* This function registers an interrupt handler at the bridge, in
* order not to call the interrupt handlers of child devices when
* a card-deletion interrupt occurs.
*
*/
static void *
pccbb_intr_establish(struct pccbb_softc *sc, int level,
int (*func)(void *), void *arg)
{
struct pccbb_intrhand_list *pil, *newpil;
/*
* static void *pccbb_intr_disestablish(struct pccbb_softc *sc,
* void *ih)
*
* This function removes an interrupt handler pointed by ih. ih
* should be the value returned by cardbus_intr_establish() or
* NULL.
*
* When ih is NULL, this function will do nothing.
*/
static void
pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih)
{
struct pccbb_intrhand_list *pil;
pcireg_t reg;
#if defined SHOW_REGS
static void
cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt,
bus_space_handle_t memh)
{
int i;
printf("PCI config regs:");
for (i = 0; i < 0x50; i += 4) {
if (i % 16 == 0)
printf("\n 0x%02x:", i);
printf(" %08x", pci_conf_read(pc, tag, i));
}
for (i = 0x80; i < 0xb0; i += 4) {
if (i % 16 == 0)
printf("\n 0x%02x:", i);
printf(" %08x", pci_conf_read(pc, tag, i));
}
if (memh == 0) {
printf("\n");
return;
}
printf("\nsocket regs:");
for (i = 0; i <= 0x10; i += 0x04)
printf(" %08x", bus_space_read_4(memt, memh, i));
printf("\nExCA regs:");
for (i = 0; i < 0x08; ++i)
printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i));
printf("\n");
return;
}
#endif
/*
* static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc,
* int busno, int function)
* This is the function to make a tag to access config space of
* a CardBus Card. It works same as pci_conf_read.
*/
static pcitag_t
pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function)
{
struct pccbb_softc *sc = (struct pccbb_softc *)cc;
/*
* pccbb_conf_read
*
* This is the function to read the config space of a CardBus card.
* It works the same as pci_conf_read(9).
*/
static pcireg_t
pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset)
{
struct pccbb_softc *sc = (struct pccbb_softc *)cc;
pcitag_t brtag = sc->sc_tag;
pcireg_t reg;
/*
* clear cardbus master abort status; it is OK to write without
* reading before because all bits are r/o or w1tc
*/
pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS,
CBB_SECSTATUS_CBMABORT);
reg = pci_conf_read(sc->sc_pc, tag, offset);
/* check cardbus master abort status */
if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS)
& CBB_SECSTATUS_CBMABORT)
return 0xffffffff;
return reg;
}
/*
* pccbb_conf_write
*
* This is the function to write the config space of a CardBus
* card. It works the same as pci_conf_write(9).
*/
static void
pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val)
{
struct pccbb_softc *sc = (struct pccbb_softc *)cc;
pci_conf_write(sc->sc_pc, tag, reg, val);
}
#if 0
STATIC int
pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask,
int speed, int flags,
bus_space_handle_t * iohp)
#endif
/*
* STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
* bus_addr_t start, bus_size_t size,
* bus_size_t align,
* struct pcmcia_io_handle *pcihp
*
* This function only allocates I/O region for pccard. This function
* never maps the allocated region to pccard I/O area.
*
* XXX: The interface of this function is not very good, I believe.
*/
STATIC int
pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
bus_addr_t ioaddr;
int flags = 0;
bus_space_tag_t iot;
bus_space_handle_t ioh;
bus_addr_t mask;
#if rbus
rbus_tag_t rb;
#endif
if (align == 0)
align = size; /* XXX: funny??? */
if (start != 0) {
/* XXX: assume all card decode lower 10 bits by its hardware */
mask = 0x3ff;
/* enforce to use only masked address */
start &= mask;
} else {
/*
* calculate mask:
* 1. get the most significant bit of size (call it msb).
* 2. compare msb with the value of size.
* 3. if size is larger, shift msb left once.
* 4. obtain mask value to decrement msb.
*/
bus_size_t size_tmp = size;
int shifts = 0;
/*
* STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
* struct pcmcia_io_handle *pcihp)
*
* This function only frees I/O region for pccard.
*
* XXX: The interface of this function is not very good, I believe.
*/
void
pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
struct pcmcia_io_handle *pcihp)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
#if !rbus
bus_space_tag_t iot = pcihp->iot;
#endif
bus_space_handle_t ioh = pcihp->ioh;
bus_size_t size = pcihp->size;
/*
* STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width,
* bus_addr_t offset, bus_size_t size,
* struct pcmcia_io_handle *pcihp,
* int *windowp)
*
* This function maps the allocated I/O region to pccard. This function
* never allocates any I/O region for pccard I/O area. I don't
* understand why the original authors of pcmciabus separated alloc and
* map. I believe the two must be unite.
*
* XXX: no wait timing control?
*/
int
pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
struct pcic_handle *ph = &sc->sc_pcmcia_h;
bus_addr_t ioaddr = pcihp->addr + offset;
int i, win;
#if defined CBB_DEBUG
static const char *width_names[] = { "dynamic", "io8", "io16" };
#endif
/* Sanity check I/O handle. */
if (!bus_space_is_equal(sc->sc_iot, pcihp->iot))
panic("pccbb_pcmcia_io_map iot is bogus");
/* XXX Sanity check offset/size. */
win = -1;
for (i = 0; i < PCIC_IO_WINS; i++) {
if ((ph->ioalloc & (1 << i)) == 0) {
win = i;
ph->ioalloc |= (1 << i);
break;
}
}
static int
pccbb_pcmcia_wait_ready(struct pccbb_softc *sc)
{
uint8_t stat;
int i;
/* wait an initial 10ms for quick cards */
stat = Pcic_read(sc, PCIC_IF_STATUS);
if (stat & PCIC_IF_STATUS_READY)
return 0;
pccbb_pcmcia_delay(sc, 10, "pccwr0");
for (i = 0; i < 50; i++) {
stat = Pcic_read(sc, PCIC_IF_STATUS);
if (stat & PCIC_IF_STATUS_READY)
return 0;
if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) !=
PCIC_IF_STATUS_CARDDETECT_PRESENT)
return ENXIO;
/* wait .1s (100ms) each iteration now */
pccbb_pcmcia_delay(sc, 100, "pccwr1");
}
printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n",
stat);
return EWOULDBLOCK;
}
/*
* Perform long (msec order) delay. timo is in milliseconds.
*/
static void
pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg)
{
#ifdef DIAGNOSTIC
if (timo <= 0)
panic("pccbb_pcmcia_delay: called with timeout %d", timo);
if (!curlwp)
panic("pccbb_pcmcia_delay: called in interrupt context");
#endif
DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo));
kpause(wmesg, false, uimax(mstohz(timo), 1), NULL);
}
/*
* STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
*
* This function enables the card. All information is stored in
* the first argument, pcmcia_chipset_handle_t.
*/
STATIC void
pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
struct pcic_handle *ph = &sc->sc_pcmcia_h;
pcireg_t spsr;
int voltage;
int win;
uint8_t power, intr;
#ifdef DIAGNOSTIC
int reg;
#endif
/* this bit is mostly stolen from pcic_attach_card */
DPRINTF(("pccbb_pcmcia_socket_enable: "));
/* get card Vcc info */
spsr =
bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
CB_SOCKET_STAT);
if (spsr & CB_SOCKET_STAT_5VCARD) {
DPRINTF(("5V card\n"));
voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC;
} else if (spsr & CB_SOCKET_STAT_3VCARD) {
DPRINTF(("3V card\n"));
voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC;
} else {
DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */
return;
}
/* zero out the address windows */
Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0);
/* power down the socket to reset it, clear the card reset pin */
pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
/* power off; assert output enable bit */
power = PCIC_PWRCTL_OE;
Pcic_write(sc, PCIC_PWRCTL, power);
/* power up the socket */
if (pccbb_power(sc, voltage) == 0)
return;
/*
* Table 4-18 and figure 4-6 of the PC Card specifiction say:
* Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above)
* RESET Width (Th (Hi-z RESET)) = 1ms
* RESET Width (Tw (RESET)) = 10us
*
* some machines require some more time to be settled
* for example old toshiba topic bridges!
* (100ms is added here).
*/
pccbb_pcmcia_delay(sc, 200 + 1, "pccen1");
#ifdef DIAGNOSTIC
reg = Pcic_read(sc, PCIC_IF_STATUS);
if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0)
printf("pccbb_pcmcia_socket_enable: no power, status=%x\n",
reg);
#endif
/* wait for the chip to finish initializing */
if (pccbb_pcmcia_wait_ready(sc)) {
#ifdef DIAGNOSTIC
printf("pccbb_pcmcia_socket_enable: never became ready\n");
#endif
/* XXX return a failure status?? */
pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
Pcic_write(sc, PCIC_PWRCTL, 0);
return;
}
/* reinstall all the memory and io mappings */
for (win = 0; win < PCIC_MEM_WINS; ++win)
if (ph->memalloc & (1 << win))
pccbb_pcmcia_do_mem_map(sc, win);
for (win = 0; win < PCIC_IO_WINS; ++win)
if (ph->ioalloc & (1 << win))
pccbb_pcmcia_do_io_map(sc, win);
}
/*
* STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph)
*
* This function disables the card. All information is stored in
* the first argument, pcmcia_chipset_handle_t.
*/
STATIC void
pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
uint8_t intr;
/*
* STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph)
*
* This function detects whether a card is in the slot or not.
* If a card is inserted, return 1. Otherwise, return 0.
*/
STATIC int
pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
#if 0
STATIC int
pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags,
bus_space_tag_t * memtp bus_space_handle_t * memhp)
#endif
/*
* STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
* bus_size_t size,
* struct pcmcia_mem_handle *pcmhp)
*
* This function only allocates memory region for pccard. This
* function never maps the allocated region to pccard memory area.
*
* XXX: Why the argument of start address is not in?
*/
STATIC int
pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
struct pcmcia_mem_handle *pcmhp)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
bus_space_handle_t memh;
bus_addr_t addr;
bus_size_t sizepg;
#if rbus
rbus_tag_t rb;
#endif
/* Check that the card is still there. */
if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) !=
PCIC_IF_STATUS_CARDDETECT_PRESENT)
return 1;
/* out of sc->memh, allocate as many pages as necessary */
/* convert size to PCIC pages */
/*
* This is not enough; when the requested region is on the page
* boundaries, this may calculate wrong result.
*/
sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE;
#if 0
if (sizepg > PCIC_MAX_MEM_PAGES)
return 1;
#endif
if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32))
return 1;
pcmhp->memt = sc->sc_memt;
pcmhp->memh = memh;
pcmhp->addr = addr;
pcmhp->size = size;
pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
/* What is mhandle? I feel it is very dirty and it must go trush. */
pcmhp->mhandle = 0;
/* No offset??? Funny. */
return 0;
}
/*
* STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
* struct pcmcia_mem_handle *pcmhp)
*
* This function release the memory space allocated by the function
* pccbb_pcmcia_mem_alloc().
*/
STATIC void
pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
struct pcmcia_mem_handle *pcmhp)
{
#if rbus
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
/*
* STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win)
*
* This function release the memory space allocated by the function
* pccbb_pcmcia_mem_alloc().
*/
STATIC void
pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win)
{
int regbase_win;
bus_addr_t phys_addr;
bus_addr_t phys_end;
struct pcic_handle *ph = &sc->sc_pcmcia_h;
/*
* STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
* bus_addr_t card_addr, bus_size_t size,
* struct pcmcia_mem_handle *pcmhp,
* bus_addr_t *offsetp, int *windowp)
*
* This function maps memory space allocated by the function
* pccbb_pcmcia_mem_alloc().
*/
STATIC int
pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp,
bus_size_t *offsetp, int *windowp)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
struct pcic_handle *ph = &sc->sc_pcmcia_h;
bus_addr_t busaddr;
long card_offset;
int win;
/* Check that the card is still there. */
if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) !=
PCIC_IF_STATUS_CARDDETECT_PRESENT)
return 1;
if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) {
panic("pccbb_pcmcia_mem_map memt is bogus");
}
busaddr = pcmhp->addr;
/*
* compute the address offset to the pcmcia address space for the
* pcic. this is intentionally signed. The masks and shifts below
* will cause TRT to happen in the pcic registers. Deal with making
* sure the address is aligned, and return the alignment offset.
*/
/*
* STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch,
* int window)
*
* This function unmaps memory space which mapped by the function
* pccbb_pcmcia_mem_map().
*/
STATIC void
pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
struct pcic_handle *ph = &sc->sc_pcmcia_h;
int reg;
if (window >= PCIC_MEM_WINS)
panic("pccbb_pcmcia_mem_unmap: window out of range");
/*
* STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
* struct pcmcia_function *pf,
* int ipl,
* int (*func)(void *),
* void *arg);
*
* This function enables PC-Card interrupt. PCCBB uses PCI interrupt line.
*/
STATIC void *
pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg)
{
struct pccbb_softc *sc = (struct pccbb_softc *)pch;
if (!(pf->cfe->flags & (PCMCIA_CFE_IRQLEVEL|PCMCIA_CFE_IRQPULSE))) {
/*
* XXX Noooooo! The interrupt flag must set properly!!
* dumb pcmcia driver!!
*/
DPRINTF(("%s does not provide edge nor pulse interrupt\n",
device_xname(sc->sc_dev)));
return NULL;
}
if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) {
if (align < 16) {
return 1;
}
/*
* XXX: align more than 0x1000 to avoid overwrapping
* memory windows for two or more devices. 0x1000
* means memory window's granularity.
*
* Two or more devices should be able to share same
* memory window region. However, overrapping memory
* window is not good because some devices, such as
* 3Com 3C575[BC], have a broken address decoder and
* intrude other's memory region.
*/
if (align < 0x1000) {
align = 0x1000;
}
} else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) {
if (align < 4) {
return 1;
}
/* XXX: hack for avoiding ISA image */
if (mask < 0x0100) {
mask = 0x3ff;
addr = 0x300;
}
} else {
DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is "
"NOT used. io: 0x%lx, mem: 0x%lx\n",
(unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot,
(unsigned long)sc->sc_memt));
return 1;
/* XXX: panic here? */
}
if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) {
aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n");
return 1;
}
for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) {
if (win[1].win_start == 0xffffffff) {
/* window 1 is not used */
if ((win[0].win_flags == chainp->wc_flags) &&
(win[0].win_limit + align >=
(chainp->wc_start & mask))) {
/* concatenate */
win[0].win_limit = chainp->wc_end & mask;
} else {
/* make new window */
win[1].win_start = chainp->wc_start & mask;
win[1].win_limit = chainp->wc_end & mask;
win[1].win_flags = chainp->wc_flags;
}
continue;
}
/* Both windows are engaged. */
if (win[0].win_flags == win[1].win_flags) {
/* same flags */
if (win[0].win_flags == chainp->wc_flags) {
if (win[1].win_start - (win[0].win_limit +
align) <
(chainp->wc_start & mask) -
((chainp->wc_end & mask) + align)) {
/*
* merge window 0 and 1, and set win1
* to chainp
*/
win[0].win_limit = win[1].win_limit;
win[1].win_start =
chainp->wc_start & mask;
win[1].win_limit =
chainp->wc_end & mask;
} else {
win[1].win_limit =
chainp->wc_end & mask;
}
} else {
/* different flags */
/* concatenate win0 and win1 */
win[0].win_limit = win[1].win_limit;
/* allocate win[1] to new space */
win[1].win_start = chainp->wc_start & mask;
win[1].win_limit = chainp->wc_end & mask;
win[1].win_flags = chainp->wc_flags;
}
} else {
/* the flags of win[0] and win[1] is different */
if (win[0].win_flags == chainp->wc_flags) {
win[0].win_limit = chainp->wc_end & mask;
/*
* XXX this creates overlapping windows, so
* what should the poor bridge do if one is
* cachable, and the other is not?
*/
aprint_error_dev(sc->sc_dev,
"overlapping windows\n");
} else {
win[1].win_limit = chainp->wc_end & mask;
}
}
}
/*
* check for card insertion or removal during suspend period.
* XXX: the code can't cope with card swap (remove then
* insert). how can we detect such situation?
*/
(void)pccbbintr(sc);
