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/*
* Copyright (c) 2011 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Coyote Point Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef RSC
/*
* HW RSC control:
* this feature only works with
* IPv4, and only on 82599 and later.
* Also this will cause IP forwarding to
* fail and that can't be controlled by
* the stack as LRO can. For all these
* reasons I've deemed it best to leave
* this off and not bother with a tuneable
* interface, this would need to be compiled
* to enable.
*/
static bool ixgbe_rsc_enable = FALSE;
#endif
#ifdef IXGBE_FDIR
/*
* For Flow Director: this is the
* number of TX packets we sample
* for the filter pool, this means
* every 20th packet will be probed.
*
* This feature can be disabled by
* setting this to 0.
*/
static int atr_sample_rate = 20;
#endif
/************************************************************************
* ixgbe_legacy_start_locked - Transmit entry point
*
* Called by the stack to initiate a transmit.
* The driver will remain in this routine as long as there are
* packets to transmit and transmit resources are available.
* In case resources are not available, the stack is notified
* and the packet is requeued.
************************************************************************/
int
ixgbe_legacy_start_locked(struct ifnet *ifp, struct tx_ring *txr)
{
int rc;
struct mbuf *m_head;
struct ixgbe_softc *sc = txr->sc;
IXGBE_TX_LOCK_ASSERT(txr);
if (sc->link_active != LINK_STATE_UP) {
/*
* discard all packets buffered in IFQ to avoid
* sending old packets at next link up timing.
*/
ixgbe_drain(ifp, txr);
return (ENETDOWN);
}
if ((ifp->if_flags & IFF_RUNNING) == 0)
return (ENETDOWN);
if (txr->txr_no_space)
return (ENETDOWN);
while (!IFQ_IS_EMPTY(&ifp->if_snd)) {
if (txr->tx_avail <= IXGBE_QUEUE_MIN_FREE)
break;
IFQ_POLL(&ifp->if_snd, m_head);
if (m_head == NULL)
break;
if ((rc = ixgbe_xmit(txr, m_head)) == EAGAIN) {
break;
}
IFQ_DEQUEUE(&ifp->if_snd, m_head);
if (rc != 0) {
m_freem(m_head);
continue;
}
/* Send a copy of the frame to the BPF listener */
bpf_mtap(ifp, m_head, BPF_D_OUT);
}
/************************************************************************
* ixgbe_legacy_start
*
* Called by the stack, this always uses the first tx ring,
* and should not be used with multiqueue tx enabled.
************************************************************************/
void
ixgbe_legacy_start(struct ifnet *ifp)
{
struct ixgbe_softc *sc = ifp->if_softc;
struct tx_ring *txr = sc->tx_rings;
/*
* When doing RSS, map it to the same outbound queue
* as the incoming flow would be mapped to.
*
* If everything is setup correctly, it should be the
* same bucket that the current CPU we're on is.
*/
#ifdef RSS
if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
if ((sc->feat_en & IXGBE_FEATURE_RSS) &&
(rss_hash2bucket(m->m_pkthdr.flowid, M_HASHTYPE_GET(m),
&bucket_id) == 0)) {
i = bucket_id % sc->num_queues;
#ifdef IXGBE_DEBUG
if (bucket_id > sc->num_queues)
if_printf(ifp,
"bucket_id (%d) > num_queues (%d)\n",
bucket_id, sc->num_queues);
#endif
} else
i = m->m_pkthdr.flowid % sc->num_queues;
} else
#endif /* 0 */
i = (cpu_index(curcpu()) % ncpu) % sc->num_queues;
/* Check for a hung queue and pick alternative */
if (((1ULL << i) & sc->active_queues) == 0)
i = ffs64(sc->active_queues);
txr = &sc->tx_rings[i];
if (__predict_false(!pcq_put(txr->txr_interq, m))) {
m_freem(m);
IXGBE_EVC_ADD(&txr->pcq_drops, 1);
return ENOBUFS;
}
#ifdef IXGBE_ALWAYS_TXDEFER
kpreempt_disable();
softint_schedule(txr->txr_si);
kpreempt_enable();
#else
if (IXGBE_TX_TRYLOCK(txr)) {
ixgbe_mq_start_locked(ifp, txr);
IXGBE_TX_UNLOCK(txr);
} else {
if (sc->txrx_use_workqueue) {
u_int *enqueued;
/*
* This function itself is not called in interrupt
* context, however it can be called in fast softint
* context right after receiving forwarding packets.
* So, it is required to protect workqueue from twice
* enqueuing when the machine uses both spontaneous
* packets and forwarding packets.
*/
enqueued = percpu_getref(sc->txr_wq_enqueued);
if (*enqueued == 0) {
*enqueued = 1;
percpu_putref(sc->txr_wq_enqueued);
workqueue_enqueue(sc->txr_wq,
&txr->wq_cookie, curcpu());
} else
percpu_putref(sc->txr_wq_enqueued);
} else {
kpreempt_disable();
softint_schedule(txr->txr_si);
kpreempt_enable();
}
}
#endif
if (txr->sc->link_active != LINK_STATE_UP) {
/*
* discard all packets buffered in txr_interq to avoid
* sending old packets at next link up timing.
*/
ixgbe_drain(ifp, txr);
return (ENETDOWN);
}
if ((ifp->if_flags & IFF_RUNNING) == 0)
return (ENETDOWN);
if (txr->txr_no_space)
return (ENETDOWN);
/* Process the queue */
while ((next = pcq_get(txr->txr_interq)) != NULL) {
if ((err = ixgbe_xmit(txr, next)) != 0) {
m_freem(next);
/* All errors are counted in ixgbe_xmit() */
break;
}
enqueued++;
#if __FreeBSD_version >= 1100036
/*
* Since we're looking at the tx ring, we can check
* to see if we're a VF by examining our tail register
* address.
*/
if ((txr->sc->feat_en & IXGBE_FEATURE_VF) &&
(next->m_flags & M_MCAST))
if_inc_counter(ifp, IFCOUNTER_OMCASTS, 1);
#endif
/* Send a copy of the frame to the BPF listener */
bpf_mtap(ifp, next, BPF_D_OUT);
if ((ifp->if_flags & IFF_RUNNING) == 0)
break;
}
if (txr->tx_avail < IXGBE_TX_CLEANUP_THRESHOLD(txr->sc))
ixgbe_txeof(txr);
return (err);
} /* ixgbe_mq_start_locked */
/************************************************************************
* ixgbe_deferred_mq_start
*
* Called from a softint and workqueue (indirectly) to drain queued
* transmit packets.
************************************************************************/
void
ixgbe_deferred_mq_start(void *arg)
{
struct tx_ring *txr = arg;
struct ixgbe_softc *sc = txr->sc;
struct ifnet *ifp = sc->ifp;
if (vlan_has_tag(m_head))
cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
/*
* Important to capture the first descriptor
* used because it will contain the index of
* the one we tell the hardware to report back
*/
first = txr->next_avail_desc;
txbuf = &txr->tx_buffers[first];
map = txbuf->map;
/*
* Map the packet for DMA.
*/
retry:
error = bus_dmamap_load_mbuf(txr->txtag->dt_dmat, map, m_head,
BUS_DMA_NOWAIT);
if (__predict_false(error)) {
struct mbuf *m;
switch (error) {
case EAGAIN:
txr->q_eagain_tx_dma_setup++;
return EAGAIN;
case ENOMEM:
txr->q_enomem_tx_dma_setup++;
return EAGAIN;
case EFBIG:
/* Try it again? - one try */
if (remap == TRUE) {
remap = FALSE;
/*
* XXX: m_defrag will choke on
* non-MCLBYTES-sized clusters
*/
txr->q_efbig_tx_dma_setup++;
m = m_defrag(m_head, M_NOWAIT);
if (m == NULL) {
txr->q_mbuf_defrag_failed++;
return ENOBUFS;
}
m_head = m;
goto retry;
} else {
txr->q_efbig2_tx_dma_setup++;
return error;
}
case EINVAL:
txr->q_einval_tx_dma_setup++;
return error;
default:
txr->q_other_tx_dma_setup++;
return error;
}
}
/* Make certain there are enough descriptors */
if (txr->tx_avail < (map->dm_nsegs + 2)) {
txr->txr_no_space = true;
IXGBE_EVC_ADD(&txr->no_desc_avail, 1);
ixgbe_dmamap_unload(txr->txtag, txbuf->map);
return EAGAIN;
}
/*
* Set up the appropriate offload context if requested,
* this may consume one TX descriptor.
*/
error = ixgbe_tx_ctx_setup(txr, m_head, &cmd_type_len, &olinfo_status);
if (__predict_false(error)) {
return (error);
}
#ifdef IXGBE_FDIR
/* Do the flow director magic */
if ((sc->feat_en & IXGBE_FEATURE_FDIR) &&
(txr->atr_sample) && (!sc->fdir_reinit)) {
++txr->atr_count;
if (txr->atr_count >= atr_sample_rate) {
ixgbe_atr(txr, m_head);
txr->atr_count = 0;
}
}
#endif
olinfo_status |= IXGBE_ADVTXD_CC;
i = txr->next_avail_desc;
for (j = 0; j < map->dm_nsegs; j++) {
bus_size_t seglen;
uint64_t segaddr;
txbuf->m_head = m_head;
/*
* Here we swap the map so the last descriptor,
* which gets the completion interrupt has the
* real map, and the first descriptor gets the
* unused map from this descriptor.
*/
txr->tx_buffers[first].map = txbuf->map;
txbuf->map = map;
bus_dmamap_sync(txr->txtag->dt_dmat, map, 0, m_head->m_pkthdr.len,
BUS_DMASYNC_PREWRITE);
/* Set the EOP descriptor that will be marked done */
txbuf = &txr->tx_buffers[first];
txbuf->eop = txd;
ixgbe_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
/*
* Advance the Transmit Descriptor Tail (Tdt), this tells the
* hardware that this frame is available to transmit.
*/
IXGBE_EVC_ADD(&txr->total_packets, 1);
IXGBE_WRITE_REG(&sc->hw, txr->tail, i);
/************************************************************************
* ixgbe_allocate_transmit_buffers
*
* Allocate memory for tx_buffer structures. The tx_buffer stores all
* the information needed to transmit a packet on the wire. This is
* called only once at attach, setup is done every reset.
************************************************************************/
static int
ixgbe_allocate_transmit_buffers(struct tx_ring *txr)
{
struct ixgbe_softc *sc = txr->sc;
device_t dev = sc->dev;
struct ixgbe_tx_buf *txbuf;
int error, i;
/* Create the descriptor buffer dma maps */
txbuf = txr->tx_buffers;
for (i = 0; i < sc->num_tx_desc; i++, txbuf++) {
error = ixgbe_dmamap_create(txr->txtag, 0, &txbuf->map);
if (error != 0) {
aprint_error_dev(dev,
"Unable to create TX DMA map (%d)\n", error);
goto fail;
}
}
return 0;
fail:
/* We free all, it handles case where we are in the middle */
#if 0 /* XXX was FreeBSD */
ixgbe_free_transmit_structures(sc);
#else
ixgbe_free_transmit_buffers(txr);
#endif
return (error);
} /* ixgbe_allocate_transmit_buffers */
/* Clear the old ring contents */
IXGBE_TX_LOCK(txr);
#ifdef DEV_NETMAP
if (sc->feat_en & IXGBE_FEATURE_NETMAP) {
/*
* (under lock): if in netmap mode, do some consistency
* checks and set slot to entry 0 of the netmap ring.
*/
slot = netmap_reset(na, NR_TX, txr->me, 0);
}
#endif /* DEV_NETMAP */
/* Free any existing tx buffers. */
txbuf = txr->tx_buffers;
for (int i = 0; i < txr->num_desc; i++, txbuf++) {
if (txbuf->m_head != NULL) {
bus_dmamap_sync(txr->txtag->dt_dmat, txbuf->map,
0, txbuf->m_head->m_pkthdr.len,
BUS_DMASYNC_POSTWRITE);
ixgbe_dmamap_unload(txr->txtag, txbuf->map);
m_freem(txbuf->m_head);
txbuf->m_head = NULL;
}
#ifdef DEV_NETMAP
/*
* In netmap mode, set the map for the packet buffer.
* NOTE: Some drivers (not this one) also need to set
* the physical buffer address in the NIC ring.
* Slots in the netmap ring (indexed by "si") are
* kring->nkr_hwofs positions "ahead" wrt the
* corresponding slot in the NIC ring. In some drivers
* (not here) nkr_hwofs can be negative. Function
* netmap_idx_n2k() handles wraparounds properly.
*/
if ((sc->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
int si = netmap_idx_n2k(na->tx_rings[txr->me], i);
netmap_load_map(na, txr->txtag,
txbuf->map, NMB(na, slot + si));
}
#endif /* DEV_NETMAP */
/* First check if TSO is to be used */
if (mp->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) {
int rv = ixgbe_tso_setup(txr, mp, cmd_type_len, olinfo_status);
if (rv != 0)
IXGBE_EVC_ADD(&sc->tso_err, 1);
return rv;
}
if ((mp->m_pkthdr.csum_flags & M_CSUM_OFFLOAD) == 0)
offload = FALSE;
/* Indicate the whole packet as payload when not doing TSO */
*olinfo_status |= mp->m_pkthdr.len << IXGBE_ADVTXD_PAYLEN_SHIFT;
/*
* In advanced descriptors the vlan tag must
* be placed into the context descriptor. Hence
* we need to make one even if not doing offloads.
*/
if (vlan_has_tag(mp)) {
vtag = htole16(vlan_get_tag(mp));
vlan_macip_lens |= (vtag << IXGBE_ADVTXD_VLAN_SHIFT);
} else if (!(txr->sc->feat_en & IXGBE_FEATURE_NEEDS_CTXD) &&
(offload == FALSE))
return (0);
/* Set the ether header length */
vlan_macip_lens |= ehdrlen << IXGBE_ADVTXD_MACLEN_SHIFT;
if (offload == FALSE)
goto no_offloads;
/*
* If the first mbuf only includes the ethernet header,
* jump to the next one
* XXX: This assumes the stack splits mbufs containing headers
* on header boundaries
* XXX: And assumes the entire IP header is contained in one mbuf
*/
if (mp->m_len == ehdrlen && mp->m_next)
l3d = mtod(mp->m_next, char *);
else
l3d = mtod(mp, char *) + ehdrlen;
/************************************************************************
* ixgbe_txeof
*
* Examine each tx_buffer in the used queue. If the hardware is done
* processing the packet then free associated resources. The
* tx_buffer is put back on the free queue.
************************************************************************/
bool
ixgbe_txeof(struct tx_ring *txr)
{
struct ixgbe_softc *sc = txr->sc;
struct ifnet *ifp = sc->ifp;
struct ixgbe_tx_buf *buf;
union ixgbe_adv_tx_desc *txd;
u32 work, processed = 0;
u32 limit = sc->tx_process_limit;
u16 avail;
KASSERT(mutex_owned(&txr->tx_mtx));
#ifdef DEV_NETMAP
if ((sc->feat_en & IXGBE_FEATURE_NETMAP) &&
(sc->ifp->if_capenable & IFCAP_NETMAP)) {
struct netmap_sc *na = NA(sc->ifp);
struct netmap_kring *kring = na->tx_rings[txr->me];
txd = txr->tx_base;
bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
BUS_DMASYNC_POSTREAD);
/*
* In netmap mode, all the work is done in the context
* of the client thread. Interrupt handlers only wake up
* clients, which may be sleeping on individual rings
* or on a global resource for all rings.
* To implement tx interrupt mitigation, we wake up the client
* thread roughly every half ring, even if the NIC interrupts
* more frequently. This is implemented as follows:
* - ixgbe_txsync() sets kring->nr_kflags with the index of
* the slot that should wake up the thread (nkr_num_slots
* means the user thread should not be woken up);
* - the driver ignores tx interrupts unless netmap_mitigate=0
* or the slot has the DD bit set.
*/
if (kring->nr_kflags < kring->nkr_num_slots &&
le32toh(txd[kring->nr_kflags].wb.status) & IXGBE_TXD_STAT_DD) {
netmap_tx_irq(ifp, txr->me);
}
return false;
}
#endif /* DEV_NETMAP */
/* Get work starting point */
work = txr->next_to_clean;
buf = &txr->tx_buffers[work];
txd = &txr->tx_base[work];
work -= txr->num_desc; /* The distance to ring end */
avail = txr->tx_avail;
ixgbe_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
BUS_DMASYNC_POSTREAD);
do {
union ixgbe_adv_tx_desc *eop = buf->eop;
if (eop == NULL) /* No work */
break;
if ((le32toh(eop->wb.status) & IXGBE_TXD_STAT_DD) == 0)
break; /* I/O not complete */
/* We clean the range if multi segment */
while (txd != eop) {
++txd;
++buf;
++work;
/* wrap the ring? */
if (__predict_false(!work)) {
work -= txr->num_desc;
buf = txr->tx_buffers;
txd = txr->tx_base;
}
if (buf->m_head) {
txr->bytes +=
buf->m_head->m_pkthdr.len;
bus_dmamap_sync(txr->txtag->dt_dmat,
buf->map,
0, buf->m_head->m_pkthdr.len,
BUS_DMASYNC_POSTWRITE);
ixgbe_dmamap_unload(txr->txtag,
buf->map);
m_freem(buf->m_head);
buf->m_head = NULL;
}
++avail;
buf->eop = NULL;
}
++processed;
/* Try the next packet */
++txd;
++buf;
++work;
/* reset with a wrap */
if (__predict_false(!work)) {
work -= txr->num_desc;
buf = txr->tx_buffers;
txd = txr->tx_base;
}
prefetch(txd);
} while (__predict_true(--limit));
/*
* Queue Hang detection, we know there's
* work outstanding or the first return
* would have been taken, so increment busy
* if nothing managed to get cleaned, then
* in local_timer it will be checked and
* marked as HUNG if it exceeds a MAX attempt.
*/
if ((processed == 0) && (txr->busy != IXGBE_QUEUE_HUNG))
++txr->busy;
/*
* If anything gets cleaned we reset state to 1,
* note this will turn off HUNG if its set.
*/
if (processed)
txr->busy = 1;
if (txr->tx_avail == txr->num_desc)
txr->busy = 0;
#ifdef RSC
/************************************************************************
* ixgbe_rsc_count
*
* Used to detect a descriptor that has been merged by Hardware RSC.
************************************************************************/
static inline u32
ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
{
return (le32toh(rx->wb.lower.lo_dword.data) &
IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
} /* ixgbe_rsc_count */
/************************************************************************
* ixgbe_setup_hw_rsc
*
* Initialize Hardware RSC (LRO) feature on 82599
* for an RX ring, this is toggled by the LRO capability
* even though it is transparent to the stack.
*
* NOTE: Since this HW feature only works with IPv4 and
* testing has shown soft LRO to be as effective,
* this feature will be disabled by default.
************************************************************************/
static void
ixgbe_setup_hw_rsc(struct rx_ring *rxr)
{
struct ixgbe_softc *sc = rxr->sc;
struct ixgbe_hw *hw = &sc->hw;
u32 rscctrl, rdrxctl;
/* If turning LRO/RSC off we need to disable it */
if ((sc->ifp->if_capenable & IFCAP_LRO) == 0) {
rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxr->me));
rscctrl &= ~IXGBE_RSCCTL_RSCEN;
return;
}
rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxr->me));
rscctrl |= IXGBE_RSCCTL_RSCEN;
/*
* Limit the total number of descriptors that
* can be combined, so it does not exceed 64K
*/
if (rxr->mbuf_sz == MCLBYTES)
rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
else if (rxr->mbuf_sz == MJUMPAGESIZE)
rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
else if (rxr->mbuf_sz == MJUM9BYTES)
rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
else /* Using 16K cluster */
rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
/************************************************************************
* ixgbe_refresh_mbufs
*
* Refresh mbuf buffers for RX descriptor rings
* - now keeps its own state so discards due to resource
* exhaustion are unnecessary, if an mbuf cannot be obtained
* it just returns, keeping its placeholder, thus it can simply
* be recalled to try again.
************************************************************************/
static void
ixgbe_refresh_mbufs(struct rx_ring *rxr, int limit)
{
struct ixgbe_softc *sc = rxr->sc;
struct ixgbe_rx_buf *rxbuf;
struct mbuf *mp;
int i, error;
bool refreshed = false;
i = rxr->next_to_refresh;
/* next_to_refresh points to the previous one */
if (++i == rxr->num_desc)
i = 0;
while (i != limit) {
rxbuf = &rxr->rx_buffers[i];
if (__predict_false(rxbuf->buf == NULL)) {
mp = ixgbe_getcl();
if (mp == NULL) {
IXGBE_EVC_ADD(&rxr->no_mbuf, 1);
goto update;
}
mp->m_pkthdr.len = mp->m_len = rxr->mbuf_sz;
IXGBE_M_ADJ(sc, rxr, mp);
} else
mp = rxbuf->buf;
/* If we're dealing with an mbuf that was copied rather
* than replaced, there's no need to go through busdma.
*/
if ((rxbuf->flags & IXGBE_RX_COPY) == 0) {
/* Get the memory mapping */
ixgbe_dmamap_unload(rxr->ptag, rxbuf->pmap);
error = bus_dmamap_load_mbuf(rxr->ptag->dt_dmat,
rxbuf->pmap, mp, BUS_DMA_NOWAIT);
if (__predict_false(error != 0)) {
device_printf(sc->dev, "Refresh mbufs: "
"payload dmamap load failure - %d\n",
error);
m_free(mp);
rxbuf->buf = NULL;
goto update;
}
rxbuf->buf = mp;
bus_dmamap_sync(rxr->ptag->dt_dmat, rxbuf->pmap,
0, mp->m_pkthdr.len, BUS_DMASYNC_PREREAD);
rxbuf->addr = rxr->rx_base[i].read.pkt_addr =
htole64(rxbuf->pmap->dm_segs[0].ds_addr);
} else {
rxr->rx_base[i].read.pkt_addr = rxbuf->addr;
rxbuf->flags &= ~IXGBE_RX_COPY;
}
refreshed = true;
/* next_to_refresh points to the previous one */
rxr->next_to_refresh = i;
if (++i == rxr->num_desc)
i = 0;
}
update:
if (refreshed) /* Update hardware tail index */
IXGBE_WRITE_REG(&sc->hw, rxr->tail, rxr->next_to_refresh);
return;
} /* ixgbe_refresh_mbufs */
/************************************************************************
* ixgbe_allocate_receive_buffers
*
* Allocate memory for rx_buffer structures. Since we use one
* rx_buffer per received packet, the maximum number of rx_buffer's
* that we'll need is equal to the number of receive descriptors
* that we've allocated.
************************************************************************/
static int
ixgbe_allocate_receive_buffers(struct rx_ring *rxr)
{
struct ixgbe_softc *sc = rxr->sc;
device_t dev = sc->dev;
struct ixgbe_rx_buf *rxbuf;
int bsize, error;
/* Free current RX buffer structs and their mbufs */
ixgbe_free_receive_ring(rxr);
/* Now replenish the mbufs */
for (int i = 0; i < rxr->num_desc; i++) {
struct mbuf *mp;
rxbuf = &rxr->rx_buffers[i];
#ifdef DEV_NETMAP
/*
* In netmap mode, fill the map and set the buffer
* address in the NIC ring, considering the offset
* between the netmap and NIC rings (see comment in
* ixgbe_setup_transmit_ring() ). No need to allocate
* an mbuf, so end the block with a continue;
*/
if ((sc->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
int sj = netmap_idx_n2k(na->rx_rings[rxr->me], i);
uint64_t paddr;
void *addr;
/************************************************************************
* ixgbe_setup_receive_structures - Initialize all receive rings.
************************************************************************/
int
ixgbe_setup_receive_structures(struct ixgbe_softc *sc)
{
struct rx_ring *rxr = sc->rx_rings;
int j;
INIT_DEBUGOUT("ixgbe_setup_receive_structures");
for (j = 0; j < sc->num_queues; j++, rxr++)
if (ixgbe_setup_receive_ring(rxr))
goto fail;
return (0);
fail:
/*
* Free RX buffers allocated so far, we will only handle
* the rings that completed, the failing case will have
* cleaned up for itself. 'j' failed, so its the terminus.
*/
for (int i = 0; i < j; ++i) {
rxr = &sc->rx_rings[i];
IXGBE_RX_LOCK(rxr);
ixgbe_free_receive_ring(rxr);
IXGBE_RX_UNLOCK(rxr);
}
/*
* ATM LRO is only for IP/TCP packets and TCP checksum of the packet
* should be computed by hardware. Also it should not have VLAN tag in
* ethernet header. In case of IPv6 we do not yet support ext. hdrs.
*/
if (rxr->lro_enabled &&
(ec->ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0 &&
(ptype & IXGBE_RXDADV_PKTTYPE_ETQF) == 0 &&
((ptype & (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)) ==
(IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP) ||
(ptype & (IXGBE_RXDADV_PKTTYPE_IPV6 | IXGBE_RXDADV_PKTTYPE_TCP)) ==
(IXGBE_RXDADV_PKTTYPE_IPV6 | IXGBE_RXDADV_PKTTYPE_TCP)) &&
(m->m_pkthdr.csum_flags & (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) ==
(CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) {
/*
* Send to the stack if:
* - LRO not enabled, or
* - no LRO resources, or
* - lro enqueue fails
*/
if (rxr->lro.lro_cnt != 0)
if (tcp_lro_rx(&rxr->lro, m, 0) == 0)
return;
}
#endif /* LRO */
/*
* With advanced descriptors the writeback clobbers the buffer addrs,
* so its easier to just free the existing mbufs and take the normal
* refresh path to get new buffers and mapping.
*/
if (rbuf->fmp != NULL) {/* Partial chain ? */
bus_dmamap_sync(rxr->ptag->dt_dmat, rbuf->pmap, 0,
rbuf->buf->m_pkthdr.len, BUS_DMASYNC_POSTREAD);
ixgbe_dmamap_unload(rxr->ptag, rbuf->pmap);
m_freem(rbuf->fmp);
rbuf->fmp = NULL;
rbuf->buf = NULL; /* rbuf->buf is part of fmp's chain */
} else if (rbuf->buf) {
bus_dmamap_sync(rxr->ptag->dt_dmat, rbuf->pmap, 0,
rbuf->buf->m_pkthdr.len, BUS_DMASYNC_POSTREAD);
ixgbe_dmamap_unload(rxr->ptag, rbuf->pmap);
m_free(rbuf->buf);
rbuf->buf = NULL;
}
rbuf->flags = 0;
return;
} /* ixgbe_rx_discard */
/************************************************************************
* ixgbe_rxeof
*
* Executes in interrupt context. It replenishes the
* mbufs in the descriptor and sends data which has
* been dma'ed into host memory to upper layer.
*
* Return TRUE for more work, FALSE for all clean.
************************************************************************/
bool
ixgbe_rxeof(struct ix_queue *que)
{
struct ixgbe_softc *sc = que->sc;
struct rx_ring *rxr = que->rxr;
struct ifnet *ifp = sc->ifp;
#ifdef LRO
struct lro_ctrl *lro = &rxr->lro;
#endif /* LRO */
union ixgbe_adv_rx_desc *cur;
struct ixgbe_rx_buf *rbuf, *nbuf;
int i, nextp, processed = 0;
u32 staterr = 0;
u32 loopcount = 0, numdesc;
u32 limit = sc->rx_process_limit;
u32 rx_copy_len = sc->rx_copy_len;
bool discard_multidesc = rxr->discard_multidesc;
bool wraparound = false;
unsigned int syncremain;
#ifdef RSS
u16 pkt_info;
#endif
IXGBE_RX_LOCK(rxr);
#ifdef DEV_NETMAP
if (sc->feat_en & IXGBE_FEATURE_NETMAP) {
/* Same as the txeof routine: wakeup clients on intr. */
if (netmap_rx_irq(ifp, rxr->me, &processed)) {
IXGBE_RX_UNLOCK(rxr);
return (FALSE);
}
}
#endif /* DEV_NETMAP */
/* Sync the ring. The size is rx_process_limit or the first half */
if ((rxr->next_to_check + limit) <= rxr->num_desc) {
/* Non-wraparound */
numdesc = limit;
syncremain = 0;
} else {
/* Wraparound. Sync the first half. */
numdesc = rxr->num_desc - rxr->next_to_check;
/* Set the size of the last half */
syncremain = limit - numdesc;
}
bus_dmamap_sync(rxr->rxdma.dma_tag->dt_dmat,
rxr->rxdma.dma_map,
sizeof(union ixgbe_adv_rx_desc) * rxr->next_to_check,
sizeof(union ixgbe_adv_rx_desc) * numdesc,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
/*
* The max number of loop is rx_process_limit. If discard_multidesc is
* true, continue processing to not to send broken packet to the upper
* layer.
*/
for (i = rxr->next_to_check;
(loopcount < limit) || (discard_multidesc == true);) {
/* Make sure bad packets are discarded */
if (eop && (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) != 0) {
#if __FreeBSD_version >= 1100036
if (sc->feat_en & IXGBE_FEATURE_VF)
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
#endif
IXGBE_EVC_ADD(&rxr->rx_discarded, 1);
ixgbe_rx_discard(rxr, i);
discard_multidesc = false;
goto next_desc;
}
if (__predict_false(discard_multidesc))
discard = true;
else {
/* Pre-alloc new mbuf. */
if ((rbuf->fmp == NULL) &&
eop && (len <= rx_copy_len)) {
/* For short packet. See below. */
sendmp = m_gethdr(M_NOWAIT, MT_DATA);
if (__predict_false(sendmp == NULL)) {
IXGBE_EVC_ADD(&rxr->no_mbuf, 1);
discard = true;
}
} else {
/* For long packet. */
newmp = ixgbe_getcl();
if (__predict_false(newmp == NULL)) {
IXGBE_EVC_ADD(&rxr->no_mbuf, 1);
discard = true;
}
}
}
if (__predict_false(discard)) {
/*
* Descriptor initialization is already done by the
* above code (cur->wb.upper.status_error = 0).
* So, we can reuse current rbuf->buf for new packet.
*
* Rewrite the buffer addr, see comment in
* ixgbe_rx_discard().
*/
cur->read.pkt_addr = rbuf->addr;
m_freem(rbuf->fmp);
rbuf->fmp = NULL;
if (!eop) {
/* Discard the entire packet. */
discard_multidesc = true;
} else
discard_multidesc = false;
goto next_desc;
}
discard_multidesc = false;
/*
* On 82599 which supports a hardware
* LRO (called HW RSC), packets need
* not be fragmented across sequential
* descriptors, rather the next descriptor
* is indicated in bits of the descriptor.
* This also means that we might process
* more than one packet at a time, something
* that has never been true before, it
* required eliminating global chain pointers
* in favor of what we are doing here. -jfv
*/
if (!eop) {
/*
* Figure out the next descriptor
* of this frame.
*/
#ifdef RSC
if (rxr->hw_rsc == TRUE) {
rsc = ixgbe_rsc_count(cur);
rxr->rsc_num += (rsc - 1);
}
if (rsc) { /* Get hardware index */
nextp = ((staterr & IXGBE_RXDADV_NEXTP_MASK) >>
IXGBE_RXDADV_NEXTP_SHIFT);
} else
#endif
{ /* Just sequential */
nextp = i + 1;
if (nextp == sc->num_rx_desc)
nextp = 0;
}
nbuf = &rxr->rx_buffers[nextp];
prefetch(nbuf);
}
/*
* Rather than using the fmp/lmp global pointers
* we now keep the head of a packet chain in the
* buffer struct and pass this along from one
* descriptor to the next, until we get EOP.
*/
/*
* See if there is a stored head
* that determines what we are
*/
if (rbuf->fmp != NULL) {
/* Secondary frag */
sendmp = rbuf->fmp;
/* For sendmp */
sendmp->m_pkthdr.len += mp->m_len;
} else {
/*
* It's the first segment of a multi descriptor
* packet or a single segment which contains a full
* packet.
*/
if (eop && (len <= rx_copy_len)) {
/*
* Optimize. This might be a small packet, may
* be just a TCP ACK. Copy into a new mbuf, and
* Leave the old mbuf+cluster for re-use.
*/
sendmp->m_data += ETHER_ALIGN;
memcpy(mtod(sendmp, void *),
mtod(mp, void *), len);
IXGBE_EVC_ADD(&rxr->rx_copies, 1);
rbuf->flags |= IXGBE_RX_COPY;
} else {
/* For long packet */
/* first desc of a non-ps chain */
sendmp->m_pkthdr.len = sendmp->m_len = len;
}
++processed;
/* Pass the head pointer on */
if (eop == 0) {
nbuf->fmp = sendmp;
sendmp = NULL;
mp->m_next = nbuf->buf;
} else { /* Sending this frame */
m_set_rcvif(sendmp, ifp);
++rxr->packets;
IXGBE_EVC_ADD(&rxr->rx_packets, 1);
/* capture data for AIM */
rxr->bytes += sendmp->m_pkthdr.len;
IXGBE_EVC_ADD(&rxr->rx_bytes, sendmp->m_pkthdr.len);
/* Process vlan info */
if ((rxr->vtag_strip) && (staterr & IXGBE_RXD_STAT_VP))
vtag = le16toh(cur->wb.upper.vlan);
if (vtag) {
vlan_set_tag(sendmp, vtag);
}
if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
ixgbe_rx_checksum(staterr, sendmp, ptype,
&sc->stats.pf);
}
#if 0 /* FreeBSD */
/*
* In case of multiqueue, we have RXCSUM.PCSD bit set
* and never cleared. This means we have RSS hash
* available to be used.
*/
if (sc->num_queues > 1) {
sendmp->m_pkthdr.flowid =
le32toh(cur->wb.lower.hi_dword.rss);
switch (pkt_info & IXGBE_RXDADV_RSSTYPE_MASK) {
case IXGBE_RXDADV_RSSTYPE_IPV4:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_IPV4);
break;
case IXGBE_RXDADV_RSSTYPE_IPV4_TCP:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_TCP_IPV4);
break;
case IXGBE_RXDADV_RSSTYPE_IPV6:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_IPV6);
break;
case IXGBE_RXDADV_RSSTYPE_IPV6_TCP:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_TCP_IPV6);
break;
case IXGBE_RXDADV_RSSTYPE_IPV6_EX:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_IPV6_EX);
break;
case IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_TCP_IPV6_EX);
break;
#if __FreeBSD_version > 1100000
case IXGBE_RXDADV_RSSTYPE_IPV4_UDP:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_UDP_IPV4);
break;
case IXGBE_RXDADV_RSSTYPE_IPV6_UDP:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_UDP_IPV6);
break;
case IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_RSS_UDP_IPV6_EX);
break;
#endif
default:
M_HASHTYPE_SET(sendmp,
M_HASHTYPE_OPAQUE_HASH);
}
} else {
sendmp->m_pkthdr.flowid = que->msix;
M_HASHTYPE_SET(sendmp, M_HASHTYPE_OPAQUE);
}
#endif
}
next_desc:
ixgbe_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
/* Advance our pointers to the next descriptor. */
if (++i == rxr->num_desc) {
wraparound = true;
i = 0;
}
rxr->next_to_check = i;
/* Now send to the stack or do LRO */
if (sendmp != NULL)
ixgbe_rx_input(rxr, ifp, sendmp, ptype);
/* Every 8 descriptors we go to refresh mbufs */
if (processed == 8) {
ixgbe_refresh_mbufs(rxr, i);
processed = 0;
}
}
/* Save the current status */
rxr->discard_multidesc = discard_multidesc;
/* Refresh any remaining buf structs */
if (ixgbe_rx_unrefreshed(rxr))
ixgbe_refresh_mbufs(rxr, i);
IXGBE_RX_UNLOCK(rxr);
#ifdef LRO
/*
* Flush any outstanding LRO work
*/
tcp_lro_flush_all(lro);
#endif /* LRO */
/*
* Still have cleaning to do?
*/
if ((staterr & IXGBE_RXD_STAT_DD) != 0)
return (TRUE);
return (FALSE);
} /* ixgbe_rxeof */
/************************************************************************
* ixgbe_rx_checksum
*
* Verify that the hardware indicated that the checksum is valid.
* Inform the stack about the status of checksum so that stack
* doesn't spend time verifying the checksum.
************************************************************************/
static void
ixgbe_rx_checksum(u32 staterr, struct mbuf * mp, u32 ptype,
struct ixgbe_hw_stats *stats)
{
u16 status = (u16)staterr;
u8 errors = (u8)(staterr >> 24);
#if 0
bool sctp = false;
/************************************************************************
* ixgbe_allocate_queues
*
* Allocate memory for the transmit and receive rings, and then
* the descriptors associated with each, called only once at attach.
************************************************************************/
int
ixgbe_allocate_queues(struct ixgbe_softc *sc)
{
device_t dev = sc->dev;
struct ix_queue *que;
struct tx_ring *txr;
struct rx_ring *rxr;
int rsize, tsize, error = IXGBE_SUCCESS;
int txconf = 0, rxconf = 0;
/* First, allocate the top level queue structs */
sc->queues = kmem_zalloc(sizeof(struct ix_queue) * sc->num_queues,
KM_SLEEP);
/* Second, allocate the TX ring struct memory */
sc->tx_rings = kmem_zalloc(sizeof(struct tx_ring) * sc->num_queues,
KM_SLEEP);
/* Third, allocate the RX ring */
sc->rx_rings = kmem_zalloc(sizeof(struct rx_ring) * sc->num_queues,
KM_SLEEP);
/* For the ring itself */
tsize = sc->num_tx_desc * sizeof(union ixgbe_adv_tx_desc);
KASSERT((tsize % DBA_ALIGN) == 0);
/*
* Now set up the TX queues, txconf is needed to handle the
* possibility that things fail midcourse and we need to
* undo memory gracefully
*/
for (int i = 0; i < sc->num_queues; i++, txconf++) {
/* Set up some basics */
txr = &sc->tx_rings[i];
txr->sc = sc;
txr->txr_interq = NULL;
/* In case SR-IOV is enabled, align the index properly */
#ifdef PCI_IOV
txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool,
i);
#else
txr->me = i;
#endif
txr->num_desc = sc->num_tx_desc;
/* Initialize the TX side lock */
mutex_init(&txr->tx_mtx, MUTEX_DEFAULT, IPL_NET);
/* Allocate receive buffers for the ring */
if (ixgbe_allocate_receive_buffers(rxr)) {
aprint_error_dev(dev,
"Critical Failure setting up receive buffers\n");
error = ENOMEM;
goto err_rx_desc;
}
}
/*
* Finally set up the queue holding structs
*/
for (int i = 0; i < sc->num_queues; i++) {
que = &sc->queues[i];
que->sc = sc;
que->me = i;
que->txr = &sc->tx_rings[i];
que->rxr = &sc->rx_rings[i];
/************************************************************************
* ixgbe_free_queues
*
* Free descriptors for the transmit and receive rings, and then
* the memory associated with each.
************************************************************************/
void
ixgbe_free_queues(struct ixgbe_softc *sc)
{
struct ix_queue *que;
int i;
ixgbe_free_transmit_structures(sc);
ixgbe_free_receive_structures(sc);
for (i = 0; i < sc->num_queues; i++) {
que = &sc->queues[i];
mutex_destroy(&que->dc_mtx);
}
kmem_free(sc->queues, sizeof(struct ix_queue) * sc->num_queues);
} /* ixgbe_free_queues */
