/*
* Copyright (c) 2004 Manuel Bouyer.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* Driver for the IDE part of the AMD Geode CS5530A companion chip
* and AMD Geode SC1100.
* Docs available from AMD's web site
*/
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
/*
* XXXJRT What chip revisions actually need the DMA
* alignment work-around?
*/
sc->sc_wdcdev.dma_init = geodeide_dma_init;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
/*
* The 5530 is utterly swamped by UDMA mode 2, so limit to mode 1
* so that the chip is able to perform the other functions it has
* while IDE UDMA is going on.
*/
if (sc->sc_pp->ide_product == PCI_PRODUCT_CYRIX_CX5530_IDE) {
sc->sc_wdcdev.sc_atac.atac_udma_cap = 1;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.wdc_maxdrives = 2;
/*
* Soekris Engineering Issue #0003:
* "The SC1100 built in busmaster IDE controller is pretty
* standard, but have two bugs: data transfers need to be
* dword aligned and it cannot do an exact 64Kbyte data
* transfer."
*/
if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) {
if (sc->sc_dma_boundary == 0x10000)
sc->sc_dma_boundary -= PAGE_SIZE;
if (sc->sc_dma_maxsegsz == 0x10000)
sc->sc_dma_maxsegsz -= PAGE_SIZE;
}
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
/* controller is compat-only */
if (pciide_chansetup(sc, channel, 0) == 0)
continue;
pciide_mapchan(pa, cp, 0, pciide_pci_intr);
}
}