/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
sc->sc_dma_ok = 1;
/*
* Errata #4 says that if the cacheline length is not set correctly,
* we can get corrupt MWI and Memory-Block-Write transactions.
*/
cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag,
PCI_BHLC_REG));
if (cacheline_len == 0) {
aprint_verbose(", but unused (cacheline size not set in PCI conf)\n");
sc->sc_dma_ok = 0;
return;
}
/*
* Final step of the work-around is to force the DMA engine to use
* the cache-line length information.
*/
dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR);
dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE;
pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl);
if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
PCIIDE_OPTIONS_NODMA) {
aprint_verbose(
", but unused (forced off by config file)\n");
sc->sc_dma_ok = 0;
return;
}
/*
* Set up the default handles for the DMA registers.
* Just reserve 32 bits for each handle, unless space
* doesn't permit it.
*/
for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) {
pc = &sc->pciide_channels[chan];
if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2,
&pc->dma_iohs[IDEDMA_CMD]) != 0 ||
bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1,
&pc->dma_iohs[IDEDMA_CTL]) != 0 ||
bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4,
&pc->dma_iohs[IDEDMA_TBL]) != 0) {
sc->sc_dma_ok = 0;
aprint_verbose(", but can't subregion registers\n");
return;
}
}
/*
* Perform a quick check to ensure that the device isn't configured
* in Spread-spectrum clocking mode. This feature is buggy and has
* been removed from the latest documentation.
*
* Note that although this bit is in the Channel regs, it's the same
* for all channels, so we check it just once here.
*/
if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh,
ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF +
ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"Spread-spectrum clocking not supported by device\n");
return;
}
