/*      $NetBSD: miidevs.h,v 1.172 2024/10/23 05:46:51 skrll Exp $      */

/*
* THIS FILE IS AUTOMATICALLY GENERATED.  DO NOT EDIT.
*
* generated from:
*      NetBSD: miidevs,v 1.174 2024/10/23 05:44:10 skrll Exp
*/

/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/

/*
* List of known MII OUIs.
* For a complete list see http://standards.ieee.org/regauth/oui/
*
* XXX Vendors do obviously not agree how OUIs (24 bit) are mapped
* to the 22 bits available in the id registers.
* IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
* mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
* (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
* about this.)
* The MII_OUI() macro in "miivar.h" reflects this.
* If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
* which is mangled accordingly to compensate.
*/

/*
* Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h
*/

#define MII_OUI_AMD     0x00001a                /* Advanced Micro Devices */
#define MII_OUI_TRIDIUM 0x0001f0                /* Tridium */
#define MII_OUI_DATATRACK       0x0002c6                /* Data Track Technology */
#define MII_OUI_AGERE   0x00053d                /* Agere */
#define MII_OUI_QUAKE   0x000897                /* Quake Technologies */
#define MII_OUI_BANKSPEED       0x0006b8                /* Bankspeed Pty */
#define MII_OUI_NETEXCELL       0x0008bb                /* NetExcell */
#define MII_OUI_NETAS   0x0009c3                /* Netas */
#define MII_OUI_BROADCOM2       0x000af7                /* Broadcom Corporation */
#define MII_OUI_AELUROS 0x000b25                /* Aeluros */
#define MII_OUI_RALINK  0x000c43                /* Ralink Technology */
#define MII_OUI_ASIX    0x000ec6                /* ASIX */
#define MII_OUI_BROADCOM        0x001018                /* Broadcom Corporation */
#define MII_OUI_MICREL  0x0010a1                /* Micrel */
#define MII_OUI_ALTIMA  0x0010a9                /* Altima Communications */
#define MII_OUI_ENABLESEMI      0x0010dd                /* Enable Semiconductor */
#define MII_OUI_SUNPLUS 0x001105                /* Sunplus Technology */
#define MII_OUI_TERANETICS      0x0014a6                /* Teranetics */
#define MII_OUI_RALINK2 0x0017a5                /* Ralink Technology */
#define MII_OUI_AQUANTIA        0x0017b6                /* Aquantia Corporation */
#define MII_OUI_BROADCOM3       0x001be9                /* Broadcom Corporation */
#define MII_OUI_LEVEL1  0x00207b                /* Level 1 */
#define MII_OUI_MARVELL 0x005043                /* Marvell Semiconductor */
#define MII_OUI_QUALSEMI        0x006051                /* Quality Semiconductor */
#define MII_OUI_AMLOGIC 0x006051                /* Amlogic */
#define MII_OUI_DAVICOM 0x00606e                /* Davicom Semiconductor */
#define MII_OUI_SMSC    0x00800f                /* SMSC */
#define MII_OUI_SEEQ    0x00a07d                /* Seeq */
#define MII_OUI_ICS     0x00a0be                /* Integrated Circuit Systems */
#define MII_OUI_INTEL   0x00aa00                /* Intel */
#define MII_OUI_TSC     0x00c039                /* TDK Semiconductor */
#define MII_OUI_MYSON   0x00c0b4                /* Myson Technology */
#define MII_OUI_ATTANSIC        0x00c82e                /* Attansic Technology */
#define MII_OUI_JMICRON 0x00d831                /* JMicron */
#define MII_OUI_PMCSIERRA       0x00e004                /* PMC-Sierra */
#define MII_OUI_SIS     0x00e006                /* Silicon Integrated Systems */
#define MII_OUI_REALTEK 0x00e04c                /* RealTek */
#define MII_OUI_ADMTEK  0x00e092                /* ADMtek */
#define MII_OUI_XAQTI   0x00e0ae                /* XaQti Corp. */
#define MII_OUI_NATSEMI 0x080017                /* National Semiconductor */
#define MII_OUI_TI      0x080028                /* Texas Instruments */
#define MII_OUI_BROADCOM4       0x18c086                /* Broadcom Corporation */
#define MII_OUI_RENESAS 0x749050                /* Renesas */
#define MII_OUI_INTEL2  0x984fee                /* Intel */
#define MII_OUI_MAXLINEAR       0xac9a96                /* MaxLinear */
#define MII_OUI_MOTORCOMM       0xc82b5e                /* Motorcomm */

/* Unregistered or wrong OUI */
#define MII_OUI_yyREALTEK       0x000004                /* Realtek */
#define MII_OUI_yyAMD   0x000058                /* Advanced Micro Devices */
#define MII_OUI_xxVIA   0x0002c6                /* VIA Technologies */
#define MII_OUI_xxMYSON 0x00032d                /* Myson Technology */
#define MII_OUI_xxTSC   0x00039c                /* TDK Semiconductor */
#define MII_OUI_xxASIX  0x000674                /* Asix Semiconductor */
#define MII_OUI_xxDAVICOM       0x000676                /* Davicom Semiconductor */
#define MII_OUI_xxAMLOGIC       0x00068a                /* Amlogic */
#define MII_OUI_xxQUALSEMI      0x00068a                /* Quality Semiconductor */
#define MII_OUI_xxREALTEK       0x000732                /* Realtek */
#define MII_OUI_xxADMTEK        0x000749                /* ADMTek */
#define MII_OUI_xxBROADCOM      0x000818                /* Broadcom Corporation */
#define MII_OUI_xxPMCSIERRA     0x0009c0                /* PMC-Sierra */
#define MII_OUI_xxICPLUS        0x0009c3                /* IC Plus Corp. */
#define MII_OUI_xxMARVELL       0x000ac2                /* Marvell Semiconductor */
#define MII_OUI_xxINTEL 0x001f00                /* Intel */
#define MII_OUI_xxBROADCOM_ALT1 0x0050ef                /* Broadcom Corporation */
#define MII_OUI_yyINTEL 0x005500                /* Intel */
#define MII_OUI_yyASIX  0x007063                /* Asix Semiconductor */
#define MII_OUI_xxVITESSE       0x008083                /* Vitesse Semiconductor */
#define MII_OUI_xxPMCSIERRA2    0x009057                /* PMC-Sierra */
#define MII_OUI_xxCICADA        0x00c08f                /* Cicada Semiconductor */
#define MII_OUI_xxRDC   0x00d02d                /* RDC Semiconductor */
#define MII_OUI_xxMAXLINEAR     0x0c32ab                /* MaxLinear */
#define MII_OUI_xxNATSEMI       0x1000e8                /* National Semiconductor */
#define MII_OUI_xxLEVEL1        0x782000                /* Level 1 */
#define MII_OUI_xxXAQTI 0xace000                /* XaQti Corp. */

/*
* List of known models.  Grouped by oui.
*/

/*
* Agere PHYs
*/
#define MII_MODEL_AGERE_ET1011  0x0001          /* ET1011 10/100/1000baseT PHY */
#define MII_STR_AGERE_ET1011    "ET1011 10/100/1000baseT PHY"
#define MII_MODEL_AGERE_ET1011C 0x0004          /* ET1011C 10/100/1000baseT PHY */
#define MII_STR_AGERE_ET1011C   "ET1011C 10/100/1000baseT PHY"

/* Asix semiconductor PHYs */
#define MII_MODEL_xxASIX_AX88X9X        0x0031          /* Ax88x9x internal PHY */
#define MII_STR_xxASIX_AX88X9X  "Ax88x9x internal PHY"
#define MII_MODEL_yyASIX_AX88772        0x0001          /* AX88772 internal PHY */
#define MII_STR_yyASIX_AX88772  "AX88772 internal PHY"
#define MII_MODEL_yyASIX_AX88772A       0x0006          /* AX88772A internal PHY */
#define MII_STR_yyASIX_AX88772A "AX88772A internal PHY"
#define MII_MODEL_yyASIX_AX88772B       0x0008          /* AX88772B internal PHY */
#define MII_STR_yyASIX_AX88772B "AX88772B internal PHY"

/* Altima Communications PHYs */
/* Don't know the model for ACXXX */
#define MII_MODEL_ALTIMA_ACXXX  0x0001          /* ACXXX 10/100 media interface */
#define MII_STR_ALTIMA_ACXXX    "ACXXX 10/100 media interface"
#define MII_MODEL_ALTIMA_AC101L 0x0012          /* AC101L 10/100 media interface */
#define MII_STR_ALTIMA_AC101L   "AC101L 10/100 media interface"
#define MII_MODEL_ALTIMA_AC101  0x0021          /* AC101 10/100 media interface */
#define MII_STR_ALTIMA_AC101    "AC101 10/100 media interface"
/* AMD Am79C87[45] have ALTIMA OUI */
#define MII_MODEL_ALTIMA_Am79C875       0x0014          /* Am79C875 10/100 media interface */
#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface"
#define MII_MODEL_ALTIMA_Am79C874       0x0021          /* Am79C874 10/100 media interface */
#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface"

/* Amlogic PHYs */
#define MII_MODEL_AMLOGIC_GXL   0x0000          /* Meson GXL internal PHY */
#define MII_STR_AMLOGIC_GXL     "Meson GXL internal PHY"
#define MII_MODEL_xxAMLOGIC_GXL 0x0000          /* Meson GXL internal PHY */
#define MII_STR_xxAMLOGIC_GXL   "Meson GXL internal PHY"

/* Attansic/Atheros PHYs */
#define MII_MODEL_ATTANSIC_L1   0x0001          /* L1 10/100/1000 PHY */
#define MII_STR_ATTANSIC_L1     "L1 10/100/1000 PHY"
#define MII_MODEL_ATTANSIC_L2   0x0002          /* L2 10/100 PHY */
#define MII_STR_ATTANSIC_L2     "L2 10/100 PHY"
#define MII_MODEL_ATTANSIC_AR8021       0x0004          /* Atheros AR8021 10/100/1000 PHY */
#define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY"
#define MII_MODEL_ATTANSIC_AR8035       0x0007          /* Atheros AR8035 10/100/1000 PHY */
#define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY"

/* Advanced Micro Devices PHYs */
/* see Davicom DM9101 for Am79C873 */
#define MII_MODEL_yyAMD_79C972_10T      0x0001          /* Am79C972 internal 10BASE-T interface */
#define MII_STR_yyAMD_79C972_10T        "Am79C972 internal 10BASE-T interface"
#define MII_MODEL_yyAMD_79c973phy       0x0036          /* Am79C973 internal 10/100 media interface */
#define MII_STR_yyAMD_79c973phy "Am79C973 internal 10/100 media interface"
#define MII_MODEL_yyAMD_79c901  0x0037          /* Am79C901 10BASE-T interface */
#define MII_STR_yyAMD_79c901    "Am79C901 10BASE-T interface"
#define MII_MODEL_yyAMD_79c901home      0x0039          /* Am79C901 HomePNA 1.0 interface */
#define MII_STR_yyAMD_79c901home        "Am79C901 HomePNA 1.0 interface"

/* Broadcom Corp. PHYs */
#define MII_MODEL_xxBROADCOM_3C905B     0x0012          /* Broadcom 3c905B internal PHY */
#define MII_STR_xxBROADCOM_3C905B       "Broadcom 3c905B internal PHY"
#define MII_MODEL_xxBROADCOM_3C905C     0x0017          /* Broadcom 3c905C internal PHY */
#define MII_STR_xxBROADCOM_3C905C       "Broadcom 3c905C internal PHY"
#define MII_MODEL_xxBROADCOM_BCM5221    0x001e          /* BCM5221 10/100 media interface */
#define MII_STR_xxBROADCOM_BCM5221      "BCM5221 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5201    0x0021          /* BCM5201 10/100 media interface */
#define MII_STR_xxBROADCOM_BCM5201      "BCM5201 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5214    0x0028          /* BCM5214 Quad 10/100 media interface */
#define MII_STR_xxBROADCOM_BCM5214      "BCM5214 Quad 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5222    0x0032          /* BCM5222 Dual 10/100 media interface */
#define MII_STR_xxBROADCOM_BCM5222      "BCM5222 Dual 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM4401    0x0036          /* BCM4401 10/100 media interface */
#define MII_STR_xxBROADCOM_BCM4401      "BCM4401 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5365    0x0037          /* BCM5365 10/100 5-port PHY switch */
#define MII_STR_xxBROADCOM_BCM5365      "BCM5365 10/100 5-port PHY switch"
#define MII_MODEL_BROADCOM_BCM5400      0x0004          /* BCM5400 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5400        "BCM5400 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5401      0x0005          /* BCM5401 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5401        "BCM5401 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5402      0x0006          /* BCM5402 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5402        "BCM5402 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5411      0x0007          /* BCM5411 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5411        "BCM5411 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5404      0x0008          /* BCM5404 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5404        "BCM5404 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5424      0x000a          /* BCM5424/BCM5234 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5424        "BCM5424/BCM5234 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5464      0x000b          /* BCM5464 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5464        "BCM5464 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5461      0x000c          /* BCM5461 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5461        "BCM5461 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5462      0x000d          /* BCM5462 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5462        "BCM5462 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5421      0x000e          /* BCM5421 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5421        "BCM5421 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5752      0x0010          /* BCM5752 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5752        "BCM5752 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5701      0x0011          /* BCM5701 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5701        "BCM5701 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5706      0x0015          /* BCM5706 1000BASE-T/SX media interface */
#define MII_STR_BROADCOM_BCM5706        "BCM5706 1000BASE-T/SX media interface"
#define MII_MODEL_BROADCOM_BCM5703      0x0016          /* BCM5703 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5703        "BCM5703 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5750      0x0018          /* BCM5750 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5750        "BCM5750 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5704      0x0019          /* BCM5704 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5704        "BCM5704 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5705      0x001a          /* BCM5705 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5705        "BCM5705 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM54K2      0x002e          /* BCM54K2 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM54K2        "BCM54K2 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5714      0x0034          /* BCM5714 1000BASE-T/X media interface */
#define MII_STR_BROADCOM_BCM5714        "BCM5714 1000BASE-T/X media interface"
#define MII_MODEL_BROADCOM_BCM5780      0x0035          /* BCM5780 1000BASE-T/X media interface */
#define MII_STR_BROADCOM_BCM5780        "BCM5780 1000BASE-T/X media interface"
#define MII_MODEL_BROADCOM_BCM5708C     0x0036          /* BCM5708C 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5708C       "BCM5708C 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5466      0x003b          /* BCM5466 1000BASE-T media interface */
#define MII_STR_BROADCOM_BCM5466        "BCM5466 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5325     0x0003          /* BCM5325 10/100 5-port PHY switch */
#define MII_STR_BROADCOM2_BCM5325       "BCM5325 10/100 5-port PHY switch"
#define MII_MODEL_BROADCOM2_BCM5906     0x0004          /* BCM5906 10/100baseTX media interface */
#define MII_STR_BROADCOM2_BCM5906       "BCM5906 10/100baseTX media interface"
#define MII_MODEL_BROADCOM2_BCM5478     0x0008          /* BCM5478 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5478       "BCM5478 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5488     0x0009          /* BCM5488 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5488       "BCM5488 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5481     0x000a          /* BCM5481 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5481       "BCM5481 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5482     0x000b          /* BCM5482 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5482       "BCM5482 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5755     0x000c          /* BCM5755 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5755       "BCM5755 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5756     0x000d          /* BCM5756 1000BASE-T media interface XXX */
#define MII_STR_BROADCOM2_BCM5756       "BCM5756 1000BASE-T media interface XXX"
#define MII_MODEL_BROADCOM2_BCM5754     0x000e          /* BCM5754/5787 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5754       "BCM5754/5787 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5708S    0x0015          /* BCM5708S 1000/2500baseSX PHY */
#define MII_STR_BROADCOM2_BCM5708S      "BCM5708S 1000/2500baseSX PHY"
#define MII_MODEL_BROADCOM2_BCM5785     0x0016          /* BCM5785 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5785       "BCM5785 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5709CAX  0x002c          /* BCM5709CAX 10/100/1000baseT PHY */
#define MII_STR_BROADCOM2_BCM5709CAX    "BCM5709CAX 10/100/1000baseT PHY"
#define MII_MODEL_BROADCOM2_BCM5722     0x002d          /* BCM5722 1000BASE-T media interface */
#define MII_STR_BROADCOM2_BCM5722       "BCM5722 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5784     0x003a          /* BCM5784 10/100/1000baseT PHY */
#define MII_STR_BROADCOM2_BCM5784       "BCM5784 10/100/1000baseT PHY"
#define MII_MODEL_BROADCOM2_BCM5709C    0x003c          /* BCM5709 10/100/1000baseT PHY */
#define MII_STR_BROADCOM2_BCM5709C      "BCM5709 10/100/1000baseT PHY"
#define MII_MODEL_BROADCOM2_BCM5761     0x003d          /* BCM5761 10/100/1000baseT PHY */
#define MII_STR_BROADCOM2_BCM5761       "BCM5761 10/100/1000baseT PHY"
#define MII_MODEL_BROADCOM2_BCM5709S    0x003f          /* BCM5709S 1000/2500baseSX PHY */
#define MII_STR_BROADCOM2_BCM5709S      "BCM5709S 1000/2500baseSX PHY"
#define MII_MODEL_BROADCOM3_BCM57780    0x0019          /* BCM57780 1000BASE-T media interface */
#define MII_STR_BROADCOM3_BCM57780      "BCM57780 1000BASE-T media interface"
#define MII_MODEL_BROADCOM3_BCM5717C    0x0020          /* BCM5717C 1000BASE-T media interface */
#define MII_STR_BROADCOM3_BCM5717C      "BCM5717C 1000BASE-T media interface"
#define MII_MODEL_BROADCOM3_BCM5719C    0x0022          /* BCM5719C 1000BASE-T media interface */
#define MII_STR_BROADCOM3_BCM5719C      "BCM5719C 1000BASE-T media interface"
#define MII_MODEL_BROADCOM3_BCM57765    0x0024          /* BCM57765 1000BASE-T media interface */
#define MII_STR_BROADCOM3_BCM57765      "BCM57765 1000BASE-T media interface"
#define MII_MODEL_BROADCOM3_BCM53125    0x0032          /* BCM53125 1000BASE-T switch */
#define MII_STR_BROADCOM3_BCM53125      "BCM53125 1000BASE-T switch"
#define MII_MODEL_BROADCOM3_BCM5720C    0x0036          /* BCM5720C 1000BASE-T media interface */
#define MII_STR_BROADCOM3_BCM5720C      "BCM5720C 1000BASE-T media interface"
#define MII_MODEL_BROADCOM4_BCM54213PE  0x000a          /* BCM54213PE 1000BASE-T media interface */
#define MII_STR_BROADCOM4_BCM54213PE    "BCM54213PE 1000BASE-T media interface"
#define MII_MODEL_BROADCOM4_BCM5725C    0x0038          /* BCM5725C 1000BASE-T media interface */
#define MII_STR_BROADCOM4_BCM5725C      "BCM5725C 1000BASE-T media interface"
#define MII_MODEL_xxBROADCOM_ALT1_BCM5906       0x0004          /* BCM5906 10/100baseTX media interface */
#define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface"

/* Cicada Semiconductor PHYs (-> Vitesse -> Microsemi) */

#define MII_MODEL_xxCICADA_CIS8201      0x0001          /* Cicada CIS8201 10/100/1000TX PHY */
#define MII_STR_xxCICADA_CIS8201        "Cicada CIS8201 10/100/1000TX PHY"
#define MII_MODEL_xxCICADA_CIS8204      0x0004          /* Cicada CIS8204 10/100/1000TX PHY */
#define MII_STR_xxCICADA_CIS8204        "Cicada CIS8204 10/100/1000TX PHY"
#define MII_MODEL_xxCICADA_VSC8211      0x000b          /* Cicada VSC8211 10/100/1000TX PHY */
#define MII_STR_xxCICADA_VSC8211        "Cicada VSC8211 10/100/1000TX PHY"
#define MII_MODEL_xxCICADA_VSC8221      0x0015          /* Vitesse VSC8221 10/100/1000BASE-T PHY */
#define MII_STR_xxCICADA_VSC8221        "Vitesse VSC8221 10/100/1000BASE-T PHY"
#define MII_MODEL_xxCICADA_VSC8224      0x0018          /* Vitesse VSC8224 10/100/1000BASE-T PHY */
#define MII_STR_xxCICADA_VSC8224        "Vitesse VSC8224 10/100/1000BASE-T PHY"
#define MII_MODEL_xxCICADA_CIS8201A     0x0020          /* Cicada CIS8201 10/100/1000TX PHY */
#define MII_STR_xxCICADA_CIS8201A       "Cicada CIS8201 10/100/1000TX PHY"
#define MII_MODEL_xxCICADA_CIS8201B     0x0021          /* Cicada CIS8201 10/100/1000TX PHY */
#define MII_STR_xxCICADA_CIS8201B       "Cicada CIS8201 10/100/1000TX PHY"
#define MII_MODEL_xxCICADA_VSC8234      0x0022          /* Vitesse VSC8234 10/100/1000TX PHY */
#define MII_STR_xxCICADA_VSC8234        "Vitesse VSC8234 10/100/1000TX PHY"
#define MII_MODEL_xxCICADA_VSC8244      0x002c          /* Vitesse VSC8244 Quad 10/100/1000BASE-T PHY */
#define MII_STR_xxCICADA_VSC8244        "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY"

/* Davicom Semiconductor PHYs */
/* AMD Am79C873 seems to be a relabeled DM9101 */
#define MII_MODEL_DAVICOM_DM9101        0x0000          /* DM9101 (AMD Am79C873) 10/100 media interface */
#define MII_STR_DAVICOM_DM9101  "DM9101 (AMD Am79C873) 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9101      0x0000          /* DM9101 (AMD Am79C873) 10/100 media interface */
#define MII_STR_xxDAVICOM_DM9101        "DM9101 (AMD Am79C873) 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9102      0x0004          /* DM9102 10/100 media interface */
#define MII_STR_xxDAVICOM_DM9102        "DM9102 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9161      0x0008          /* DM9161 10/100 media interface */
#define MII_STR_xxDAVICOM_DM9161        "DM9161 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9161A     0x000a          /* DM9161A 10/100 media interface */
#define MII_STR_xxDAVICOM_DM9161A       "DM9161A 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9161B     0x000b          /* DM9161[BC] 10/100 media interface */
#define MII_STR_xxDAVICOM_DM9161B       "DM9161[BC] 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9601      0x000c          /* DM9601 internal 10/100 media interface */
#define MII_STR_xxDAVICOM_DM9601        "DM9601 internal 10/100 media interface"

/* IC Plus Corp. PHYs */
#define MII_MODEL_xxICPLUS_IP100        0x0004          /* IP100 10/100 PHY */
#define MII_STR_xxICPLUS_IP100  "IP100 10/100 PHY"
#define MII_MODEL_xxICPLUS_IP101        0x0005          /* IP101 10/100 PHY */
#define MII_STR_xxICPLUS_IP101  "IP101 10/100 PHY"
#define MII_MODEL_xxICPLUS_IP1000A      0x0008          /* IP1000A 10/100/1000 PHY */
#define MII_STR_xxICPLUS_IP1000A        "IP1000A 10/100/1000 PHY"
#define MII_MODEL_xxICPLUS_IP1001       0x0019          /* IP1001 10/100/1000 PHY */
#define MII_STR_xxICPLUS_IP1001 "IP1001 10/100/1000 PHY"

/* Integrated Circuit Systems PHYs */
#define MII_MODEL_ICS_1889      0x0001          /* ICS1889 10/100 media interface */
#define MII_STR_ICS_1889        "ICS1889 10/100 media interface"
#define MII_MODEL_ICS_1890      0x0002          /* ICS1890 10/100 media interface */
#define MII_STR_ICS_1890        "ICS1890 10/100 media interface"
#define MII_MODEL_ICS_1892      0x0003          /* ICS1892 10/100 media interface */
#define MII_STR_ICS_1892        "ICS1892 10/100 media interface"
#define MII_MODEL_ICS_1893      0x0004          /* ICS1893 10/100 media interface */
#define MII_STR_ICS_1893        "ICS1893 10/100 media interface"
#define MII_MODEL_ICS_1893C     0x0005          /* ICS1893C 10/100 media interface */
#define MII_STR_ICS_1893C       "ICS1893C 10/100 media interface"

/* Intel PHYs */
#define MII_MODEL_xxINTEL_I82553        0x0000          /* i82553 10/100 media interface */
#define MII_STR_xxINTEL_I82553  "i82553 10/100 media interface"
#define MII_MODEL_yyINTEL_I82555        0x0015          /* i82555 10/100 media interface */
#define MII_STR_yyINTEL_I82555  "i82555 10/100 media interface"
#define MII_MODEL_yyINTEL_I82562EH      0x0017          /* i82562EH HomePNA interface */
#define MII_STR_yyINTEL_I82562EH        "i82562EH HomePNA interface"
#define MII_MODEL_yyINTEL_I82562G       0x0031          /* i82562G 10/100 media interface */
#define MII_STR_yyINTEL_I82562G "i82562G 10/100 media interface"
#define MII_MODEL_yyINTEL_I82562EM      0x0032          /* i82562EM 10/100 media interface */
#define MII_STR_yyINTEL_I82562EM        "i82562EM 10/100 media interface"
#define MII_MODEL_yyINTEL_I82562ET      0x0033          /* i82562ET 10/100 media interface */
#define MII_STR_yyINTEL_I82562ET        "i82562ET 10/100 media interface"
#define MII_MODEL_yyINTEL_I82553        0x0035          /* i82553 10/100 media interface */
#define MII_STR_yyINTEL_I82553  "i82553 10/100 media interface"
#define MII_MODEL_yyINTEL_IGP01E1000    0x0038          /* Intel IGP01E1000 Gigabit PHY */
#define MII_STR_yyINTEL_IGP01E1000      "Intel IGP01E1000 Gigabit PHY"
#define MII_MODEL_yyINTEL_I82566        0x0039          /* i82566 10/100/1000 media interface */
#define MII_STR_yyINTEL_I82566  "i82566 10/100/1000 media interface"
#define MII_MODEL_INTEL_I82577  0x0005          /* i82577 10/100/1000 media interface */
#define MII_STR_INTEL_I82577    "i82577 10/100/1000 media interface"
#define MII_MODEL_INTEL_I82579  0x0009          /* i82579 10/100/1000 media interface */
#define MII_STR_INTEL_I82579    "i82579 10/100/1000 media interface"
#define MII_MODEL_INTEL_I217    0x000a          /* i217 10/100/1000 media interface */
#define MII_STR_INTEL_I217      "i217 10/100/1000 media interface"
#define MII_MODEL_INTEL_X540    0x0020          /* X540 100M/1G/10G media interface */
#define MII_STR_INTEL_X540      "X540 100M/1G/10G media interface"
#define MII_MODEL_INTEL_X550    0x0022          /* X550 100M/1G/10G media interface */
#define MII_STR_INTEL_X550      "X550 100M/1G/10G media interface"
#define MII_MODEL_INTEL_X557    0x0024          /* X557 100M/1G/10G media interface */
#define MII_STR_INTEL_X557      "X557 100M/1G/10G media interface"
#define MII_MODEL_INTEL_I82580  0x003a          /* 82580 10/100/1000 media interface */
#define MII_STR_INTEL_I82580    "82580 10/100/1000 media interface"
#define MII_MODEL_INTEL_I350    0x003b          /* I350 10/100/1000 media interface */
#define MII_STR_INTEL_I350      "I350 10/100/1000 media interface"
#define MII_MODEL_xxMARVELL_I210        0x0000          /* I210 10/100/1000 media interface */
#define MII_STR_xxMARVELL_I210  "I210 10/100/1000 media interface"
#define MII_MODEL_xxMARVELL_I82563      0x000a          /* i82563 10/100/1000 media interface */
#define MII_STR_xxMARVELL_I82563        "i82563 10/100/1000 media interface"
#define MII_MODEL_ATTANSIC_I82578       0x0004          /* Intel 82578 10/100/1000 media interface */
#define MII_STR_ATTANSIC_I82578 "Intel 82578 10/100/1000 media interface"
/* Acquired by MaxLinear */
#define MII_MODEL_INTEL2_GPY211 0x0000          /* MaxLinear GPY21[125] 2.5G PHY */
#define MII_STR_INTEL2_GPY211   "MaxLinear GPY21[125] 2.5G PHY"
#define MII_MODEL_INTEL2_I226_1 0x0001          /* I226 2.5G media interface (1) */
#define MII_STR_INTEL2_I226_1   "I226 2.5G media interface (1)"
#define MII_MODEL_INTEL2_I226_2 0x0005          /* I226 2.5G media interface (2) */
#define MII_STR_INTEL2_I226_2   "I226 2.5G media interface (2)"
#define MII_MODEL_INTEL2_I225   0x000c          /* I225 2.5G media interface */
#define MII_STR_INTEL2_I225     "I225 2.5G media interface"
#define MII_MODEL_INTEL2_GPY211_2       0x0020          /* MaxLinear GPY21[12] 2.5G PHY (2) */
#define MII_STR_INTEL2_GPY211_2 "MaxLinear GPY21[12] 2.5G PHY (2)"
#define MII_MODEL_INTEL2_GPY211_3       0x0021          /* MaxLinear GPY211 2.5G PHY (3) */
#define MII_STR_INTEL2_GPY211_3 "MaxLinear GPY211 2.5G PHY (3)"
#define MII_MODEL_INTEL2_GPY212 0x0022          /* MaxLinear GPY212 2.5G PHY */
#define MII_STR_INTEL2_GPY212   "MaxLinear GPY212 2.5G PHY"
#define MII_MODEL_INTEL2_GPY115 0x0030          /* MaxLinear GPY115 Gigabit PHY */
#define MII_STR_INTEL2_GPY115   "MaxLinear GPY115 Gigabit PHY"
#define MII_MODEL_INTEL2_GPY215 0x0032          /* MaxLinear GPY215 2.5G PHY */
#define MII_STR_INTEL2_GPY215   "MaxLinear GPY215 2.5G PHY"

/* JMicron PHYs */
#define MII_MODEL_JMICRON_JMP211        0x0021          /* JMP211 10/100/1000 media interface */
#define MII_STR_JMICRON_JMP211  "JMP211 10/100/1000 media interface"
#define MII_MODEL_JMICRON_JMP202        0x0022          /* JMP202 10/100 media interface */
#define MII_STR_JMICRON_JMP202  "JMP202 10/100 media interface"

/* Level 1 PHYs */
#define MII_MODEL_xxLEVEL1_LXT970       0x0000          /* LXT970 10/100 media interface */
#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
#define MII_MODEL_LEVEL1_LXT1000_OLD    0x0003          /* LXT1000 1000BASE-T media interface */
#define MII_STR_LEVEL1_LXT1000_OLD      "LXT1000 1000BASE-T media interface"
#define MII_MODEL_LEVEL1_LXT974 0x0004          /* LXT974 10/100 Quad PHY */
#define MII_STR_LEVEL1_LXT974   "LXT974 10/100 Quad PHY"
#define MII_MODEL_LEVEL1_LXT975 0x0005          /* LXT975 10/100 Quad PHY */
#define MII_STR_LEVEL1_LXT975   "LXT975 10/100 Quad PHY"
#define MII_MODEL_LEVEL1_LXT1000        0x000c          /* LXT1000 1000BASE-T media interface */
#define MII_STR_LEVEL1_LXT1000  "LXT1000 1000BASE-T media interface"
#define MII_MODEL_LEVEL1_LXT971 0x000e          /* LXT971/2 10/100 media interface */
#define MII_STR_LEVEL1_LXT971   "LXT971/2 10/100 media interface"
#define MII_MODEL_LEVEL1_LXT973 0x0021          /* LXT973 10/100 Dual PHY */
#define MII_STR_LEVEL1_LXT973   "LXT973 10/100 Dual PHY"

/* Marvell Semiconductor PHYs */
#define MII_MODEL_xxMARVELL_E1000       0x0000          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1011       0x0002          /* Marvell 88E1011 Gigabit PHY */
#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1000_3     0x0003          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_xxMARVELL_E1000_3       "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1000S      0x0004          /* Marvell 88E1000S Gigabit PHY */
#define MII_STR_xxMARVELL_E1000S        "Marvell 88E1000S Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1000_5     0x0005          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_xxMARVELL_E1000_5       "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1101       0x0006          /* Marvell 88E1101 Gigabit PHY */
#define MII_STR_xxMARVELL_E1101 "Marvell 88E1101 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E3082       0x0008          /* Marvell 88E3082 10/100 Fast Ethernet PHY */
#define MII_STR_xxMARVELL_E3082 "Marvell 88E3082 10/100 Fast Ethernet PHY"
#define MII_MODEL_xxMARVELL_E1112       0x0009          /* Marvell 88E1112 Gigabit PHY */
#define MII_STR_xxMARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1149       0x000b          /* Marvell 88E1149 Gigabit PHY */
#define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1111       0x000c          /* Marvell 88E1111 Gigabit PHY */
#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1145       0x000d          /* Marvell 88E1145 Quad Gigabit PHY */
#define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY"
#define MII_MODEL_xxMARVELL_E6060       0x0010          /* Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch */
#define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch"
#define MII_MODEL_xxMARVELL_I347        0x001c          /* Intel I347-AT4 Gigabit PHY */
#define MII_STR_xxMARVELL_I347  "Intel I347-AT4 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1512       0x001d          /* Marvell 88E151[0248] Gigabit PHY */
#define MII_STR_xxMARVELL_E1512 "Marvell 88E151[0248] Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1340M      0x001f          /* Marvell 88E1340 Gigabit PHY */
#define MII_STR_xxMARVELL_E1340M        "Marvell 88E1340 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1116       0x0021          /* Marvell 88E1116 Gigabit PHY */
#define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1118       0x0022          /* Marvell 88E1118 Gigabit PHY */
#define MII_STR_xxMARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1240       0x0023          /* Marvell 88E1240 Gigabit PHY */
#define MII_STR_xxMARVELL_E1240 "Marvell 88E1240 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1116R      0x0024          /* Marvell 88E1116R Gigabit PHY */
#define MII_STR_xxMARVELL_E1116R        "Marvell 88E1116R Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1149R      0x0025          /* Marvell 88E1149R Quad Gigabit PHY */
#define MII_STR_xxMARVELL_E1149R        "Marvell 88E1149R Quad Gigabit PHY"
#define MII_MODEL_xxMARVELL_E3016       0x0026          /* Marvell 88E3016 10/100 Fast Ethernet PHY */
#define MII_STR_xxMARVELL_E3016 "Marvell 88E3016 10/100 Fast Ethernet PHY"
#define MII_MODEL_xxMARVELL_PHYG65G     0x0027          /* Marvell PHYG65G Gigabit PHY */
#define MII_STR_xxMARVELL_PHYG65G       "Marvell PHYG65G Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1318S      0x0029          /* Marvell 88E1318S Gigabit PHY */
#define MII_STR_xxMARVELL_E1318S        "Marvell 88E1318S Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1543       0x002a          /* Marvell 88E154[358] Alaska Quad Port Gb PHY */
#define MII_STR_xxMARVELL_E1543 "Marvell 88E154[358] Alaska Quad Port Gb PHY"
#define MII_MODEL_MARVELL_E1000_0       0x0000          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_MARVELL_E1000_0 "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_MARVELL_E1011 0x0002          /* Marvell 88E1011 Gigabit PHY */
#define MII_STR_MARVELL_E1011   "Marvell 88E1011 Gigabit PHY"
#define MII_MODEL_MARVELL_E1000_3       0x0003          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_MARVELL_E1000_5       0x0005          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_MARVELL_E1000_6       0x0006          /* Marvell 88E1000 Gigabit PHY */
#define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY"
#define MII_MODEL_MARVELL_E1111 0x000c          /* Marvell 88E1111 Gigabit PHY */
#define MII_STR_MARVELL_E1111   "Marvell 88E1111 Gigabit PHY"

/* Micrel PHYs (Kendin and Microchip) */
#define MII_MODEL_MICREL_KSZ8041        0x0011          /* Micrel KSZ8041TL/FTL/MLL 10/100 PHY */
#define MII_STR_MICREL_KSZ8041  "Micrel KSZ8041TL/FTL/MLL 10/100 PHY"
#define MII_MODEL_MICREL_KSZ8041RNLI    0x0013          /* Micrel KSZ8041RNLI 10/100 PHY */
#define MII_STR_MICREL_KSZ8041RNLI      "Micrel KSZ8041RNLI 10/100 PHY"
#define MII_MODEL_MICREL_KSZ8051        0x0015          /* Micrel KSZ80[235]1 10/100 PHY */
#define MII_STR_MICREL_KSZ8051  "Micrel KSZ80[235]1 10/100 PHY"
#define MII_MODEL_MICREL_KSZ8081        0x0016          /* Micrel KSZ80[89]1 10/100 PHY */
#define MII_STR_MICREL_KSZ8081  "Micrel KSZ80[89]1 10/100 PHY"
#define MII_MODEL_MICREL_KSZ8061        0x0017          /* Micrel KSZ8061 10/100 PHY */
#define MII_STR_MICREL_KSZ8061  "Micrel KSZ8061 10/100 PHY"
#define MII_MODEL_MICREL_KSZ9021_8001_8721      0x0021          /* Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY */
#define MII_STR_MICREL_KSZ9021_8001_8721        "Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY"
#define MII_MODEL_MICREL_KSZ9031        0x0022          /* Micrel KSZ9031 10/100/1000 PHY */
#define MII_STR_MICREL_KSZ9031  "Micrel KSZ9031 10/100/1000 PHY"
#define MII_MODEL_MICREL_KSZ9477        0x0023          /* Micrel KSZ9477 10/100/1000 PHY */
#define MII_STR_MICREL_KSZ9477  "Micrel KSZ9477 10/100/1000 PHY"
#define MII_MODEL_MICREL_KSZ9131        0x0024          /* Micrel KSZ9131 10/100/1000 PHY */
#define MII_STR_MICREL_KSZ9131  "Micrel KSZ9131 10/100/1000 PHY"
#define MII_MODEL_MICREL_KS8737 0x0032          /* Micrel KS8737 10/100 PHY */
#define MII_STR_MICREL_KS8737   "Micrel KS8737 10/100 PHY"

/* Motorcomm */
#define MII_MODEL_MOTORCOMM_YT8531      0x0011          /* Motorcomm YT8531 Gigabit PHY */
#define MII_STR_MOTORCOMM_YT8531        "Motorcomm YT8531 Gigabit PHY"

/* Myson Technology PHYs */
#define MII_MODEL_xxMYSON_MTD972        0x0000          /* MTD972 10/100 media interface */
#define MII_STR_xxMYSON_MTD972  "MTD972 10/100 media interface"
#define MII_MODEL_MYSON_MTD803  0x0000          /* MTD803 3-in-1 media interface */
#define MII_STR_MYSON_MTD803    "MTD803 3-in-1 media interface"

/* National Semiconductor PHYs */
#define MII_MODEL_xxNATSEMI_DP83840     0x0000          /* DP83840 10/100 media interface */
#define MII_STR_xxNATSEMI_DP83840       "DP83840 10/100 media interface"
#define MII_MODEL_xxNATSEMI_DP83843     0x0001          /* DP83843 10/100 media interface */
#define MII_STR_xxNATSEMI_DP83843       "DP83843 10/100 media interface"
#define MII_MODEL_xxNATSEMI_DP83815     0x0002          /* DP83815/DP83846A 10/100 media interface */
#define MII_STR_xxNATSEMI_DP83815       "DP83815/DP83846A 10/100 media interface"
#define MII_MODEL_xxNATSEMI_DP83847     0x0003          /* DP83847 10/100 media interface */
#define MII_STR_xxNATSEMI_DP83847       "DP83847 10/100 media interface"
#define MII_MODEL_xxNATSEMI_DP83891     0x0005          /* DP83891 1000BASE-T media interface */
#define MII_STR_xxNATSEMI_DP83891       "DP83891 1000BASE-T media interface"
#define MII_MODEL_xxNATSEMI_DP83861     0x0006          /* DP83861 1000BASE-T media interface */
#define MII_STR_xxNATSEMI_DP83861       "DP83861 1000BASE-T media interface"
#define MII_MODEL_xxNATSEMI_DP83865     0x0007          /* DP83865 1000BASE-T media interface */
#define MII_STR_xxNATSEMI_DP83865       "DP83865 1000BASE-T media interface"
#define MII_MODEL_xxNATSEMI_DP83849     0x000a          /* DP83849 10/100 media interface */
#define MII_STR_xxNATSEMI_DP83849       "DP83849 10/100 media interface"

/* PMC Sierra PHYs */
#define MII_MODEL_xxPMCSIERRA_PM8351    0x0000          /* PM8351 OctalPHY Gigabit interface */
#define MII_STR_xxPMCSIERRA_PM8351      "PM8351 OctalPHY Gigabit interface"
#define MII_MODEL_xxPMCSIERRA2_PM8352   0x0002          /* PM8352 OctalPHY Gigabit interface */
#define MII_STR_xxPMCSIERRA2_PM8352     "PM8352 OctalPHY Gigabit interface"
#define MII_MODEL_xxPMCSIERRA2_PM8353   0x0003          /* PM8353 QuadPHY Gigabit interface */
#define MII_STR_xxPMCSIERRA2_PM8353     "PM8353 QuadPHY Gigabit interface"
#define MII_MODEL_PMCSIERRA_PM8354      0x0004          /* PM8354 QuadPHY Gigabit interface */
#define MII_STR_PMCSIERRA_PM8354        "PM8354 QuadPHY Gigabit interface"

/* Quality Semiconductor PHYs */
#define MII_MODEL_xxQUALSEMI_QS6612     0x0000          /* QS6612 10/100 media interface */
#define MII_STR_xxQUALSEMI_QS6612       "QS6612 10/100 media interface"

/* RDC Semiconductor PHYs */
#define MII_MODEL_xxRDC_R6040   0x0003          /* R6040 10/100 media interface */
#define MII_STR_xxRDC_R6040     "R6040 10/100 media interface"
#define MII_MODEL_xxRDC_R6040_2 0x0005          /* R6040 10/100 media interface */
#define MII_STR_xxRDC_R6040_2   "R6040 10/100 media interface"
#define MII_MODEL_xxRDC_R6040_3 0x0006          /* R6040 10/100 media interface */
#define MII_STR_xxRDC_R6040_3   "R6040 10/100 media interface"

/* RealTek PHYs */
#define MII_MODEL_xxREALTEK_RTL8169S    0x0011          /* RTL8169S/8110S/8211 1000BASE-T media interface */
#define MII_STR_xxREALTEK_RTL8169S      "RTL8169S/8110S/8211 1000BASE-T media interface"
#define MII_MODEL_yyREALTEK_RTL8201L    0x0020          /* RTL8201L 10/100 media interface */
#define MII_STR_yyREALTEK_RTL8201L      "RTL8201L 10/100 media interface"
#define MII_MODEL_REALTEK_RTL8251       0x0000          /* RTL8251 1000BASE-T media interface */
#define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface"
#define MII_MODEL_REALTEK_RTL8201E      0x0008          /* RTL8201E 10/100 media interface */
#define MII_STR_REALTEK_RTL8201E        "RTL8201E 10/100 media interface"
#define MII_MODEL_REALTEK_RTL8169S      0x0011          /* RTL8169S/8110S/8211 1000BASE-T media interface */
#define MII_STR_REALTEK_RTL8169S        "RTL8169S/8110S/8211 1000BASE-T media interface"

/* Seeq PHYs */
#define MII_MODEL_SEEQ_80220    0x0003          /* Seeq 80220 10/100 media interface */
#define MII_STR_SEEQ_80220      "Seeq 80220 10/100 media interface"
#define MII_MODEL_SEEQ_84220    0x0004          /* Seeq 84220 10/100 media interface */
#define MII_STR_SEEQ_84220      "Seeq 84220 10/100 media interface"
#define MII_MODEL_SEEQ_80225    0x0008          /* Seeq 80225 10/100 media interface */
#define MII_STR_SEEQ_80225      "Seeq 80225 10/100 media interface"

/* Silicon Integrated Systems PHYs */
#define MII_MODEL_SIS_900       0x0000          /* SiS 900 10/100 media interface */
#define MII_STR_SIS_900 "SiS 900 10/100 media interface"

/* SMSC PHYs */
#define MII_MODEL_SMSC_LAN83C185        0x000a          /* SMSC LAN83C185 10/100 PHY */
#define MII_STR_SMSC_LAN83C185  "SMSC LAN83C185 10/100 PHY"
#define MII_MODEL_SMSC_LAN8700  0x000c          /* SMSC LAN8700 10/100 Ethernet Transceiver */
#define MII_STR_SMSC_LAN8700    "SMSC LAN8700 10/100 Ethernet Transceiver"
#define MII_MODEL_SMSC_LAN911X  0x000d          /* SMSC LAN911X internal 10/100 PHY */
#define MII_STR_SMSC_LAN911X    "SMSC LAN911X internal 10/100 PHY"
#define MII_MODEL_SMSC_LAN75XX  0x000e          /* SMSC LAN75XX internal 10/100 PHY */
#define MII_STR_SMSC_LAN75XX    "SMSC LAN75XX internal 10/100 PHY"
#define MII_MODEL_SMSC_LAN8710_LAN8720  0x000f          /* SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver */
#define MII_STR_SMSC_LAN8710_LAN8720    "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver"
#define MII_MODEL_SMSC_LAN8740  0x0011          /* SMSC LAN8740 10/100 media interface */
#define MII_STR_SMSC_LAN8740    "SMSC LAN8740 10/100 media interface"
#define MII_MODEL_SMSC_LAN8741A 0x0012          /* SMSC LAN8741A 10/100 media interface */
#define MII_STR_SMSC_LAN8741A   "SMSC LAN8741A 10/100 media interface"
#define MII_MODEL_SMSC_LAN8742  0x0013          /* SMSC LAN8742 10/100 media interface */
#define MII_STR_SMSC_LAN8742    "SMSC LAN8742 10/100 media interface"

/* Teranetics PHY */
#define MII_MODEL_TERANETICS_TN1010     0x0001          /* Teranetics TN1010 10GBase-T PHY */
#define MII_STR_TERANETICS_TN1010       "Teranetics TN1010 10GBase-T PHY"

/* Texas Instruments PHYs */
#define MII_MODEL_TI_TLAN10T    0x0001          /* ThunderLAN 10BASE-T media interface */
#define MII_STR_TI_TLAN10T      "ThunderLAN 10BASE-T media interface"
#define MII_MODEL_TI_100VGPMI   0x0002          /* ThunderLAN 100VG-AnyLan media interface */
#define MII_STR_TI_100VGPMI     "ThunderLAN 100VG-AnyLan media interface"
#define MII_MODEL_TI_TNETE2101  0x0003          /* TNETE2101 media interface */
#define MII_STR_TI_TNETE2101    "TNETE2101 media interface"

/* TDK Semiconductor PHYs */
#define MII_MODEL_xxTSC_78Q2120 0x0014          /* 78Q2120 10/100 media interface */
#define MII_STR_xxTSC_78Q2120   "78Q2120 10/100 media interface"
#define MII_MODEL_xxTSC_78Q2121 0x0015          /* 78Q2121 100BASE-TX media interface */
#define MII_STR_xxTSC_78Q2121   "78Q2121 100BASE-TX media interface"

/* VIA Technologies PHYs */
#define MII_MODEL_xxVIA_VT6103  0x0032          /* VT6103 10/100 PHY */
#define MII_STR_xxVIA_VT6103    "VT6103 10/100 PHY"
#define MII_MODEL_xxVIA_VT6103_2        0x0034          /* VT6103 10/100 PHY */
#define MII_STR_xxVIA_VT6103_2  "VT6103 10/100 PHY"

/* Vitesse PHYs (Now Microsemi) */
#define MII_MODEL_xxVITESSE_VSC8601     0x0002          /* VSC8601 10/100/1000 PHY */
#define MII_STR_xxVITESSE_VSC8601       "VSC8601 10/100/1000 PHY"
#define MII_MODEL_xxVITESSE_VSC8641     0x0003          /* Vitesse VSC8641 10/100/1000TX PHY */
#define MII_STR_xxVITESSE_VSC8641       "Vitesse VSC8641 10/100/1000TX PHY"
#define MII_MODEL_xxVITESSE_VSC8504     0x000c          /* Vitesse VSC8504 quad 10/100/1000TX PHY */
#define MII_STR_xxVITESSE_VSC8504       "Vitesse VSC8504 quad 10/100/1000TX PHY"
#define MII_MODEL_xxVITESSE_VSC8552     0x000e          /* Vitesse VSC8552 dual 10/100/1000TX PHY */
#define MII_STR_xxVITESSE_VSC8552       "Vitesse VSC8552 dual 10/100/1000TX PHY"
#define MII_MODEL_xxVITESSE_VSC8502     0x0012          /* Vitesse VSC8502 dual 10/100/1000TX PHY */
#define MII_STR_xxVITESSE_VSC8502       "Vitesse VSC8502 dual 10/100/1000TX PHY"
#define MII_MODEL_xxVITESSE_VSC8501     0x0013          /* Vitesse VSC8501 10/100/1000TX PHY */
#define MII_STR_xxVITESSE_VSC8501       "Vitesse VSC8501 10/100/1000TX PHY"
#define MII_MODEL_xxVITESSE_VSC8531     0x0017          /* Vitesse VSC8531 10/100/1000TX PHY */
#define MII_STR_xxVITESSE_VSC8531       "Vitesse VSC8531 10/100/1000TX PHY"
#define MII_MODEL_xxVITESSE_VSC8662     0x0026          /* Vitesse VSC866[24] dual/quad 1000T 100FX 1000X PHY */
#define MII_STR_xxVITESSE_VSC8662       "Vitesse VSC866[24] dual/quad 1000T 100FX 1000X PHY"
#define MII_MODEL_xxVITESSE_VSC8514     0x0027          /* Vitesse VSC8514 quad 1000T PHY */
#define MII_STR_xxVITESSE_VSC8514       "Vitesse VSC8514 quad 1000T PHY"
#define MII_MODEL_xxVITESSE_VSC8512     0x002e          /* Vitesse VSC8512 12port 1000T PHY */
#define MII_STR_xxVITESSE_VSC8512       "Vitesse VSC8512 12port 1000T PHY"
#define MII_MODEL_xxVITESSE_VSC8522     0x002f          /* Vitesse VSC8522 12port 1000T PHY */
#define MII_STR_xxVITESSE_VSC8522       "Vitesse VSC8522 12port 1000T PHY"
#define MII_MODEL_xxVITESSE_VSC8658     0x0035          /* Vitesse VSC8658 octal 1000T 100FX 1000X PHY */
#define MII_STR_xxVITESSE_VSC8658       "Vitesse VSC8658 octal 1000T 100FX 1000X PHY"
#define MII_MODEL_xxVITESSE_VSC8541     0x0037          /* Vitesse VSC8541 1000T PHY */
#define MII_STR_xxVITESSE_VSC8541       "Vitesse VSC8541 1000T PHY"

/* XaQti Corp. PHYs */
#define MII_MODEL_xxXAQTI_XMACII        0x0000          /* XaQti Corp. XMAC II gigabit interface */
#define MII_STR_xxXAQTI_XMACII  "XaQti Corp. XMAC II gigabit interface"

/* Define format strings for non-existent values */
#define mii_id1_format  "oui %6.6x"
#define mii_id2_format  "model %4.4x"

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