/* $NetBSD: ikphyreg.h,v 1.4 2019/12/11 07:33:55 msaitoh Exp $ */
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/*
* Copied from the Intel code, and then modified to match NetBSD
* style for MII registers more.
*/
#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alternate Page Select */
#define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) /* MAC Specific Control Register */
/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
#define GG82563_MSCR_TX_CLK_MASK 0x0007
#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
#define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Specific Control 2 */