/*******************************************************************************
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Developed by Semihalf

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*******************************************************************************/

#ifndef _MVSPIREG_H_
#define _MVSPIREG_H_

#define         MVSPI_SIZE                      0x80            /* Size of MVSPI */

/* Definition of registers */
#define         MVSPI_CTRL_REG                  0x00            /* MVSPI Control Register */
#define         MVSPI_INTCONF_REG               0x04            /* MVSPI Interface Configuration Register */
#define         MVSPI_DATAOUT_REG               0x08            /* MVSPI Data Out Register */
#define         MVSPI_DATAIN_REG                0x0C            /* MVSPI Data In Register */
#define         MVSPI_IRQCAUSE_REG              0x10            /* MVSPI Interrupt Cause Register */
#define         MVSPI_IRQMASK_REG               0x14            /* MVSPI Interrupt Mask Register */
#define         MVSPI_TIMEPAR1_REG              0x18            /* MVSPI Timing Parameters 1 Register*/
#define         MVSPI_TIMEPAR2_REG              0x1C            /* MVSPI Timing Parameters 2 Register */
#define         MVSPI_DIRWRITE_REG              0x20            /* MVSPI Direct Write Configuration Register*/
#define         MVSPI_DIRWRITEHD_REG            0x24            /* MVSPI Direct Write Header Register */
#define         MVSPI_DIRREADHD_REG             0x28            /* MVSPI Direct Read Header Register */
#define         MVSPI_CSADRDEC_REG              0x2C            /* MVSPI CS Address Decode Register */
#define         MVSPI_CSnTIMPAR_REG             0x30            /* MVSPI CSn Timing Parameters Register */
#define         MVSPI_CNTVER_REG                0x50            /* MVSPI Controller Version Register */

/* Masks */
#define         MVSPI_CPOL_MASK                 0x0800          /* CPOL bit = 1 */
#define         MVSPI_CPHA_MASK                 0x1000          /* CPHA bit = 1 */
#define         MVSPI_DIRHS_MASK                0xFBFF          /* SPI Direct Read High Speed Transaction Mask */
#define         MVSPI_1BYTE_MASK                0xFFDF          /* Number of bits in each I/O transfer Mask */
#define         MVSPI_SPR_MASK                  0x0007          /* SPR field mask */
#define         MVSPI_SPPR_MASK                 0x00D0          /* SPPR field mask */
#define         MVSPI_SPPRHI_MASK               0x00C0          /* SPPR_HI field mask */
#define         MVSPI_SPPR0_MASK                0x0010          /* SPPR0 field mask */
#define         MVSPI_CSNACT_MASK               0x0001          /* CSn transfer acknowledge bit */

#define         MVSPI_CR_SMEMRDY                0x0002          /* MVSPI Control Register Serial Memory Data Transfer Ready */

#define         MVSPI_DUMMY_BYTE                0xFF            /* Dummy byte */

#define         MVSPI_WAIT_RDY_MAX_LOOP         100000          /* Transfer timeout threshold */
#define         MVSPI_SPR_MAXVALUE              15              /* Maximum value for SPR coeficient */
#define         MVSPI_SPPR_MAXVALUE             7               /* Maximum value for SPPR coeficient */

#endif          /* _MVSPIREG_H_ */