/*-
* Copyright (c) 2019, 2020 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Nuvoton NCT5104D
*
* - GPIO: full support.
* - Watchdog: no support. Watchdog uses GPIO pins.
* - UARTS: handled by com driver. 3rd & 4th UARTs use GPIO pins.
*
* If asked to probe with a wildcard address, we'll only do so if known to
* be running on a PC Engines system. Probe is invasive.
*
* Register access on Super I/O chips typically involves one or two levels
* of indirection, so we try hard to avoid needless register access.
*/
/* Access to the remaining members is covered by sc_lock. */
kmutex_t sc_lock; /* Serialization */
int sc_curdev; /* Cur. logical dev */
int sc_curreg; /* Cur. register */
struct nct_bank sc_bank[3]; /* Bank descriptions */
};
/*
* Set up register space and basics of our state.
*/
if (bus_space_map(ia->ia_iot, ia->ia_io[0].ir_addr,
ia->ia_io[0].ir_size, 0, &sc->sc_ioh) != 0) {
aprint_normal(": can't map i/o space\n");
return;
}
aprint_normal(": Nuvoton NCT5104D GPIO\n");
sc->sc_dev = self;
sc->sc_iot = ia->ia_iot;
sc->sc_curdev = -1;
sc->sc_curreg = -1;
/*
* All pin access is funneled through a common, indirect register
* interface. The gpio framework doesn't serialize calls to our
* access methods, so do it internally. This is likely such a
* common requirement that it should be factored out as is done for
* audio devices, allowing the driver to specify the appropriate
* locks. Anyhow, acquire the lock immediately to pacify locking
* assertions.
*/
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
mutex_spin_enter(&sc->sc_lock);
/*
* Fill pin descriptions and initialize registers.
*/
memset(sc->sc_pins, 0, sizeof(sc->sc_pins));
for (i = 0; i < __arraycount(sc->sc_bank); i++) {
nb = &sc->sc_bank[i];
mutex_spin_enter(&sc->sc_lock);
nb->nb_val_dir = nct_rd(sc, nb->nb_reg_dir);
nb->nb_val_inv = nct_rd(sc, nb->nb_reg_inv);
nb->nb_val_mode = nct_rd(sc, nb->nb_reg_mode);
mutex_spin_exit(&sc->sc_lock);
for (j = 0; j < nb->nb_numpins; j++) {
gpio_pin_t *pin = &sc->sc_pins[nb->nb_firstpin + j];
pin->pin_num = nb->nb_firstpin + j;
/* Skip pin if not configured as GPIO. */
if ((nb->nb_enabled & (1 << j)) == 0) {
continue;
}
pin->pin_caps =
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
GPIO_PIN_OPENDRAIN |
GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE |
GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
pin->pin_flags =
GPIO_PIN_INPUT | GPIO_PIN_OPENDRAIN;
nct_gpio_ctl(sc, pin->pin_num, pin->pin_flags);
pin->pin_state = nct_gpio_read(sc, pin->pin_num);
}
}
/*
* Attach to gpio framework, and attach all pins unconditionally.
* If the pins are disabled, we'll ignore any access later.
*/
sc->sc_gc.gp_cookie = sc;
sc->sc_gc.gp_pin_read = nct_gpio_read;
sc->sc_gc.gp_pin_write = nct_gpio_write;
sc->sc_gc.gp_pin_ctl = nct_gpio_ctl;
/*
* Given pin number, return bank and pin mask. This alters no state and so
* can safely be called without the mutex held.
*/
static struct nct_bank *
nct_sel(struct nct_softc *sc, int pin, u_int8_t *mask)
{
struct nct_bank *nb;
nb = nct_sel(sc, pin, &mask);
if (__predict_false(mask == 0)) {
return;
}
/*
* Set input direction early to avoid perturbation.
*/
mutex_spin_enter(&sc->sc_lock);
data = nb->nb_val_dir;
if ((flg & (GPIO_PIN_INPUT | GPIO_PIN_TRISTATE)) != 0) {
data |= mask;
}
if (data != nb->nb_val_dir) {
nct_wr(sc, nb->nb_reg_dir, data);
nb->nb_val_dir = data;
}
/*
* Set inversion.
*/
data = nb->nb_val_inv;
if ((flg & (GPIO_PIN_OUTPUT | GPIO_PIN_INVOUT)) ==
(GPIO_PIN_OUTPUT | GPIO_PIN_INVOUT) ||
(flg & (GPIO_PIN_INPUT | GPIO_PIN_INVIN)) ==
(GPIO_PIN_INPUT | GPIO_PIN_INVIN)) {
data |= mask;
} else {
data &= ~mask;
}
if (data != nb->nb_val_inv) {
nct_wr(sc, nb->nb_reg_inv, data);
nb->nb_val_inv = data;
}
/*
* Set drain mode.
*/
data = nb->nb_val_mode;
if ((flg & GPIO_PIN_PUSHPULL) != 0) {
data |= mask;
} else /* GPIO_PIN_OPENDRAIN */ {
data &= ~mask;
}
if (data != nb->nb_val_mode) {
nct_wr(sc, nb->nb_reg_mode, data);
nb->nb_val_mode = data;
}
/*
* Set output direction late to avoid perturbation.
*/
data = nb->nb_val_dir;
if ((flg & (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE)) == GPIO_PIN_OUTPUT) {
data &= ~mask;
}
if (data != nb->nb_val_dir) {
nct_wr(sc, nb->nb_reg_dir, data);
nb->nb_val_dir = data;
}
mutex_spin_exit(&sc->sc_lock);
}
