/*-
* Copyright (c) 2008 Hauke Fath
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Zilog Z8536 CIO (Counter/Timer and Parallel I/O Unit)
* Register Definitions
*
* The CIO has four registers: One control register, and three data
* registers for ports A/B/C. To set up the CIO through the control
* register, first write the number of the internal register to it,
* then access or set the selected register contents. Once selected,
* an internal register can be polled continuously by reading out the
* control port.
*
* Internal registers are read-writable, except where noted.
*/
#define Z8536_IOSIZE 0x04
#define Z8536_MICR 0x00 /* Master Interrupt Control Register */
#define MICR_RESET 0x01 /* Chip Reset */
#define MICR_RJA 0x02 /* Only z8036 (ZBUS version) */
#define MICR_CTVIS 0x04 /* CT vector includes status */
#define MICR_PBVIS 0x08 /* Port B vector includes status */
#define MICR_PAVIS 0x10 /* Port A vector includes status */
#define MICR_NV 0x20 /* No Vector (NV) */
#define MICR_DLC 0x40 /* Disable Lower Chain (DLC) */
#define MICR_MIE 0x80 /* Master Interrupt Enable (MIE) */
/* Interrupt Vector Registers */
#define Z8536_IVRA 0x02 /* Port A Interrupt Vector */
#define Z8536_IVRB 0x03 /* Port B Interrupt Vector */
#define Z8536_IVRCT 0x04 /* Counter/Timer Interrupt Vector */
/* Port C setup */
#define Z8536_DPPRC 0x05 /* Port C Data Path Polarity */
#define Z8536_DDRC 0x06 /* Port C Data Direction */
#define Z8536_SIOCRC 0x07 /* Port C Special I/O Control */
#define Z8536_PCSRA 0x08 /* Port A Command and Status */
#define Z8536_PCSRB 0x09 /* Port B Command and Status */
/* Z8536_PCSRA + Z8536_PCSRB command and status bits */
#define PCSR_IOE 0x01 /* Interrupt on error */
#define PCSR_PMF 0x02 /* Pattern match flag (RO) */
#define PCSR_IRF 0x04 /* Input register full (RO) */
#define PCSR_ORE 0x08 /* Output register empty (RO) */
#define PCSR_ERR 0x10 /* Interrupt error */
#define PCSR_IP 0x20 /* Interrupt pending */
#define PCSR_IE 0x40 /* Interrupt enable */
#define PCSR_IUS 0x80 /* Interrupt under service */
/* PCSR{A,B} interrupt bits: IUS/IE/IP */
#define PCSR_NULL 0x00 /* Null Code */
#define PCSR_CLR_IP_IUS 0x20 /* Clear IP and IUS */
#define PCSR_SET_IUS 0x40 /* Set Interrupt Under Service */
#define PCSR_CLR_IUS 0x60 /* Clear Interrupt Under Service */
#define PCSR_SET_IP 0x80 /* Set Interrupt Pending */
#define PCSR_CLR_IP 0xA0 /* Clear Interrupt Pending */
#define PCSR_SET_IE 0xC0 /* Set Interrupt Enable */
#define PCSR_CLR_IE 0xE0 /* Clear Interrupt Enable */
/* Counter/Timer 1..3 Command and Status Registers */
#define Z8536_CTCSR1 0x0A /* CT 1 Command and Status */
#define Z8536_CTCSR2 0x0B /* CT 2 Command and Status */
#define Z8536_CTCSR3 0x0C /* CT 3 Command and Status */
/* The port data registers are directly accessible at their own IO address */
#define Z8536_PDRA 0x0D /* Port A Data Register */
#define Z8536_PDRB 0x0E /* Port B Data Register */
#define Z8536_PDRC 0x0F /* Port C Data Register */
/* Bytewise access to current count registers (read-only) */
#define Z8536_CTCCR1_MSB 0x10 /* CT 1 Current Count MSB */
#define Z8536_CTCCR1_LSB 0x11 /* CT 1 Current Count LSB */
#define Z8536_CTCCR2_MSB 0x12 /* CT 2 Current Count MSB */
#define Z8536_CTCCR2_LSB 0x13 /* CT 2 Current Count LSB */
#define Z8536_CTCCR3_MSB 0x14 /* CT 3 Current Count MSB */
#define Z8536_CTCCR3_LSB 0x15 /* CT 3 Current Count LSB */
/* Bytewise access to time constant registers */
#define Z8536_CTTCR1_MSB 0x16 /* CT 1 Time Constant MSB */
#define Z8536_CTTCR1_LSB 0x17 /* CT 1 Time Constant LSB */
#define Z8536_CTTCR2_MSB 0x18 /* CT 2 Time Constant MSB */
#define Z8536_CTTCR2_LSB 0x19 /* CT 2 Time Constant LSB */
#define Z8536_CTTCR3_MSB 0x1A /* CT 3 Time Constant MSB */
#define Z8536_CTTCR3_LSB 0x1B /* CT 3 Time Constant LSB */
#define Z8536_CVR 0x1F /* Current Interrupt Vector (RO) */
/* Port A specification registers */
#define Z8536_PMSRA 0x20 /* Port A Mode Specification */
#define Z8536_PHSRA 0x21 /* Port A Handshake Specification */
#define Z8536_DPPRA 0x22 /* Port A Data Path Polarity */
#define Z8536_DDRA 0x23 /* Port A Data Direction */
#define Z8536_SIOCRA 0x24 /* Port A Special I/O Control */
#define Z8536_PPRA 0x25 /* Port A Pattern Polarity */
#define Z8536_PTRA 0x26 /* Port A Pattern Transition */
#define Z8536_PMRA 0x27 /* Port A Pattern Mask */
/* Port B specification registers */
#define Z8536_PMSRB 0x28 /* Port B Mode Specification */
#define Z8536_PHSRB 0x29 /* Port B Handshake Specification */
#define Z8536_DPPRB 0x2A /* Port B Data Path Polarity */
#define Z8536_DDRB 0x2B /* Port B Data Direction */
#define Z8536_SIOCRB 0x2C /* Port B Special I/O Control */
#define Z8536_PPRB 0x2D /* Port B Pattern Polarity */
#define Z8536_PTRB 0x2E /* Port B Pattern Transition */
#define Z8536_PMRB 0x2F /* Port B Pattern Mask */
