/*
* Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#define WDCDELAY 100 /* 100 microseconds */
#define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
#if 0
/* If you enable this, it will report any delays more than WDCDELAY * N long. */
#define WDCNDELAY_DEBUG 50
#endif
/* When polling wait that much and then kpause for 1/hz seconds */
#define WDCDELAY_POLL 1 /* ms */
/* timeout for the control commands */
#define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */
/*
* timeout when waiting for BSY to deassert when probing.
* set to 5s. From the standards this could be up to 31, but we can't
* wait that much at boot time, and 5s seems to be enough.
*/
#define WDC_PROBE_WAIT 5
#if NSATA > 0
/*
* probe drives on SATA controllers with standard SATA registers:
* bring the PHYs online, read the drive signature and set drive flags
* appropriately.
*/
void
wdc_sataprobe(struct ata_channel *chp)
{
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
uint8_t st = 0, sc __unused, sn __unused, cl, ch;
int i;
/* reset the PHY and bring online */
switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control,
wdr->sata_status, AT_WAIT)) {
case SStatus_DET_DEV:
/* wait 5s for BSY to clear */
for (i = 0; i < WDC_PROBE_WAIT * hz; i++) {
bus_space_write_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
delay(10); /* 400ns delay */
st = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_status], 0);
if ((st & WDCS_BSY) == 0)
break;
ata_delay(chp, 1, "sataprb", AT_WAIT);
}
if (i == WDC_PROBE_WAIT * hz)
aprint_error_dev(chp->ch_atac->atac_dev,
"BSY never cleared, status 0x%02x\n", st);
sc = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_seccnt], 0);
sn = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_sector], 0);
cl = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_cyl_lo], 0);
ch = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_cyl_hi], 0);
ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x "
"cl=0x%x ch=0x%x\n",
device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
sc, sn, cl, ch), DEBUG_PROBE);
if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) {
ata_channel_unlock(chp);
return;
}
/*
* sc and sn are supposed to be 0x1 for ATAPI, but in some
* cases we get wrong values here, so ignore it.
*/
if (cl == 0x14 && ch == 0xeb)
chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI;
else
chp->ch_drive[0].drive_type = ATA_DRIVET_ATA;
/*
* issue a reset in case only the interface part of the drive
* is up
*/
if (wdcreset(chp, RESET_SLEEP) != 0)
chp->ch_drive[0].drive_type = ATA_DRIVET_NONE;
break;
default:
break;
}
ata_channel_unlock(chp);
}
#endif /* NSATA > 0 */
/* Test to see controller with at last one attached drive is there.
* Returns a bit for each possible drive found (0x01 for drive 0,
* 0x02 for drive 1).
* Logic:
* - If a status register is at 0xff, assume there is no drive here
* (ISA has pull-up resistors). Similarly if the status register has
* the value we last wrote to the bus (for IDE interfaces without pullups).
* If no drive at all -> return.
* - reset the controller, wait for it to complete (may take up to 31s !).
* If timeout -> return.
* - test ATA/ATAPI signatures. If at last one drive found -> return.
* - try an ATA command on the master.
*/
/* Wait a bit, some devices are weird just after a reset. */
delay(5000);
for (i = 0; i < chp->ch_ndrives; i++) {
#if NATA_DMA
/*
* Init error counter so that an error within the first xfers
* will trigger a downgrade
*/
chp->ch_drive[i].n_dmaerrs = NERRS_MAX - 1;
#endif
/* If controller can't do 16bit flag the drives as 32bit */
if ((atac->atac_cap &
(ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) {
ata_channel_lock(chp);
chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32;
ata_channel_unlock(chp);
}
if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE)
continue;
/* Shortcut in case we've been shutdown */
if (chp->ch_flags & ATACH_SHUTDOWN)
return;
/*
* Issue an identify, to try to detect ghosts.
* Note that we can't use interrupts here, because if there
* is no devices, we will get a command aborted without
* interrupts.
*/
error = ata_get_params(&chp->ch_drive[i],
AT_WAIT | AT_POLL, ¶ms);
if (error != CMD_OK) {
ata_channel_lock(chp);
ata_delay(chp, 1000, "atacnf", AT_WAIT);
ata_channel_unlock(chp);
/* Shortcut in case we've been shutdown */
if (chp->ch_flags & ATACH_SHUTDOWN)
return;
#if 0 /* XXX this break some ATA or ATAPI devices */
/*
* reset bus. Also send an ATAPI_RESET to devices, in case there are
* ATAPI device out there which don't react to the bus reset
*/
if (ret_value & 0x01) {
if (wdc->select)
wdc->select(chp,0);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
0, WDSD_IBM);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0,
ATAPI_SOFT_RESET);
}
if (ret_value & 0x02) {
if (wdc->select)
wdc->select(chp,0);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
0, WDSD_IBM | 0x10);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0,
ATAPI_SOFT_RESET);
}
/* if reset failed, there's nothing here */
if (ret_value == 0) {
return 0;
}
/*
* Test presence of drives. First test register signatures looking
* for ATAPI devices. If it's not an ATAPI and reset said there may
* be something here assume it's ATA or OLD. Ghost will be killed
* later in attach routine.
*/
for (drive = 0; drive < wdc->wdc_maxdrives; drive++) {
if ((ret_value & (0x01 << drive)) == 0)
continue;
if (wdc->select)
wdc->select(chp,drive);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
WDSD_IBM | (drive << 4));
delay(10); /* 400ns delay */
/* Save registers contents */
sc = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_seccnt], 0);
sn = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_sector], 0);
cl = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_cyl_lo], 0);
ch = bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_cyl_hi], 0);
ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
"cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc,
sn, cl, ch), DEBUG_PROBE);
/*
* sc & sn are supposed to be 0x1 for ATAPI but in some cases
* we get wrong values here, so ignore it.
*/
if (chp->ch_drive != NULL) {
if (cl == 0x14 && ch == 0xeb) {
chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI;
} else {
chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA;
}
}
}
/*
* Select an existing drive before lowering spl, some WDC_NO_IDS
* devices incorrectly assert IRQ on nonexistent slave
*/
if (ret_value & 0x01) {
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
WDSD_IBM);
(void)bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_status], 0);
}
return (ret_value);
}
for (i = 0; i < atac->atac_nchannels; i++) {
chp = atac->atac_channels[i];
if (child == chp->atabus) {
chp->atabus = NULL;
return;
}
}
}
int
wdcdetach(device_t self, int flags)
{
struct atac_softc *atac = device_private(self);
struct ata_channel *chp;
struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
int i, error = 0;
for (i = 0; i < atac->atac_nchannels; i++) {
chp = atac->atac_channels[i];
if (chp->atabus == NULL)
continue;
ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n",
device_xname(atac->atac_dev), device_xname(chp->atabus)),
DEBUG_DETACH);
if ((error = config_detach(chp->atabus, flags)) != 0)
return error;
ata_channel_detach(chp);
}
if (adapt->adapt_refcnt != 0)
return EBUSY;
return 0;
}
/* restart an interrupted I/O */
void
wdcrestart(void *v)
{
struct ata_channel *chp = v;
int s;
s = splbio();
atastart(chp);
splx(s);
}
/*
* Interrupt routine for the controller. Acknowledge the interrupt, check for
* errors on the current operation, mark it done if necessary, and start the
* next request. Also check for a partially done transfer, and continue with
* the next chunk if so.
*/
int
wdcintr(void *arg)
{
struct ata_channel *chp = arg;
struct atac_softc *atac = chp->ch_atac;
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
struct ata_xfer *xfer;
int ret;
if (!device_is_active(atac->atac_dev)) {
ATADEBUG_PRINT(("wdcintr: deactivated controller\n"),
DEBUG_INTR);
return (0);
}
if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0)
goto ignore;
xfer = ata_queue_get_active_xfer(chp);
if (xfer == NULL) {
ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
ignore:
/* try to clear the pending interrupt anyway */
(void)bus_space_read_1(wdr->cmd_iot,
wdr->cmd_iohs[wd_status], 0);
return (0);
}
/*
* On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit
* actually has no effect, and interrupt is triggered regardless.
* Ignore polled commands here, they are processed separately.
*/
if (ISSET(xfer->c_flags, C_POLL)) {
ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__),
DEBUG_INTR);
goto ignore;
}
#if NATA_DMA || NATA_PIOBM
if (chp->ch_flags & ATACH_DMA_WAIT) {
wdc->dma_status =
(*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel,
xfer->c_drive, WDC_DMAEND_END);
if (wdc->dma_status & WDC_DMAST_NOIRQ) {
/* IRQ not for us, not detected by DMA engine */
return 0;
}
chp->ch_flags &= ~ATACH_DMA_WAIT;
}
#endif
chp->ch_flags &= ~ATACH_IRQ_WAIT;
KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL);
ret = xfer->ops->c_intr(chp, xfer, 1);
if (ret == 0) /* irq was not for us, still waiting for irq */
chp->ch_flags |= ATACH_IRQ_WAIT;
return (ret);
}
/* Put all disk in RESET state */
void
wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp)
{
struct ata_channel *chp = drvp->chnl_softc;
ata_channel_lock_owned(chp);
KASSERT(sigp == NULL);
ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n",
device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
drvp->drive), DEBUG_FUNCS);
/* reset the channel */
if (flags & AT_WAIT)
(void) wdcreset(chp, RESET_SLEEP);
else
(void) wdcreset(chp, RESET_POLL);
/*
* wait a bit after reset; in case the DMA engines needs some time
* to recover.
*/
ata_delay(chp, 1000, "atardl", flags);
/*
* Look for pending xfers. If we have a shared queue, we'll also reset
* the other channel if the current xfer is running on it.
* Then we'll kill the eventual active transfer explicitly, so that
* it is queued for retry immediately without waiting for I/O timeout.
*/
if (xfer) {
if (xfer->c_chp != chp) {
ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET,
ATACH_NODRIVE);
} else {
#if NATA_DMA || NATA_PIOBM
/*
* If we're waiting for DMA, stop the
* DMA engine
*/
if (chp->ch_flags & ATACH_DMA_WAIT) {
(*wdc->dma_finish)(wdc->dma_arg,
chp->ch_channel, xfer->c_drive,
WDC_DMAEND_ABRT_QUIET);
chp->ch_flags &= ~ATACH_DMA_WAIT;
}
#endif
}
}
ata_kill_active(chp, KILL_RESET, flags);
}
static int
wdcreset(struct ata_channel *chp, int poll)
{
struct atac_softc *atac = chp->ch_atac;
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
int drv_mask1, drv_mask2;
/*
* Wait for a drive to be !BSY, and have mask in its status register.
* return -1 for a timeout after "timeout" ms.
*/
static int
__wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd)
{
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
u_char status, error = 0;
int xtime = 0;
int rv;
/*
* Call __wdcwait(), polling using kpause() or waking up the kernel
* thread if possible
*/
int
wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags,
int *tfd)
{
int error, i, timeout_hz = mstohz(timeout);
ata_channel_lock_owned(chp);
if (timeout_hz == 0 ||
(flags & (AT_WAIT | AT_POLL)) == AT_POLL)
error = __wdcwait(chp, mask, bits, timeout, tfd);
else {
error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd);
if (error != 0) {
if (ata_is_thread_run(chp) || (flags & AT_WAIT)) {
/*
* we're running in the channel thread
* or some userland thread context
*/
for (i = 0; i < timeout_hz; i++) {
if (__wdcwait(chp, mask, bits,
WDCDELAY_POLL, tfd) == 0) {
error = 0;
break;
}
kpause("atapoll", true, 1,
&chp->ch_lock);
}
} else {
/*
* we're probably in interrupt context,
* caller must ask the thread to come back here
*/
return(WDCWAIT_THR);
}
}
}
return (error);
}
#if NATA_DMA
/*
* Busy-wait for DMA to complete
*/
int
wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout)
{
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
int xtime;
for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) {
wdc->dma_status =
(*wdc->dma_finish)(wdc->dma_arg,
chp->ch_channel, xfer->c_drive, WDC_DMAEND_END);
if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0)
return 0;
delay(WDCDELAY);
}
/* timeout, force a DMA halt */
wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg,
chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT);
return 1;
}
#endif
/*
* Polled command. Wait for drive ready or drq. Done in intr().
* Wait for at last 400ns for status bit to be valid.
*/
delay(10); /* 400ns delay */
return ATASTART_POLL;
}
static int
__wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
{
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
struct ata_command *ata_c = &xfer->c_ata_c;
int bcount = ata_c->bcount;
char *data = ata_c->data;
int wflags, tfd;
int drive_flags;
if (ata_c->r_command == WDCC_IDENTIFY ||
ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
/*
* The IDENTIFY data has been designed as an array of
* u_int16_t, so we can byteswap it on the fly.
* Historically it's what we have always done so keeping it
* here ensure binary backward compatibility.
*/
drive_flags = ATA_DRIVE_NOSTREAM |
chp->ch_drive[xfer->c_drive].drive_flags;
} else {
/*
* Other data structure are opaque and should be transferred
* as is.
*/
drive_flags = chp->ch_drive[xfer->c_drive].drive_flags;
}
#ifdef WDC_NO_IDS
wflags = AT_POLL;
#else
if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) {
/* both wait and poll, we can kpause here */
wflags = AT_WAIT | AT_POLL;
} else {
wflags = AT_POLL;
}
#endif
ata_channel_lock(chp);
again:
ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
xfer->c_drive), DEBUG_INTR);
/*
* after a ATAPI_SOFT_RESET, the device will have released the bus.
* Reselect again, it doesn't hurt for others commands, and the time
* penalty for the extra register write is acceptable,
* wdc_exec_command() isn't called often (mostly for autoconfig)
*/
if ((xfer->c_flags & C_ATAPI) != 0) {
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
WDSD_IBM | (xfer->c_drive << 4));
}
if ((ata_c->flags & AT_XFDONE) != 0) {
/*
* We have completed a data xfer. The drive should now be
* in its initial state
*/
if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0,
wflags, &tfd) == WDCWAIT_TOUT) {
if (irq && (xfer->c_flags & C_TIMEOU) == 0) {
ata_channel_unlock(chp);
return 0; /* IRQ was not for us */
}
ata_c->flags |= AT_TIMEOU;
}
goto out;
}
if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask,
(irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) {
if (irq && (xfer->c_flags & C_TIMEOU) == 0) {
ata_channel_unlock(chp);
return 0; /* IRQ was not for us */
}
ata_c->flags |= AT_TIMEOU;
goto out;
}
if (wdc->irqack)
wdc->irqack(chp);
if (ata_c->flags & AT_READ) {
if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) {
ata_c->flags |= AT_TIMEOU;
goto out;
}
wdc->datain_pio(chp, drive_flags, data, bcount);
/* at this point the drive should be in its initial state */
ata_c->flags |= AT_XFDONE;
/*
* XXX checking the status register again here cause some
* hardware to timeout.
*/
} else if (ata_c->flags & AT_WRITE) {
if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) {
ata_c->flags |= AT_TIMEOU;
goto out;
}
wdc->dataout_pio(chp, drive_flags, data, bcount);
ata_c->flags |= AT_XFDONE;
if ((ata_c->flags & AT_POLL) == 0) {
chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
callout_reset(&chp->c_timo_callout,
mstohz(ata_c->timeout), wdctimeout, chp);
ata_channel_unlock(chp);
return 1;
} else {
goto again;
}
}
out:
if (ATACH_ST(tfd) & WDCS_DWF)
ata_c->flags |= AT_DF;
if (ATACH_ST(tfd) & WDCS_ERR) {
ata_c->flags |= AT_ERROR;
ata_c->r_error = ATACH_ST(tfd);
}
out:
if (ata_c->flags & AT_POLL) {
/* enable interrupts */
if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
wd_aux_ctlr, WDCTL_4BIT);
delay(10); /* some drives need a little delay here */
}
/*
* Simplified version of wdccommand(). Unbusy/ready/drq must be
* tested by the caller.
*/
void
wdccommandshort(struct ata_channel *chp, int drive, int command)
{
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
