/*
* Not (c) 2007 Matthew Orgass
* This file is public domain, meaning anyone can make any use of part or all
* of this file including copying into other works without credit. Any use,
* modified or not, is solely the responsibility of the user. If this file is
* part of a collection then use in the collection is governed by the terms of
* the collection.
*/
/*
* Cypress/ScanLogic SL811HS/T USB Host Controller
* Datasheet, Errata, and App Note available at www.cypress.com
*
* Uses: Ratoc CFU1U PCMCIA USB Host Controller, Nereid X68k USB HC, ISA
* HCs. The Ratoc CFU2 uses a different chip.
*
* This chip puts the serial in USB. It implements USB by means of an eight
* bit I/O interface. It can be used for ISA, PCMCIA/CF, parallel port,
* serial port, or any eight bit interface. It has 256 bytes of memory, the
* first 16 of which are used for register access. There are two sets of
* registers for sending individual bus transactions. Because USB is polled,
* this organization means that some amount of card access must often be made
* when devices are attached, even if when they are not directly being used.
* A per-ms frame interrupt is necessary and many devices will poll with a
* per-frame bulk transfer.
*
* It is possible to write a little over two bytes to the chip (auto
* incremented) per full speed byte time on the USB. Unfortunately,
* auto-increment does not work reliably so write and bus speed is
* approximately the same for full speed devices.
*
* In addition to the 240 byte packet size limit for isochronous transfers,
* this chip has no means of determining the current frame number other than
* getting all 1ms SOF interrupts, which is not always possible even on a fast
* system. Isochronous transfers guarantee that transfers will never be
* retried in a later frame, so this can cause problems with devices beyond
* the difficulty in actually performing the transfer most frames. I tried
* implementing isoc transfers and was able to play CD-derrived audio via an
* iMic on a 2GHz PC, however it would still be interrupted at times and
* once interrupted, would stay out of sync. All isoc support has been
* removed.
*
* BUGS: all chip revisions have problems with low speed devices through hubs.
* The chip stops generating SOF with hubs that send SE0 during SOF. See
* comment in dointr(). All performance enhancing features of this chip seem
* not to work properly, most confirmed buggy in errata doc.
*
*/
/*
* The hard interrupt is the main entry point. Start, callbacks, and repeat
* are the only others called frequently.
*
* Since this driver attaches to pcmcia, card removal at any point should be
* expected and not cause panics or infinite loops.
*/
/*
* XXX TODO:
* copy next output packet while transferring
* usb suspend
* could keep track of known values of all buffer space?
* combined print/log function for errors
*
* ub_usepolling support is untested and may not work
*/
/*
* Maximum allowable reserved bus time. Since intr/isoc transfers have
* unconditional priority, this is all that ensures control and bulk transfers
* get a chance. It is a single value for all frames since all transfers can
* use multiple consecutive frames if an error is encountered. Note that it
* is not really possible to fill the bus with transfers, so this value should
* be on the low side. Defaults to giving a warning unless SLHCI_NO_OVERTIME
* is defined. Full time is 12000 - END_BUSTIME.
*/
#ifndef SLHCI_RESERVED_BUSTIME
#define SLHCI_RESERVED_BUSTIME 5000
#endif
/*
* Rate for "exceeds reserved bus time" warnings (default) or errors.
* Warnings only happen when an endpoint open causes the time to go above
* SLHCI_RESERVED_BUSTIME, not if it is already above.
*/
#ifndef SLHCI_OVERTIME_WARNING_RATE
#define SLHCI_OVERTIME_WARNING_RATE { 60, 0 } /* 60 seconds */
#endif
static const struct timeval reserved_warn_rate = SLHCI_OVERTIME_WARNING_RATE;
/*
* For EOF, the spec says 42 bit times, plus (I think) a possible hub skew of
* 20 bit times. By default leave 66 bit times to start the transfer beyond
* the required time. Units are full-speed bit times (a bit over 5us per 64).
* Only multiples of 64 are significant.
*/
#define SLHCI_STANDARD_END_BUSTIME 128
#ifndef SLHCI_EXTRA_END_BUSTIME
#define SLHCI_EXTRA_END_BUSTIME 0
#endif
/*
* This is an approximation of the USB worst-case timings presented on p. 54 of
* the USB 1.1 spec translated to full speed bit times.
* FS = full speed with handshake, FSII = isoc in, FSIO = isoc out,
* FSI = isoc (worst case), LS = low speed
*/
#define SLHCI_FS_CONST 114
#define SLHCI_FSII_CONST 92
#define SLHCI_FSIO_CONST 80
#define SLHCI_FSI_CONST 92
#define SLHCI_LS_CONST 804
#ifndef SLHCI_PRECICE_BUSTIME
/*
* These values are < 3% too high (compared to the multiply and divide) for
* max sized packets.
*/
#define SLHCI_FS_DATA_TIME(len) (((u_int)(len)<<3)+(len)+((len)>>1))
#define SLHCI_LS_DATA_TIME(len) (((u_int)(len)<<6)+((u_int)(len)<<4))
#else
#define SLHCI_FS_DATA_TIME(len) (56*(len)/6)
#define SLHCI_LS_DATA_TIME(len) (449*(len)/6)
#endif
/*
* Set SLHCI_WAIT_SIZE to the desired maximum size of single FS transfer
* to poll for after starting a transfer. 64 gets all full speed transfers.
* Note that even if 0 polling will occur if data equal or greater than the
* transfer size is copied to the chip while the transfer is in progress.
* Setting SLHCI_WAIT_TIME to -12000 will disable polling.
*/
#ifndef SLHCI_WAIT_SIZE
#define SLHCI_WAIT_SIZE 8
#endif
#ifndef SLHCI_WAIT_TIME
#define SLHCI_WAIT_TIME (SLHCI_FS_CONST + \
SLHCI_FS_DATA_TIME(SLHCI_WAIT_SIZE))
#endif
const int slhci_wait_time = SLHCI_WAIT_TIME;
/* Check IER values for corruption after this many unrecognized interrupts. */
#ifndef SLHCI_IER_CHECK_FREQUENCY
#ifdef SLHCI_DEBUG
#define SLHCI_IER_CHECK_FREQUENCY 1
#else
#define SLHCI_IER_CHECK_FREQUENCY 100
#endif
#endif
/* Note that buffer points to the start of the buffer for this transfer. */
struct slhci_pipe {
struct usbd_pipe pipe;
struct usbd_xfer *xfer; /* xfer in progress */
uint8_t *buffer; /* I/O buffer (if needed) */
struct gcq ap; /* All pipes */
struct gcq to; /* Timeout list */
struct gcq xq; /* Xfer queues */
unsigned int pflags; /* Pipe flags */
#define PF_GONE (0x01) /* Pipe is on disabled device */
#define PF_TOGGLE (0x02) /* Data toggle status */
#define PF_LS (0x04) /* Pipe is low speed */
#define PF_PREAMBLE (0x08) /* Needs preamble */
Frame to_frame; /* Frame number for timeout */
Frame frame; /* Frame number for intr xfer */
Frame lastframe; /* Previous frame number for intr */
uint16_t bustime; /* Worst case bus time usage */
uint16_t newbustime[2]; /* new bustimes (see index below) */
uint8_t tregs[4]; /* ADR, LEN, PID, DEV */
uint8_t newlen[2]; /* 0 = short data, 1 = ctrl data */
uint8_t newpid; /* for ctrl */
uint8_t wantshort; /* last xfer must be short */
uint8_t control; /* Host control register settings */
uint8_t nerrs; /* Current number of errors */
uint8_t ptype; /* Pipe type */
};
void
slhci_dump_cc_times(int n) {
struct slhci_cc_times *times;
int i;
switch (n) {
default:
case 0:
printf("USBA start transfer to intr:\n");
times = &t_ab[A];
break;
case 1:
printf("USBB start transfer to intr:\n");
times = &t_ab[B];
break;
case 2:
printf("abdone:\n");
times = &t_abdone;
break;
case 3:
printf("copy to device:\n");
times = &t_copy_to_dev;
break;
case 4:
printf("copy from device:\n");
times = &t_copy_from_dev;
break;
case 5:
printf("intr to intr:\n");
times = &t_intr;
break;
case 6:
printf("lock to release:\n");
times = &t_lock;
break;
case 7:
printf("delay time:\n");
times = &t_delay;
break;
case 8:
printf("hard interrupt enter to exit:\n");
times = &t_hard_int;
break;
case 9:
printf("callback:\n");
times = &t_callback;
break;
}
if (times->wraparound)
for (i = times->current + 1; i < SLHCI_N_TIMES; i++)
printf("start " CC_TYPE_FMT " stop " CC_TYPE_FMT
" difference %8i miscdata %#x\n",
times->times[i].start, times->times[i].stop,
(int)(times->times[i].stop -
times->times[i].start), times->times[i].miscdata);
/* Constified so you can read the values from ddb */
const int SLHCI_D_TRACE = 0x0001;
const int SLHCI_D_MSG = 0x0002;
const int SLHCI_D_XFER = 0x0004;
const int SLHCI_D_MEM = 0x0008;
const int SLHCI_D_INTR = 0x0010;
const int SLHCI_D_SXFER = 0x0020;
const int SLHCI_D_ERR = 0x0080;
const int SLHCI_D_BUF = 0x0100;
const int SLHCI_D_SOFT = 0x0200;
const int SLHCI_D_WAIT = 0x0400;
const int SLHCI_D_ROOT = 0x0800;
/* SOF/NAK alone normally ignored, SOF also needs D_INTR */
const int SLHCI_D_SOF = 0x1000;
const int SLHCI_D_NAK = 0x2000;
#define SLHCI_DEXEC(x, y) do { if ((slhcidebug & SLHCI_ ## x)) { y; } \
} while (/*CONSTCOND*/ 0)
#define DDOLOG(f, a, b, c, d) do { KERNHIST_LOG(usbhist, f, a, b, c, d); \
} while (/*CONSTCOND*/0)
#define DLOG(x, f, a, b, c, d) SLHCI_DEXEC(x, DDOLOG(f, a, b, c, d))
/*
* DDOLOGBUF logs a buffer up to 8 bytes at a time. No identifier so that we
* can make it a real function.
*/
static void
DDOLOGBUF(uint8_t *buf, unsigned int length)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
int i;
#if defined(DEBUG) || defined(SLHCI_DEBUG)
if (__predict_false(spipe->ptype == PT_INTR &&
xfer->ux_length > spipe->tregs[LEN])) {
printf("%s: Long INTR transfer not supported!\n",
SC_NAME(sc));
DDOLOG("Long INTR transfer not supported!", 0, 0, 0, 0);
xfer->ux_status = USBD_INVAL;
}
#endif
} else {
/* ptype may be currently set to any control transfer type. */
SLHCI_DEXEC(D_TRACE, slhci_log_xfer(xfer));
/*
* The goal of newbustime and newlen is to avoid bustime calculation
* in the interrupt. The calculations are not too complex, but they
* complicate the conditional logic somewhat and doing them all in the
* same place shares constants. Index 0 is "short length" for bulk and
* ctrl data and 1 is "full length" for ctrl data (bulk/intr are
* already set to full length).
*/
if (spipe->pflags & PF_LS) {
/*
* Setting PREAMBLE for directly connected LS devices will
* lock up the chip.
*/
if (spipe->pflags & PF_PREAMBLE)
spipe->control |= SL11_EPCTRL_PREAMBLE;
if (max_packet <= 8) {
spipe->bustime = SLHCI_LS_CONST +
SLHCI_LS_DATA_TIME(spipe->tregs[LEN]);
spipe->newbustime[0] = SLHCI_LS_CONST +
SLHCI_LS_DATA_TIME(spipe->newlen[0]);
spipe->newbustime[1] = SLHCI_LS_CONST +
SLHCI_LS_DATA_TIME(spipe->newlen[1]);
} else
xfer->ux_status = USBD_INVAL;
} else {
UL_SLASSERT(pipe->up_dev->ud_speed == USB_SPEED_FULL, sc,
spipe, xfer, return USBD_IN_PROGRESS);
if (max_packet <= SL11_MAX_PACKET_SIZE) {
spipe->bustime = SLHCI_FS_CONST +
SLHCI_FS_DATA_TIME(spipe->tregs[LEN]);
spipe->newbustime[0] = SLHCI_FS_CONST +
SLHCI_FS_DATA_TIME(spipe->newlen[0]);
spipe->newbustime[1] = SLHCI_FS_CONST +
SLHCI_FS_DATA_TIME(spipe->newlen[1]);
} else
xfer->ux_status = USBD_INVAL;
}
/*
* The datasheet incorrectly indicates that DIRECTION is for
* "transmit to host". It is for OUT and SETUP. The app note
* describes its use correctly.
*/
if ((spipe->tregs[PID] & SL11_PID_BITS) != SL11_PID_IN)
spipe->control |= SL11_EPCTRL_DIRECTION;
/*
* The endpoint descriptor will not have been set up yet in the case
* of the standard control pipe, so the max packet checks are also
* necessary in start.
*/
/*
* Must be called before the ISR is registered. Interrupts can be shared so
* slhci_intr could be called as soon as the ISR is registered.
* Note max_current argument is actual current, but stored as current/2
*/
void
slhci_preinit(struct slhci_softc *sc, PowerFunc pow, bus_space_tag_t iot,
bus_space_handle_t ioh, uint16_t max_current, uint32_t stride)
{
struct slhci_transfers *t;
int i;
for (i = 0; i <= Q_MAX; i++)
gcq_init_head(&t->q[i]);
gcq_init_head(&t->timed);
gcq_init_head(&t->to);
gcq_init_head(&t->ap);
gcq_init_head(&sc->sc_waitq);
}
/*
* It is not safe to call the soft interrupt directly as
* usb_schedsoftintr does in the ub_usepolling case (due to locking).
*/
sc->sc_cb_softintr = softint_establish(SOFTINT_NET,
slhci_callback_entry, sc);
if (t->sltype == SLTYPE_SL811HS_R12)
rev = "(rev 1.2)";
else if (t->sltype == SLTYPE_SL811HS_R14)
rev = "(rev 1.4 or 1.5)";
else
rev = "(unknown revision)";
aprint_normal("%s: ScanLogic SL811HS/T USB Host Controller %s\n",
SC_NAME(sc), rev);
aprint_normal("%s: Max Current %u mA (value by code, not by probe)\n",
SC_NAME(sc), t->max_current * 2);
if (!sc->sc_enable_power)
t->flags |= F_REALPOWER;
t->flags |= F_ACTIVE;
/* Attach usb and uhub. */
sc->sc_child = config_found(SC_DEV(sc), &sc->sc_bus, usbctlprint,
CFARGS_NONE);
if (!sc->sc_child)
return -1;
else
return 0;
}
int
slhci_detach(struct slhci_softc *sc, int flags)
{
struct slhci_transfers *t;
int ret;
t = &sc->sc_transfers;
/* By this point bus access is no longer allowed. */
KASSERT(!(t->flags & F_ACTIVE));
/*
* To be MPSAFE is not sufficient to cancel callouts and soft
* interrupts and assume they are dead since the code could already be
* running or about to run. Wait until they are known to be done.
*/
while (t->flags & (F_RESET|F_CALLBACK))
tsleep(&sc, PPAUSE, "slhci_detach", hz);
if (sc->sc_child)
ret = config_detach(sc->sc_child, flags);
#ifdef SLHCI_MEM_ACCOUNTING
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
if (sc->sc_mem_use) {
printf("%s: Memory still in use after detach! mem_use (count)"
" = %d\n", SC_NAME(sc), sc->sc_mem_use);
DDOLOG("Memory still in use after detach! mem_use (count)"
" = %d", sc->sc_mem_use, 0, 0, 0);
}
#endif
printf("%s: Clear toggle on transfer in progress! halted\n",
SC_NAME(sc));
DDOLOG("Clear toggle on transfer in progress! halted",
0, 0, 0, 0);
slhci_halt(sc, NULL, NULL);
}
#endif
}
mutex_enter(&sc->sc_intr_lock);
slhci_reset(sc);
/*
* We cannot call the callback directly since we could then be reset
* again before finishing and need the callout delay for timing.
* Scheduling the callout again before we exit would defeat the reap
* mechanism since we could be unlocked while the reset flag is not
* set. The callback code will check the wait queue.
*/
slhci_callback_schedule(sc);
mutex_exit(&sc->sc_intr_lock);
}
do {
irq = slhci_dointr(sc);
ret |= irq;
slhci_main(sc);
} while (irq);
mutex_exit(&sc->sc_intr_lock);
stop_cc_time(&t_hard_int);
return ret;
}
/* called with interrupt lock only held. */
void
slhci_main(struct slhci_softc *sc)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_transfers *t;
t = &sc->sc_transfers;
KASSERT(mutex_owned(&sc->sc_intr_lock));
waitcheck:
slhci_waitintr(sc, slhci_wait_time);
/*
* The direct call is needed in the ub_usepolling and disabled cases
* since the soft interrupt is not available. In the disabled case,
* this code can be reached from the usb detach, after the reaping of
* the soft interrupt. That test could be !F_ACTIVE, but there is no
* reason not to make the callbacks directly in the other DISABLED
* cases.
*/
if ((t->flags & F_ROOTINTR) || !gcq_empty(&t->q[Q_CALLBACKS])) {
if (__predict_false(sc->sc_bus.ub_usepolling ||
t->flags & F_DISABLED))
slhci_callback(sc);
else
slhci_callback_schedule(sc);
}
/*
* After calling waitintr it is necessary to either call slhci_callback or
* schedule the callback if necessary. The callback cannot be called directly
* from the hard interrupt since it interrupts at a high IPL and callbacks
* can do copyout and such.
*/
static void
slhci_waitintr(struct slhci_softc *sc, int wait_time)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_transfers *t;
t = &sc->sc_transfers;
KASSERT(mutex_owned(&sc->sc_intr_lock));
if (__predict_false(sc->sc_bus.ub_usepolling))
wait_time = 12000;
/* If we have an insertion event we do not care about anything else. */
if (__predict_false(r & SL11_ISR_INSERT)) {
slhci_insert(sc);
DLOG(D_INTR, "... done", 0, 0, 0, 0);
return 1;
}
stop_cc_time(&t_intr);
start_cc_time(&t_intr, r);
if (r & SL11_ISR_SOF) {
t->frame++;
gcq_merge_tail(&t->q[Q_CB], &t->q[Q_NEXT_CB]);
/*
* SOFCHECK flags are cleared in tstart. Two flags are needed
* since the first SOF interrupt processed after the transfer
* is started might have been generated before the transfer
* was started.
*/
if (__predict_false(t->flags & F_SOFCHECK2 && t->flags &
(F_AINPROG|F_BINPROG))) {
printf("%s: Missed transfer completion. halted\n",
SC_NAME(sc));
DDOLOG("Missed transfer completion. halted", 0, 0, 0,
0);
slhci_halt(sc, NULL, NULL);
return 1;
} else if (t->flags & F_SOFCHECK1) {
t->flags |= F_SOFCHECK2;
} else
t->flags |= F_SOFCHECK1;
/*
* This should never happen (unless card removal just
* occurred) but appeared frequently when both
* transfers were started at the same time and was
* accompanied by data corruption. It still happens
* at times. I have not seen data correption except
* when the STATUS bit gets set, which now causes the
* driver to halt, however this should still not
* happen so the warning is kept. See comment in
* abdone, below.
*/
printf("%s: Transfer reported done but not started! "
"Verify data integrity if not detaching. "
" flags %#x r %x\n", SC_NAME(sc), t->flags, r);
if (!(t->flags & F_AINPROG))
r &= ~SL11_ISR_USBA;
else
r &= ~SL11_ISR_USBB;
}
t->pend = INT_MAX;
if (r & SL11_ISR_USBA)
ab = A;
else
ab = B;
/*
* This happens when a low speed device is attached to
* a hub with chip rev 1.5. SOF stops, but a few transfers
* still work before causing this error.
*/
if (!(t->flags & (ab ? F_BINPROG : F_AINPROG))) {
printf("%s: %s done but not in progress! halted\n",
SC_NAME(sc), ab ? "B" : "A");
DDOLOG("AB=%d done but not in progress! halted", ab,
0, 0, 0);
slhci_halt(sc, NULL, NULL);
return 1;
}
/*
* skip this one if aborted; do not call return from the rest of the
* function unless halting, else t->len will not be cleared.
*/
if (spipe == NULL)
goto done;
/*
* I saw no status or remaining length greater than the requested
* length in early driver versions in circumstances I assumed caused
* excess power draw. I am no longer able to reproduce this when
* causing excess power draw circumstances.
*
* Disabling a power check and attaching aue to a keyboard and hub
* that is directly attached (to CFU1U, 100mA max, aue 160mA, keyboard
* 98mA) sometimes works and sometimes fails to configure. After
* removing the aue and attaching a self-powered umass dvd reader
* (unknown if it draws power from the host also) soon a single Error
* status occurs then only timeouts. The controller soon halts freeing
* memory due to being ONQU instead of BUSY. This may be the same
* basic sequence that caused the no status/bad length errors. The
* umass device seems to work (better at least) with the keyboard hub
* when not first attaching aue (tested once reading an approximately
* 200MB file).
*
* Overflow can indicate that the device and host disagree about how
* much data has been transferred. This may indicate a problem at any
* point during the transfer, not just when the error occurs. It may
* indicate data corruption. A warning message is printed.
*
* Trying to use both A and B transfers at the same time results in
* incorrect transfer completion ISR reports and the status will then
* include SL11_EPSTAT_SETUP, which is apparently set while the
* transfer is in progress. I also noticed data corruption, even
* after waiting for the transfer to complete. The driver now avoids
* trying to start both at the same time.
*
* I had accidently initialized the B registers before they were valid
* in some driver versions. Since every other performance enhancing
* feature has been confirmed buggy in the errata doc, I have not
* tried both transfers at once again with the documented
* initialization order.
*
* However, I have seen this problem again ("done but not started"
* errors), which in some cases cases the SETUP status bit to remain
* set on future transfers. In other cases, the SETUP bit is not set
* and no data corruption occurs. This occurred while using both umass
* and aue on a powered hub (maybe triggered by some local activity
* also) and needs several reads of the 200MB file to trigger. The
* driver now halts if SETUP is detected.
*/
head = Q_CALLBACKS;
} else {
head = Q_NEXT_CB;
}
} else if (spipe->ptype == PT_CTRL_SETUP) {
spipe->tregs[PID] = spipe->newpid;
if (xfer->ux_length) {
LK_SLASSERT(spipe->newlen[1] != 0, sc, spipe, xfer,
return);
spipe->tregs[LEN] = spipe->newlen[1];
spipe->bustime = spipe->newbustime[1];
spipe->buffer = xfer->ux_buf;
spipe->ptype = PT_CTRL_DATA;
} else {
status_setup:
/* CTRL_DATA swaps direction in PID then jumps here */
spipe->tregs[LEN] = 0;
if (spipe->pflags & PF_LS)
spipe->bustime = SLHCI_LS_CONST;
else
spipe->bustime = SLHCI_FS_CONST;
spipe->ptype = PT_CTRL_STATUS;
spipe->buffer = NULL;
}
/* Status or first data packet must be DATA1. */
spipe->control |= SL11_EPCTRL_DATATOGGLE;
if ((spipe->tregs[PID] & SL11_PID_BITS) == SL11_PID_IN)
spipe->control &= ~SL11_EPCTRL_DIRECTION;
else
spipe->control |= SL11_EPCTRL_DIRECTION;
head = Q_CB;
} else if (spipe->ptype == PT_CTRL_STATUS) {
head = Q_CALLBACKS;
} else { /* bulk, intr, control data */
xfer->ux_actlen += actlen;
spipe->control ^= SL11_EPCTRL_DATATOGGLE;
if (actlen == spipe->tregs[LEN] &&
(xfer->ux_length > xfer->ux_actlen || spipe->wantshort)) {
spipe->buffer += actlen;
LK_SLASSERT(xfer->ux_length >= xfer->ux_actlen, sc,
spipe, xfer, return);
if (xfer->ux_length - xfer->ux_actlen < actlen) {
spipe->wantshort = 0;
spipe->tregs[LEN] = spipe->newlen[0];
spipe->bustime = spipe->newbustime[0];
LK_SLASSERT(xfer->ux_actlen +
spipe->tregs[LEN] == xfer->ux_length, sc,
spipe, xfer, return);
}
head = Q_CB;
} else if (spipe->ptype == PT_CTRL_DATA) {
spipe->tregs[PID] ^= SLHCI_PID_SWAP_IN_OUT;
goto status_setup;
} else {
if (spipe->ptype == PT_INTR) {
spipe->lastframe +=
spipe->pipe.up_interval;
/*
* If ack, we try to keep the
* interrupt rate by using lastframe
* instead of the current frame.
*/
spipe->frame = spipe->lastframe +
spipe->pipe.up_interval;
}
/*
* Set the toggle for the next transfer. It
* has already been toggled above, so the
* current setting will apply to the next
* transfer.
*/
if (spipe->control & SL11_EPCTRL_DATATOGGLE)
spipe->pflags |= PF_TOGGLE;
else
spipe->pflags &= ~PF_TOGGLE;
head = Q_CALLBACKS;
}
}
if (head == Q_CALLBACKS) {
gcq_remove(&spipe->to);
if (t->flags & (F_AINPROG|F_BINPROG|F_DISABLED))
return;
/*
* We have about 6 us to get from the bus time check to
* starting the transfer or we might babble or the chip might fail to
* signal transfer complete. This leaves no time for any other
* interrupts.
*/
remaining_bustime = (int)(slhci_read(sc, SL811_CSOF)) << 6;
remaining_bustime -= SLHCI_END_BUSTIME;
/*
* Start one transfer only, clearing any aborted transfers that are
* not yet in progress and skipping missed isoc. It is easier to copy
* & paste most of the A/B sections than to make the logic work
* otherwise and this allows better constant use.
*/
if (t->flags & F_AREADY) {
spipe = t->spipe[A];
if (spipe == NULL) {
t->flags &= ~F_AREADY;
t->len[A] = -1;
} else if (remaining_bustime >= spipe->bustime) {
t->flags &= ~(F_AREADY|F_SOFCHECK1|F_SOFCHECK2);
t->flags |= F_AINPROG;
start_cc_time(&t_ab[A], spipe->tregs[LEN]);
slhci_write(sc, SL11_E0CTRL, spipe->control);
goto pend;
}
}
if (t->flags & F_BREADY) {
spipe = t->spipe[B];
if (spipe == NULL) {
t->flags &= ~F_BREADY;
t->len[B] = -1;
} else if (remaining_bustime >= spipe->bustime) {
t->flags &= ~(F_BREADY|F_SOFCHECK1|F_SOFCHECK2);
t->flags |= F_BINPROG;
start_cc_time(&t_ab[B], spipe->tregs[LEN]);
slhci_write(sc, SL11_E1CTRL, spipe->control);
pend:
t->pend = spipe->bustime;
}
}
}
/* Check that this transfer can fit in the remaining memory. */
if (t->len[A] + t->len[B] + spipe->tregs[LEN] + 1 >
SL11_MAX_PACKET_SIZE) {
DLOG(D_XFER, "Transfer does not fit. alen %jd blen %jd "
"len %jd", t->len[A], t->len[B], spipe->tregs[LEN],
0);
return;
}
gcq_remove(&spipe->xq);
if (t->len[A] == -1) {
ab = A;
spipe->tregs[ADR] = SL11_BUFFER_START;
} else {
ab = B;
spipe->tregs[ADR] = SL11_BUFFER_END -
spipe->tregs[LEN];
}
/*
* Called to deactivate or stop use of the controller instead of panicking.
* Will cancel the xfer correctly even when not on a list.
*/
static usbd_status
slhci_halt(struct slhci_softc *sc, struct slhci_pipe *spipe,
struct usbd_xfer *xfer)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_transfers *t;
if (t->flags & F_ACTIVE) {
slhci_intrchange(sc, 0);
/*
* leave power on when halting in case flash devices or disks
* are attached, which may be writing and could be damaged
* by abrupt power loss. The root hub clear power feature
* should still work after halting.
*/
}
/* One last callback for the drain and device removal. */
slhci_do_callback_schedule(sc);
return USBD_NORMAL_COMPLETION;
}
/*
* There are three interrupt states: no interrupts during reset and after
* device deactivation, INSERT only for no device present but power on, and
* SOF, INSERT, ADONE, and BDONE when device is present.
*/
static void
slhci_intrchange(struct slhci_softc *sc, uint8_t new_ier)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
KASSERT(mutex_owned(&sc->sc_intr_lock));
if (sc->sc_ier != new_ier) {
DLOG(D_INTR, "New IER %#jx", new_ier, 0, 0, 0);
sc->sc_ier = new_ier;
slhci_write(sc, SL11_IER, new_ier);
BSB_SYNC(sc->iot, sc->ioh, sc->pst, sc->psz);
}
}
/*
* Drain: cancel all pending transfers and put them on the callback list and
* set the UDISABLED flag. UDISABLED is cleared only by reset.
*/
static void
slhci_drain(struct slhci_softc *sc)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_transfers *t;
struct slhci_pipe *spipe;
struct gcq *q;
int i;
KASSERT(mutex_owned(&sc->sc_intr_lock));
t = &sc->sc_transfers;
DLOG(D_MSG, "DRAIN flags %#jx", t->flags, 0,0,0);
t->pend = INT_MAX;
for (i = 0; i <= 1; i++) {
t->len[i] = -1;
if (t->spipe[i] != NULL) {
enter_callback(t, t->spipe[i]);
t->spipe[i] = NULL;
}
}
/* Merge the queues into the callback queue. */
gcq_merge_tail(&t->q[Q_CALLBACKS], &t->q[Q_CB]);
gcq_merge_tail(&t->q[Q_CALLBACKS], &t->q[Q_NEXT_CB]);
gcq_merge_tail(&t->q[Q_CALLBACKS], &t->timed);
/*
* Cancel all pipes. Note that not all of these may be on the
* callback queue yet; some could be in slhci_start, for example.
*/
FOREACH_AP(q, t, spipe) {
spipe->pflags |= PF_GONE;
spipe->pipe.up_repeat = 0;
spipe->pipe.up_aborting = 1;
if (spipe->xfer != NULL)
spipe->xfer->ux_status = USBD_CANCELLED;
}
/*
* RESET: SL11_CTRL_RESETENGINE=1 and SL11_CTRL_JKSTATE=0 for 50ms
* reconfigure SOF after reset, must wait 2.5us before USB bus activity (SOF)
* check attached device speed.
* must wait 100ms before USB transaction according to app note, 10ms
* by spec. uhub does this delay
*
* Started from root hub set feature reset, which does step one.
* ub_usepolling will call slhci_reset directly, otherwise the callout goes
* through slhci_reset_entry.
*/
void
slhci_reset(struct slhci_softc *sc)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_transfers *t;
struct slhci_pipe *spipe;
struct gcq *q;
uint8_t r, pol, ctrl;
t = &sc->sc_transfers;
KASSERT(mutex_owned(&sc->sc_intr_lock));
if (r & SL11_ISR_INSERT)
slhci_write(sc, SL11_ISR, SL11_ISR_INSERT);
if (r & SL11_ISR_NODEV) {
DLOG(D_MSG, "NC", 0,0,0,0);
/*
* Normally, the hard interrupt insert routine will issue
* CCONNECT, however we need to do it here if the detach
* happened during reset.
*/
if (!(t->flags & F_NODEV))
t->flags |= F_CCONNECT|F_ROOTINTR|F_NODEV;
slhci_intrchange(sc, SL11_IER_INSERT);
} else {
if (t->flags & F_NODEV)
t->flags |= F_CCONNECT;
t->flags &= ~(F_NODEV|F_LOWSPEED);
if (r & SL11_ISR_DATA) {
DLOG(D_MSG, "FS", 0,0,0,0);
pol = ctrl = 0;
} else {
DLOG(D_MSG, "LS", 0,0,0,0);
pol = SL811_CSOF_POLARITY;
ctrl = SL11_CTRL_LOWSPEED;
t->flags |= F_LOWSPEED;
}
/* Enable SOF auto-generation */
t->frame = 0; /* write to SL811_CSOF will reset frame */
slhci_write(sc, SL11_SOFTIME, 0xe0);
slhci_write(sc, SL811_CSOF, pol|SL811_CSOF_MASTER|0x2e);
slhci_write(sc, SL11_CTRL, ctrl|SL11_CTRL_ENABLESOF);
/*
* According to the app note, ARM must be set
* for SOF generation to work. We initialize all
* USBA registers here for current_tregs.
*/
slhci_write(sc, SL11_E0ADDR, SL11_BUFFER_START);
slhci_write(sc, SL11_E0LEN, 0);
slhci_write(sc, SL11_E0PID, SL11_PID_SOF);
slhci_write(sc, SL11_E0DEV, 0);
slhci_write(sc, SL11_E0CTRL, SL11_EPCTRL_ARM);
/*
* Initialize B registers. This can't be done earlier since
* they are not valid until the SL811_CSOF register is written
* above due to SL11H compatibility.
*/
slhci_write(sc, SL11_E1ADDR, SL11_BUFFER_END - 8);
slhci_write(sc, SL11_E1LEN, 0);
slhci_write(sc, SL11_E1PID, 0);
slhci_write(sc, SL11_E1DEV, 0);
#ifdef SLHCI_DEBUG
static int
slhci_memtest(struct slhci_softc *sc)
{
enum { ASC, DESC, EITHER = ASC }; /* direction */
enum { READ, WRITE }; /* operation */
const char *ptr, *elem;
size_t i;
const int low = SL11_BUFFER_START, high = SL11_BUFFER_END;
int addr = 0, dir = ASC, op = READ;
/* Extended March C- test algorithm (SOFs also) */
const char test[] = "E(w0) A(r0w1r1) A(r1w0r0) D(r0w1) D(r1w0) E(r0)";
char c;
const uint8_t dbs[] = { 0x00, 0x0f, 0x33, 0x55 }; /* data backgrounds */
uint8_t db;
/* Perform memory test for all data backgrounds. */
for (i = 0; i < __arraycount(dbs); i++) {
ptr = test;
elem = ptr;
/* Walk test algorithm string. */
while ((c = *ptr++) != '\0')
switch (tolower((int)c)) {
case 'a':
/* Address sequence is in ascending order. */
dir = ASC;
break;
case 'd':
/* Address sequence is in descending order. */
dir = DESC;
break;
case 'e':
/* Address sequence is in either order. */
dir = EITHER;
break;
case '(':
/* Start of test element (sequence). */
elem = ptr;
addr = (dir == ASC) ? low : high;
break;
case 'r':
/* read operation */
op = READ;
break;
case 'w':
/* write operation */
op = WRITE;
break;
case '0':
case '1':
/*
* Execute previously set-up operation by
* reading/writing non-inverted ('0') or
* inverted ('1') data background.
*/
db = (c - '0') ? ~dbs[i] : dbs[i];
if (op == READ) {
if (slhci_read(sc, addr) != db)
return -1;
} else
slhci_write(sc, addr, db);
break;
case ')':
/*
* End of element: Repeat same element with next
* address or continue to next element.
*/
addr = (dir == ASC) ? addr + 1 : addr - 1;
if (addr >= low && addr <= high)
ptr = elem;
break;
default:
/* Do nothing. */
break;
}
}
return 0;
}
#endif
/* returns 1 if succeeded, 0 if failed, reserve == 0 is unreserve */
static int
slhci_reserve_bustime(struct slhci_softc *sc, struct slhci_pipe *spipe, int
reserve)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_transfers *t;
int bustime, max_packet;
KASSERT(mutex_owned(&sc->sc_intr_lock));
t = &sc->sc_transfers;
max_packet = UGETW(spipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
/*
* We do not have a way to detect over current or babble and
* suspend is currently not implemented, so connect and reset
* are the only changes that need to be reported.
*/
change = 0;
if (t->flags & F_CCONNECT)
change |= UPS_C_CONNECT_STATUS;
if (t->flags & F_CRESET)
change |= UPS_C_PORT_RESET;
status = 0;
if (!(t->flags & F_NODEV))
status |= UPS_CURRENT_CONNECT_STATUS;
if (!(t->flags & F_UDISABLED))
status |= UPS_PORT_ENABLED;
if (t->flags & F_RESET)
status |= UPS_RESET;
if (t->flags & F_POWER)
status |= UPS_PORT_POWER;
if (t->flags & F_LOWSPEED)
status |= UPS_LOW_SPEED;
USETW(ps->wPortStatus, status);
USETW(ps->wPortChange, change);
DLOG(D_ROOT, "status=%#.4jx, change=%#.4jx", status, change, 0,0);
}
static int
slhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
void *buf, int buflen)
{
SLHCIHIST_FUNC(); SLHCIHIST_CALLED();
struct slhci_softc *sc = SLHCI_BUS2SC(bus);
struct slhci_transfers *t = &sc->sc_transfers;
usbd_status error = USBD_IOERROR; /* XXX should be STALL */
uint16_t len, value, index;
uint8_t type;
int actlen = 0;
len = UGETW(req->wLength);
value = UGETW(req->wValue);
index = UGETW(req->wIndex);
type = req->bmRequestType;
SLHCI_DEXEC(D_TRACE, slhci_log_req(req));
/*
* USB requests for hubs have two basic types, standard and class.
* Each could potentially have recipients of device, interface,
* endpoint, or other. For the hub class, CLASS_OTHER means the port
* and CLASS_DEVICE means the hub. For standard requests, OTHER
* is not used. Standard request are described in section 9.4 of the
* standard, hub class requests in 11.16. Each request is either read
* or write.
*
* Clear Feature, Set Feature, and Status are defined for each of the
* used recipients. Get Descriptor and Set Descriptor are defined for
* both standard and hub class types with different descriptors.
* Other requests have only one defined recipient and type. These
* include: Get/Set Address, Get/Set Configuration, Get/Set Interface,
* and Synch Frame for standard requests and Get Bus State for hub
* class.
*
* When a device is first powered up it has address 0 until the
* address is set.
*
* Hubs are only allowed to support one interface and may not have
* isochronous endpoints. The results of the related requests are
* undefined.
*
* The standard requires invalid or unsupported requests to return
* STALL in the data stage, however this does not work well with
* current error handling. XXX
*
* Some unsupported fields:
* Clear Hub Feature is for C_HUB_LOCAL_POWER and C_HUB_OVER_CURRENT
* Set Device Features is for ENDPOINT_HALT and DEVICE_REMOTE_WAKEUP
* Get Bus State is optional sample of D- and D+ at EOF2
*/
switch (req->bRequest) {
/* Write Requests */
case UR_CLEAR_FEATURE:
if (type == UT_WRITE_CLASS_OTHER) {
if (index == 1 /* Port */) {
mutex_enter(&sc->sc_intr_lock);
error = slhci_clear_feature(sc, value);
mutex_exit(&sc->sc_intr_lock);
} else
DLOG(D_ROOT, "Clear Port Feature "
"index = %#.4jx", index, 0,0,0);
}
break;
case UR_SET_FEATURE:
if (type == UT_WRITE_CLASS_OTHER) {
if (index == 1 /* Port */) {
mutex_enter(&sc->sc_intr_lock);
error = slhci_set_feature(sc, value);
mutex_exit(&sc->sc_intr_lock);
} else
DLOG(D_ROOT, "Set Port Feature "
"index = %#.4jx", index, 0,0,0);
} else if (type != UT_WRITE_CLASS_DEVICE)
DLOG(D_ROOT, "Set Device Feature "
"ENDPOINT_HALT or DEVICE_REMOTE_WAKEUP "
"not supported", 0,0,0,0);
break;
/* Read Requests */
case UR_GET_STATUS:
if (type == UT_READ_CLASS_OTHER) {
if (index == 1 /* Port */ && len == /* XXX >=? */
sizeof(usb_port_status_t)) {
mutex_enter(&sc->sc_intr_lock);
slhci_get_status(sc, (usb_port_status_t *)
buf);
mutex_exit(&sc->sc_intr_lock);
actlen = sizeof(usb_port_status_t);
error = USBD_NORMAL_COMPLETION;
} else
DLOG(D_ROOT, "Get Port Status index = %#.4jx "
"len = %#.4jx", index, len, 0,0);
} else if (type == UT_READ_CLASS_DEVICE) { /* XXX index? */
if (len == sizeof(usb_hub_status_t)) {
DLOG(D_ROOT, "Get Hub Status",
0,0,0,0);
actlen = sizeof(usb_hub_status_t);
memset(buf, 0, actlen);
error = USBD_NORMAL_COMPLETION;
} else
DLOG(D_ROOT, "Get Hub Status bad len %#.4jx",
len, 0,0,0);
}
break;
case UR_GET_DESCRIPTOR:
if (type == UT_READ_DEVICE) {
/* value is type (&0xff00) and index (0xff) */
if (value == (UDESC_DEVICE<<8)) {
actlen = buflen;
error = USBD_NORMAL_COMPLETION;
} else if (value == (UDESC_CONFIG<<8)) {
struct usb_roothub_descriptors confd;
r = slhci_read(ssc, SL11_E0CTRL);
DDOLOG("USB A Host Control = %#.2x", r, 0, 0, 0);
DDOLOGEPCTRL(r);
aaddr = slhci_read(ssc, SL11_E0ADDR);
DDOLOG("USB A Base Address = %u", aaddr, 0,0,0);
alen = slhci_read(ssc, SL11_E0LEN);
DDOLOG("USB A Length = %u", alen, 0,0,0);
r = slhci_read(ssc, SL11_E0STAT);
DDOLOG("USB A Status = %#.2x", r, 0,0,0);
DDOLOGEPSTAT(r);
r = slhci_read(ssc, SL11_E0CONT);
DDOLOG("USB A Remaining or Overflow Length = %u", r, 0,0,0);
r = slhci_read(ssc, SL11_E1CTRL);
DDOLOG("USB B Host Control = %#.2x", r, 0,0,0);
DDOLOGEPCTRL(r);
baddr = slhci_read(ssc, SL11_E1ADDR);
DDOLOG("USB B Base Address = %u", baddr, 0,0,0);
blen = slhci_read(ssc, SL11_E1LEN);
DDOLOG("USB B Length = %u", blen, 0,0,0);
r = slhci_read(ssc, SL11_E1STAT);
DDOLOG("USB B Status = %#.2x", r, 0,0,0);
DDOLOGEPSTAT(r);
r = slhci_read(ssc, SL11_E1CONT);
DDOLOG("USB B Remaining or Overflow Length = %u", r, 0,0,0);
r = slhci_read(ssc, SL11_CTRL);
DDOLOG("Control = %#.2x", r, 0,0,0);
DDOLOGCTRL(r);
