/*
* Copyright (c) 2000, 2001 Ben Harris
* Copyright (c) 1995-1998 Mark Brinicombe
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* seeq8005.c - SEEQ 8005 device driver
*/
/*
* This driver currently supports the following chips:
* SEEQ 8005 Advanced Ethernet Data Link Controller
* SEEQ 80C04 Ethernet Data Link Controller
* SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller
*/
/*
* More information on the 8004 and 8005 AEDLC controllers can be found in
* the SEEQ Technology Inc 1992 Data Comm Devices data book.
*
* This data book may no longer be available as these are rather old chips
* (1991 - 1993)
*/
/*
* This driver is based on the arm32 ea(4) driver, hence the names of many
* of the functions.
*/
/*
* Bugs/possible improvements:
* - Does not currently support DMA
* - Does not transmit multiple packets in one go
* - Does not support 8-bit busses
*/
ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID);
id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN);
switch (id & SEEQ_PRODUCTID_MASK) {
case SEEQ_PRODUCTID_8004:
sc->sc_variant = SEEQ_8004;
switch (id & SEEQ_PRODUCTID_REV_MASK) {
case SEEQ_PRODUCTID_REV_80C04:
printf(", SEEQ 80C04\n");
break;
case SEEQ_PRODUCTID_REV_80C04A:
printf(", SEEQ 80C04A\n");
break;
default:
/* Unknown SEEQ 8004 variants */
printf(", SEEQ 8004 rev %x\n",
id & SEEQ_PRODUCTID_REV_MASK);
break;
}
break;
default: /* XXX */
sc->sc_variant = SEEQ_8005;
printf(", SEEQ 8005\n");
break;
}
/* Both the 8004 and 8005 are designed for 64K Buffer memory */
sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE;
/*
* Set up tx and rx buffers.
*
* We set aside EA_TX_BUFFER_SIZE * EA_TX_BUFFER_COUNT for TX
* buffers and the rest for RX buffers
*/
sc->sc_tx_bufs = EA_TX_BUFFER_COUNT;
sc->sc_tx_bufsize = sc->sc_tx_bufs * EA_TX_BUFFER_SIZE;
sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize;
sc->sc_enabled = 0;
/*
* This can be called before we know whether the chip is in 8- or
* 16-bit mode, so we do a reset in both modes. The 16-bit reset is
* harmless in 8-bit mode, so we do that second.
*/
/* In 16-bit mode, this will munge the PreamSelect bit. */
bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8);
delay(4);
/* In 8-bit mode, this will zero the bottom half of config reg 2. */
bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET);
delay(4);
/*
* If the DMA FIFO's in write mode, wait for it to empty. Needed when
* switching the FIFO from write to read. We also use it when changing
* the address for writes.
*/
static void
ea_await_fifo_empty(struct seeq8005_softc *sc)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int timeout;
timeout = 20000;
if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) &
SEEQ_STATUS_FIFO_DIR) != 0)
return; /* FIFO is reading anyway. */
while (--timeout > 0)
if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) &
SEEQ_STATUS_FIFO_EMPTY)
return;
log(LOG_ERR, "%s: DMA FIFO failed to empty\n",
device_xname(sc->sc_dev));
}
/*
* Wait for the DMA FIFO to fill before reading from it.
*/
static void
ea_await_fifo_full(struct seeq8005_softc *sc)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int timeout;
timeout = 20000;
while (--timeout > 0)
if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) &
SEEQ_STATUS_FIFO_FULL)
return;
log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(sc->sc_dev));
}
/*
* write to the buffer memory on the interface
*
* The buffer address is set to ADDR.
* If len != 0 then data is copied from the address starting at buf
* to the interface buffer.
* BUF must be usable as a uint16_t *.
* If LEN is odd, it must be safe to overwrite one extra byte.
*/
#ifdef DIAGNOSTIC
if (__predict_false(!ALIGNED_POINTER(buf, uint16_t)))
panic("%s: unaligned writebuf", device_xname(sc->sc_dev));
if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE))
panic("%s: writebuf out of range", device_xname(sc->sc_dev));
#endif
if (len > 0) {
if (sc->sc_flags & SF_8BIT)
bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN,
(uint8_t *)buf, len);
else
bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN,
/* LINTED: alignment checked above */
(uint16_t *)buf, len / 2);
}
if (!(sc->sc_flags & SF_8BIT) && len % 2) {
/* Write the last byte */
bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]);
}
/* Leave FIFO to empty in the background */
}
/*
* read from the buffer memory on the interface
*
* The buffer address is set to ADDR.
* If len != 0 then data is copied from the interface buffer to the
* address starting at buf.
* BUF must be usable as a uint16_t *.
* If LEN is odd, it must be safe to overwrite one extra byte.
*/
#ifdef DIAGNOSTIC
if (__predict_false(!ALIGNED_POINTER(buf, uint16_t)))
panic("%s: unaligned readbuf", device_xname(sc->sc_dev));
if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE))
panic("%s: readbuf out of range", device_xname(sc->sc_dev));
#endif
if (addr != -1) {
/*
* SEEQ 80C04 bug:
* Starting reading from certain addresses seems to cause
* us to get bogus results, so we avoid them.
*/
runup = 0;
if (sc->sc_variant == SEEQ_8004 &&
((addr & 0x00ff) == 0x00ea ||
(addr & 0x00ff) == 0x00ee ||
(addr & 0x00ff) == 0x00f0))
runup = (addr & 0x00ff) - 0x00e8;
ea_await_fifo_empty(sc);
ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
/*
* 80C04 bug workaround. I found this in the old arm32 "eb"
* driver. I've no idea what it does, but it seems to stop
* the chip mangling data so often.
*/
SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
sc->sc_command | SEEQ_CMD_FIFO_WRITE);
ea_await_fifo_empty(sc);
/*
* Start output on interface. Get datagrams from the queue and output them,
* giving the receiver a chance between datagrams. Call only from splnet or
* interrupt level!
*/
s = splnet();
DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n"));
/*
* Don't do anything if output is active. seeq8005intr() will call
* us (actually ea_txpacket()) back when the card's ready for more
* frames.
*/
if (ifp->if_flags & IFF_OACTIVE) {
splx(s);
return;
}
/* Mark interface as output active */
ifp->if_flags |= IFF_OACTIVE;
/* tx packets */
ea_txpacket(sc);
splx(s);
}
/*
* Transfer a packet to the interface buffer and start transmission
*
* Called at splnet()
*/
/*
* Copy a packet from an mbuf to the transmit buffer on the card.
*
* Puts a valid Tx header at the start of the packet, and a null header at
* the end.
*/
static int
ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart)
{
struct mbuf *m;
int len, nextpacket;
uint8_t hdr[4];
/*
* Copy the datagram to the packet buffer.
*/
len = 0;
for (m = m0; m; m = m->m_next) {
if (m->m_len == 0)
continue;
ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len,
m->m_len);
len += m->m_len;
}
if (len < ETHER_MIN_LEN) {
ea_writebuf(sc, padbuf, bufstart + 4 + len,
ETHER_MIN_LEN - len);
len = ETHER_MIN_LEN;
}
/* Follow it with a NULL packet header */
memset(hdr, 0, 4);
ea_writebuf(sc, hdr, bufstart + 4 + len, 4);
/* Ok we now have a packet len bytes long in our packet buffer */
DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len));
/* Write the packet header */
nextpacket = bufstart + len + 4;
hdr[0] = (nextpacket >> 8) & 0xff;
hdr[1] = nextpacket & 0xff;
hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS |
SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT;
hdr[3] = 0; /* Status byte -- will be updated by hardware. */
ea_writebuf(sc, hdr, bufstart, 4);
return len;
}
/*
* Ethernet controller interrupt.
*/
int
seeq8005intr(void *arg)
{
struct seeq8005_softc *sc = arg;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int status, handled;
handled = 0;
/* Get the controller status */
status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS);
/*
* If SEEQ_TXSTAT_COLLISION is set then we received at least
* one collision. On the 8004 we can find out exactly how many
* collisions occurred.
*
* The SEEQ_PKTSTAT_DONE will be set if the transmission has
* completed.
*
* If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions
* occurred and the packet transmission was aborted.
* This situation is untested as present.
*
* The SEEQ_TXSTAT_BABBLE is untested as it should only be set
* when we deliberately transmit oversized packets (e.g. for
* 802.1Q).
*/
if (txstatus & SEEQ_TXSTAT_COLLISION) {
switch (sc->sc_variant) {
case SEEQ_8004: {
int colls;
/*
* The 8004 contains a 4 bit collision count
* in the status register.
*/
#if 0
/* This appears to be broken on 80C04.AE */
if_statadd(ifp, if_collisions,
(txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT)
& SEEQ_TXSTAT_COLLISION_MASK;
#endif
/* Use the TX Collision register */
ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS);
colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN);
if_statadd(ifp, if_collisions, colls);
break;
}
case SEEQ_8005:
/* We known there was at least 1 collision */
if_statinc(ifp, if_collisions);
break;
}
} else if (txstatus & SEEQ_TXSTAT_COLLISION16) {
printf("seeq_intr: col16 %x\n", txstatus);
if_statadd2(ifp, if_collisions, 16, if_oerrors, 1);
}
/* Have we completed transmission on the packet ? */
if (txstatus & SEEQ_PKTSTAT_DONE) {
/* Clear watchdog timer. */
ifp->if_timer = 0;
ifp->if_flags &= ~IFF_OACTIVE;
/* Update stats */
if_statinc(ifp, if_opackets);
/* Tx next packet */
ea_txpacket(sc);
}
}
static void
ea_rxint(struct seeq8005_softc *sc)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
u_int addr;
int len;
int ctrl;
int ptr;
int status;
uint8_t rxhdr[4];
struct ifnet *ifp;
ifp = &sc->sc_ethercom.ec_if;
/* We start from the last rx pointer position */
addr = sc->sc_rx_ptr;
sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT;
SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
/* Zero packet ptr ? then must be null header so exit */
if (ptr == 0) break;
/* Sanity-check the next-packet pointer and flags. */
if (__predict_false(ptr < sc->sc_tx_bufsize ||
(ctrl & SEEQ_PKTCMD_TX))) {
if_statinc(ifp, if_ierrors);
log(LOG_ERR,
"%s: Rx chain corrupt at %04x (ptr = %04x)\n",
device_xname(sc->sc_dev), addr, ptr);
ea_init(ifp);
return;
}
/* Get packet length */
len = (ptr - addr) - 4;
if (len < 0)
len += sc->sc_rx_bufsize;
DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len));
/* Has the packet rx completed ? if not then exit */
if ((status & SEEQ_PKTSTAT_DONE) == 0)
break;
/*
* Did we have any errors? then note error and go to
* next packet
*/
if (__predict_false(status &
(SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR |
SEEQ_RXSTAT_SHORT_FRAME))) {
if_statinc(ifp, if_ierrors);
log(LOG_WARNING,
"%s: rx packet error at %04x (err=%02x)\n",
device_xname(sc->sc_dev), addr, status & 0x0f);
/* XXX shouldn't need to reset if it's genuine. */
ea_init(ifp);
return;
}
/*
* Is the packet too big? We allow slightly oversize packets
* for vlan(4) and tcpdump purposes, but the rest of the world
* wants incoming packets in a single mbuf cluster.
*/
if (__predict_false(len > MCLBYTES)) {
if_statinc(ifp, if_ierrors);
log(LOG_ERR,
"%s: rx packet size error at %04x (len=%d)\n",
device_xname(sc->sc_dev), addr, len);
ea_init(ifp);
return;
}
/* Pass data up to upper levels. */
ea_read(sc, addr + 4, len);
/* Store new rx pointer */
sc->sc_rx_ptr = addr;
SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8);
/* Make sure the receiver is on */
SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
sc->sc_command | SEEQ_CMD_RX_ON);
}
/*
* Pass a packet up to the higher levels.
*/
static void
ea_read(struct seeq8005_softc *sc, int addr, int len)
{
struct mbuf *m;
struct ifnet *ifp;
ifp = &sc->sc_ethercom.ec_if;
/* Pull packet off interface. */
m = ea_get(sc, addr, len, ifp);
if (m == NULL)
return;
if_percpuq_enqueue(ifp->if_percpuq, m);
}
/*
* Pull read data off a interface. Len is length of data, with local net
* header stripped. We copy the data into mbufs. When full cluster sized
* units are present we copy into clusters.
*/
struct mbuf *
ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp)
{
struct mbuf *top, **mp, *m;
int len;
u_int cp, epkt;
/*
* Set up multicast address filter by passing all multicast addresses
* through a crc generator, and then using bits 2 - 7 as an index
* into the 64 bit logical address filter. The high order bits
* selects the word, while the rest of the bits select the bit within
* the word.
*/
if (ifp->if_flags & IFF_PROMISC) {
ifp->if_flags |= IFF_ALLMULTI;
for (i = 0; i < 8; i++)
af[i] = 0xff;
return;
}
for (i = 0; i < 8; i++)
af[i] = 0;
ETHER_LOCK(ec);
ETHER_FIRST_MULTI(step, ec, enm);
while (enm != NULL) {
if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
sizeof(enm->enm_addrlo)) != 0) {
/*
* We must listen to a range of multicast addresses.
* For now, just accept all multicasts, rather than
* trying to set only those filter bits needed to match
* the range. (At this time, the only use of address
* ranges is for IP multicast routing, for which the
* range is big enough to require all bits set.)
*/
ifp->if_flags |= IFF_ALLMULTI;
for (i = 0; i < 8; i++)
af[i] = 0xff;
break;
}