/*
*
* Copyright (C) 2001 Eduardo Horvath.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _IF_GEMVAR_H
#define _IF_GEMVAR_H
#include <sys/queue.h>
#include <sys/callout.h>
#include <sys/rndsource.h>
/*
* Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
*/
/*
* Transmit descriptor list size. This is arbitrary, but allocate
* enough descriptors for 64 pending transmissions and 16 segments
* per packet.
*/
#define GEM_NTXSEGS 16
/*
* Receive descriptor list size. We have one Rx buffer per incoming
* packet, so this logic is a little simpler.
*/
#define GEM_NRXDESC 128
#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
#define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK)
#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
/*
* Control structures are DMA'd to the GEM chip. We allocate them in
* a single clump that maps to a single DMA segment to make several things
* easier.
*/
struct gem_control_data {
/*
* The transmit descriptors.
*/
struct gem_desc gcd_txdescs[GEM_NTXDESC];
/*
* The receive descriptors.
*/
struct gem_desc gcd_rxdescs[GEM_NRXDESC];
};
/*
* Software state for transmit jobs.
*/
struct gem_txsoft {
struct mbuf *txs_mbuf; /* head of our mbuf chain */
bus_dmamap_t txs_dmamap; /* our DMA map */
int txs_firstdesc; /* first descriptor in packet */
int txs_lastdesc; /* last descriptor in packet */
int txs_ndescs; /* number of descriptors */
SIMPLEQ_ENTRY(gem_txsoft) txs_q;
};
SIMPLEQ_HEAD(gem_txsq, gem_txsoft);
/*
* Software state for receive jobs.
*/
struct gem_rxsoft {
struct mbuf *rxs_mbuf; /* head of our mbuf chain */
bus_dmamap_t rxs_dmamap; /* our DMA map */
};
/*
* Software state per device.
*/
struct gem_softc {
device_t sc_dev; /* generic device information */
struct ethercom sc_ethercom; /* ethernet common data */
struct mii_data sc_mii; /* MII media control */
struct callout sc_tick_ch; /* tick callout */
struct callout sc_rx_watchdog; /* RX watchdog callout */
/* The following bus handles are to be provided by the bus front-end */
bus_space_tag_t sc_bustag; /* bus tag */
bus_dma_tag_t sc_dmatag; /* bus dma tag */
bus_dmamap_t sc_dmamap; /* bus dma handle */
bus_space_handle_t sc_h1; /* bus space handle for bank 1 regs */
bus_space_handle_t sc_h2; /* bus space handle for bank 2 regs */
bus_size_t sc_size; /* bank 1 size */
int sc_phys[2]; /* MII instance -> PHY map */
int sc_mif_config; /* Selected MII reg setting */
uint32_t sc_mii_anar; /* copy of PCS GEM_MII_ANAR register */
int sc_mii_media; /* Media selected for PCS MII */
u_int sc_variant; /* which GEM are we dealing with? */
#define GEM_UNKNOWN 0 /* don't know */
#define GEM_SUN_GEM 1 /* Sun GEM variant */
#define GEM_SUN_ERI 2 /* Sun ERI variant */
#define GEM_APPLE_GMAC 3 /* Apple GMAC variant */
#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
u_int sc_flags; /* */
u_short sc_if_flags; /* copy of ifp->if_flags */
#define GEM_GIGABIT 0x0001 /* has a gigabit PHY */
#define GEM_LINK 0x0002 /* link is up */
#define GEM_PCI 0x0004 /* XXX PCI busses are little-endian */
#define GEM_SERDES 0x0008 /* use the SERDES */
#define GEM_SERIAL 0x0010 /* use the serial link */
/*
* Ring buffer DMA stuff.
*/
bus_dma_segment_t sc_cdseg; /* control data memory */
int sc_cdnseg; /* number of segments */
bus_dmamap_t sc_cddmamap; /* control data DMA map */
#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
bus_dmamap_t sc_nulldmamap; /* for small packets padding */
/*
* Software state for transmit and receive descriptors.
*/
struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
/*
* Control data structures.
*/
struct gem_control_data *sc_control_data;
#define sc_txdescs sc_control_data->gcd_txdescs
#define sc_rxdescs sc_control_data->gcd_rxdescs
int sc_txfree; /* number of free Tx descriptors */
int sc_txnext; /* next ready Tx descriptor */
int sc_txwin; /* Tx descriptors since last Tx int */
