/*
* Copyright (c) 2009 Paul Fleischer
* All rights reserved.
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* based on sys/dev/ic/cs89x0.c */
/*
* Copyright (c) 2004 Christopher Gilbert
* All rights reserved.
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Copyright 1997
* Digital Equipment Corporation. All rights reserved.
*
* This software is furnished under license and may be used and
* copied only in accordance with the following terms and conditions.
* Subject to these conditions, you may download, copy, install,
* use, modify and distribute this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce
* and retain this copyright notice and list of conditions as
* they appear in the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Digital Equipment Corporation. Neither the "Digital Equipment
* Corporation" name nor any trademark or logo of Digital Equipment
* Corporation may be used to endorse or promote products derived
* from this software without the prior written permission of
* Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied
* warranties, including but not limited to, any implied warranties
* of merchantability, fitness for a particular purpose, or
* non-infringement are disclaimed. In no event shall DIGITAL be
* liable for any damages whatsoever, and in particular, DIGITAL
* shall not be liable for special, indirect, consequential, or
* incidental damages or damages for lost profits, loss of
* revenue or loss of use, whether such damages arise in contract,
* negligence, tort, under statute, in equity, at law or otherwise,
* even if advised of the possibility of such damage.
*/
#ifdef DM9000_DEBUG
#define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
#else
#define DPRINTF(s) do {} while (/*CONSTCOND*/0)
#endif
#ifdef DM9000_TX_DEBUG
#define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
#else
#define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0)
#endif
#ifdef DM9000_RX_DEBUG
#define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
#else
#define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0)
#endif
#ifdef DM9000_RX_DATA_DEBUG
#define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
#else
#define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0)
#endif
#ifdef DM9000_TX_DATA_DEBUG
#define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
#else
#define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0)
#endif
/* TODO: Check the vendor ID as well */
if (sc->sc_product_id != 0x9000) {
panic("dme_attach: product id mismatch (0x%hx != 0x9000)",
sc->sc_product_id);
}
#if 1 || DM9000_DEBUG
{
dme_read_c(sc, DM9000_PAB0, enaddr, 6);
aprint_normal_dev(sc->sc_dev,
"DM9000 was configured with MAC address: %s\n",
ether_sprintf(enaddr));
}
#endif
dict = device_properties(sc->sc_dev);
ea = (dict) ? prop_dictionary_get(dict, "mac-address") : NULL;
if (ea != NULL) {
/*
* If the MAC address is overridden by a device property,
* use that.
*/
KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
memcpy(enaddr, prop_data_value(ea), ETHER_ADDR_LEN);
aprint_debug_dev(sc->sc_dev, "got MAC address!\n");
} else {
/*
* If we did not get an externally configure address,
* try to read one from the current setup, before
* resetting the chip.
*/
dme_read_c(sc, DM9000_PAB0, enaddr, 6);
if (ETHER_IS_ONE(enaddr) || ETHER_IS_ZERO(enaddr)) {
/* make a random MAC address */
uint32_t maclo = 0x00f2 | (cprng_strong32() << 16);
uint32_t machi = cprng_strong32();
enaddr[0] = maclo;
enaddr[1] = maclo >> 8;
enaddr[2] = maclo >> 16;
enaddr[3] = maclo >> 26;
enaddr[4] = machi;
enaddr[5] = machi >> 8;
}
}
/* TODO: perform explicit EEPROM read op if it's available */
/* might be unnecessary as link change interrupt works well */
callout_init(&sc->sc_link_callout, 0);
callout_setfunc(&sc->sc_link_callout, phy_tick, sc);
/* frame body read/write ops in 2 byte quantity or byte-wise. */
DPRINTF(("DM9000 Operation Mode: "));
switch (io_mode) {
case DM9000_MODE_8BIT:
DPRINTF(("8-bit mode"));
sc->sc_data_width = 1;
sc->sc_pkt_write = pkt_write_1;
sc->sc_pkt_read = pkt_read_1;
break;
case DM9000_MODE_16BIT:
DPRINTF(("16-bit mode"));
sc->sc_data_width = 2;
sc->sc_pkt_write = pkt_write_2;
sc->sc_pkt_read = pkt_read_2;
break;
case DM9000_MODE_32BIT:
DPRINTF(("32-bit mode"));
sc->sc_data_width = 4;
panic("32bit mode is unsupported\n");
break;
default:
DPRINTF(("Invalid mode"));
break;
}
DPRINTF(("\n"));
return 0;
}
int
dme_detach(struct dme_softc *sc)
{
return 0;
}
/* Software Initialize/Reset of the DM9000 */
static void
dme_reset(struct dme_softc *sc)
{
uint8_t misc;
/* We only re-initialized the PHY in this function the first time it is
* called. */
if (!sc->sc_phy_initialized) {
/* PHY Reset */
mii_writereg(sc->sc_dev, 1, MII_BMCR, BMCR_RESET);
/* PHY Power Down */
misc = dme_read(sc, DM9000_GPR);
dme_write(sc, DM9000_GPR, misc | DM9000_GPR_PHY_PWROFF);
}
/* Reset the DM9000 twice, as described in section 2 of the Programming
* Guide.
* The PHY is initialized and enabled between those two resets.
*/
ETHER_LOCK(ec);
if (ifp->if_flags & IFF_PROMISC) {
ec->ec_flags |= ETHER_F_ALLMULTI;
ETHER_UNLOCK(ec);
/* run promisc. mode */
rcr |= DM9000_RCR_PRMSC;
goto update;
}
ec->ec_flags &= ~ETHER_F_ALLMULTI;
ETHER_FIRST_MULTI(step, ec, enm);
while (enm != NULL) {
if (memcpy(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
/*
* We must listen to a range of multicast addresses.
* For now, just accept all multicasts, rather than
* trying to set only those filter bits needed to match
* the range. (At this time, the only use of address
* ranges is for IP multicast routing, for which the
* range is big enough to require all bits set.)
*/
ec->ec_flags |= ETHER_F_ALLMULTI;
ETHER_UNLOCK(ec);
memset(mchash, 0xff, sizeof(mchash)); /* necessary? */
/* accept all multicast frame */
rcr |= DM9000_RCR_ALL;
goto update;
}
h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f;
/* 3(5:3) and 3(2:0) sampling to have uint8_t[8] */
mchash[h / 8] |= 1 << (h % 8);
ETHER_NEXT_MULTI(step, enm);
}
ETHER_UNLOCK(ec);
/* DM9000 receive filter is always on */
mchash[7] |= 0x80; /* to catch bcast frame */
update:
dme_write_c(sc, DM9000_MAB0, mchash, sizeof(mchash));
dme_write(sc, DM9000_RCR, rcr | DM9000_RCR_RXEN);
return;
}
/* Not quite sure what to do when called with disable == 0 */
if (disable) {
/* Disable RX */
dme_write(sc, DM9000_RCR, 0x0);
}
mii_down(&sc->sc_mii);
callout_stop(&sc->sc_link_callout);
if ((ifp->if_flags & IFF_RUNNING) == 0) {
return;
}
if (!sc->txready) {
dme_prepare(ifp);
}
if (sc->txbusy) {
/*
* We need to wait until the current frame has
* been transmitted.
*/
return;
}
if (sc->txready) {
/* We are ready to transmit right away */
dme_transmit(ifp);
}
dme_prepare(ifp); /* Prepare next one */
}
/* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */
static void
dme_prepare(struct ifnet *ifp)
{
struct dme_softc *sc = ifp->if_softc;
uint16_t length;
struct mbuf *m;
KASSERT(!sc->txready);
IFQ_DEQUEUE(&ifp->if_snd, m);
if (m == NULL) {
TX_DPRINTF(("dme_prepare: Nothing to transmit\n"));
return; /* Nothing to transmit */
}
/* Element has now been removed from the queue, so we better send it */
bpf_mtap(ifp, m, BPF_D_OUT);
/* Setup the DM9000 to accept the writes, and then write each buf in
the chain. */
/* frame has just arrived, retrieve it */
/* called right after Rx frame available interrupt */
do {
/* "no increment" read to get the avail byte without
moving past it. */
bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io,
DM9000_MRCMDX);
/* Read twice */
avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
avail &= 03; /* 1:0 we only want these bits */
if (avail == 01) {
/* Read with address increment. */
bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io,
DM9000_MRCMD);
rsr = PKT_READ(sc, &m);
if (m == NULL) {
/* failed to allocate a receive buffer */
RX_DPRINTF(("dme_receive: "
"Error allocating buffer\n"));
if_statinc(ifp, if_ierrors);
continue;
}
if (rsr & (DM9000_RSR_CE | DM9000_RSR_PLE)) {
/* Error while receiving the frame,
* discard it and keep track of counters
*/
RX_DPRINTF(("dme_receive: "
"Error reciving frame\n"));
if_statinc(ifp, if_ierrors);
continue;
}
if (rsr & DM9000_RSR_LCS) {
if_statinc(ifp, if_collisions);
continue;
}
/* pick and forward this frame to ifq */
if_percpuq_enqueue(ifp->if_percpuq, m);
} else if (avail != 00) {
/* Should this be logged somehow? */
printf("%s: Resetting chip\n",
device_xname(sc->sc_dev));
dme_reset(sc);
break;
}
} while (avail == 01);
/* frame received successfully */
}
if (isr & DM9000_ISR_PRS) {
KASSERT(ifp->if_flags & IFF_RUNNING);
dme_receive(ifp);
}
if (isr & DM9000_ISR_LNKCHNG)
lnkchg(sc);
if (isr & DM9000_ISR_PTS) {
tsr = 0x01; /* Initialize to an error value */
/* A frame has been transmitted */
sc->txbusy = 0;
nsr = dme_read(sc, DM9000_NSR);
if (nsr & DM9000_NSR_TX1END) {
tsr = dme_read(sc, DM9000_TSR1);
TX_DPRINTF(("dme_intr: Sent using channel 0\n"));
} else if (nsr & DM9000_NSR_TX2END) {
tsr = dme_read(sc, DM9000_TSR2);
TX_DPRINTF(("dme_intr: Sent using channel 1\n"));
}
if (tsr == 0x0) {
/* Frame successfully sent */
if_statinc(ifp, if_opackets);
} else {
if_statinc(ifp, if_oerrors);
}
/* If we have nothing ready to transmit, prepare something */
if (!sc->txready)
dme_prepare(ifp);
m_set_rcvif(m, ifp);
/* Ensure that we always allocate an even number of
* bytes in order to avoid writing beyond the buffer
*/
m->m_pkthdr.len = frame_length + (frame_length % quantum);
pad = ALIGN(sizeof(struct ether_header)) -
sizeof(struct ether_header);
/* All our frames have the CRC attached */
m->m_flags |= M_HASFCS;
if (m->m_pkthdr.len + pad > MHLEN) {
MCLGET(m, M_DONTWAIT);
if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
return NULL;
}
}
static int
pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain)
{
int left_over_count = 0; /* Number of bytes from previous mbuf, which
need to be written with the next.*/
uint16_t left_over_buf = 0;
int length = 0;
struct mbuf *buf;
uint8_t *write_ptr;
/* We expect that the DM9000 has been setup to accept writes before
this function is called. */
for (buf = bufChain; buf != NULL; buf = buf->m_next) {
int to_write = buf->m_len;
length += to_write;
write_ptr = buf->m_data;
while (to_write > 0 ||
(buf->m_next == NULL && left_over_count > 0)) {
if (left_over_count > 0) {
uint8_t b = 0;
DPRINTF(("pkt_write_16: "
"Writing left over byte\n"));
if (to_write > 0) {
b = *write_ptr;
to_write--;
write_ptr++;
DPRINTF(("Took single byte\n"));
} else {
DPRINTF(("Leftover in last run\n"));
length++;
}
/* Does shift direction depend on endianness? */
left_over_buf = left_over_buf | (b << 8);
/* A block of aligned data. */
for (i = 0; i < to_write / 2; i++) {
/* buf will be half-word aligned
* all the time
*/
bus_space_write_2(sc->sc_iot,
sc->sc_ioh, sc->dme_data, *dptr);
TX_DATA_DPRINTF(("%02X %02X ",
*dptr & 0xFF, (*dptr >> 8) & 0xFF));
dptr++;
}
write_ptr += i * 2;
if (to_write % 2 != 0) {
DPRINTF(("pkt_write_16: "
"to_write %% 2: %d\n",
to_write % 2));
left_over_count = 1;
/* XXX: Does this depend on
* the endianness?
*/
left_over_buf = *write_ptr;
write_ptr++;
to_write--;
DPRINTF(("pkt_write_16: "
"to_write (after): %d\n",
to_write));
DPRINTF(("pkt_write_16: i * 2: %d\n",
i*2));
}
to_write -= i * 2;
}
} /* while (...) */
} /* for (...) */
data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data);
rx_status = data & 0xFF;
frame_length = bus_space_read_2(sc->sc_iot,
sc->sc_ioh, sc->dme_data);
if (frame_length > ETHER_MAX_LEN) {
printf("Got frame of length: %d\n", frame_length);
printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN);
panic("Something is rotten");
}
RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n",
rx_status, frame_length));
m = dme_alloc_receive_buffer(ifp, frame_length);
if (m == NULL) {
/*
* didn't get a receive buffer, so we read the rest of the
* frame, throw it away and return an error
*/
for (i = 0; i < frame_length; i += 2) {
data = bus_space_read_2(sc->sc_iot,
sc->sc_ioh, sc->dme_data);
}
*outBuf = NULL;
return 0;
}
buf = mtod(m, uint16_t*);
RX_DPRINTF(("dme_receive: "));
for (i = 0; i < frame_length; i += 2) {
data = bus_space_read_2(sc->sc_iot,
sc->sc_ioh, sc->dme_data);
if ( (frame_length % 2 != 0) &&
(i == frame_length - 1) ) {
data = data & 0xff;
RX_DPRINTF((" L "));
}
*buf = data;
buf++;
RX_DATA_DPRINTF(("%02X %02X ", data & 0xff,
(data >> 8) & 0xff));
}
if (frame_length > ETHER_MAX_LEN) {
printf("Got frame of length: %d\n", frame_length);
printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN);
panic("Something is rotten");
}
RX_DPRINTF(("dme_receive: "
"rx_statux: 0x%x, frame_length: %d\n",
rx_status, frame_length));
m = dme_alloc_receive_buffer(ifp, frame_length);
if (m == NULL) {
/*
* didn't get a receive buffer, so we read the rest of the
* frame, throw it away and return an error
*/
for (i = 0; i < frame_length; i++ ) {
data = bus_space_read_2(sc->sc_iot,
sc->sc_ioh, sc->dme_data);
}
*outBuf = NULL;
return 0;
}
buf = mtod(m, uint8_t *);
RX_DPRINTF(("dme_receive: "));
for (i = 0; i< frame_length; i += 1) {
data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
*buf = data;
buf++;
RX_DATA_DPRINTF(("%02X ", data));
}
