/*
* Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by David Young.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Transmit descriptor list size. This is arbitrary, but allocate
* enough descriptors for 64 pending transmissions and 16 segments
* per packet. Since a descriptor holds 2 buffer addresses, that's
* 8 descriptors per packet. This MUST work out to a power of 2.
*/
#define ATW_NTXSEGS 16
/*
* Receive descriptor list size. We have one Rx buffer per incoming
* packet, so this logic is a little simpler.
*/
#define ATW_NRXDESC 64
#define ATW_NRXDESC_MASK (ATW_NRXDESC - 1)
#define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK)
/*
* Control structures are DMA'd to the ADM8211 chip. We allocate them in
* a single clump that maps to a single DMA segment to make several things
* easier.
*/
struct atw_control_data {
/*
* The transmit descriptors.
*/
struct atw_txdesc acd_txdescs[ATW_NTXDESC];
/*
* The receive descriptors.
*/
struct atw_rxdesc acd_rxdescs[ATW_NRXDESC];
};
#define ATW_CDOFF(x) offsetof(struct atw_control_data, x)
#define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)])
#define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)])
/*
* Software state for transmit jobs.
*/
struct atw_txsoft {
struct mbuf *txs_mbuf; /* head of our mbuf chain */
bus_dmamap_t txs_dmamap; /* our DMA map */
int txs_firstdesc; /* first descriptor in packet */
int txs_lastdesc; /* last descriptor in packet */
int txs_ndescs; /* number of descriptors */
struct ieee80211_duration txs_d0;
struct ieee80211_duration txs_dn;
SIMPLEQ_ENTRY(atw_txsoft) txs_q;
};
SIMPLEQ_HEAD(atw_txsq, atw_txsoft);
/*
* Software state for receive jobs.
*/
struct atw_rxsoft {
struct mbuf *rxs_mbuf; /* head of our mbuf chain */
bus_dmamap_t rxs_dmamap; /* our DMA map */
};
/*
* Table which describes the transmit threshold mode. We generally
* start at index 0. Whenever we get a transmit underrun, we increment
* our index, falling back if we encounter the NULL terminator.
*/
struct atw_txthresh_tab {
u_int32_t txth_opmode; /* OPMODE bits */
const char *txth_name; /* name of mode */
};
bus_space_tag_t sc_st; /* bus space tag */
bus_space_handle_t sc_sh; /* bus space handle */
bus_dma_tag_t sc_dmat; /* bus dma tag */
u_int32_t sc_cacheline; /* cache line size */
u_int32_t sc_maxburst; /* maximum burst length */
const struct atw_txthresh_tab *sc_txth;
int sc_txthresh; /* current tx threshold */
u_int sc_cur_chan; /* current channel */
int sc_flags;
u_int16_t *sc_srom;
u_int16_t sc_sromsz;
struct bpf_if * sc_radiobpf;
bus_dma_segment_t sc_cdseg; /* control data memory */
int sc_cdnseg; /* number of segments */
bus_dmamap_t sc_cddmamap; /* control data DMA map */
#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
/*
* Software state for transmit and receive descriptors.
*/
struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN];
struct atw_rxsoft sc_rxsoft[ATW_NRXDESC];
/*
* Control data structures.
*/
struct atw_control_data *sc_control_data;
#define sc_txdescs sc_control_data->acd_txdescs
#define sc_rxdescs sc_control_data->acd_rxdescs
#define sc_setup_desc sc_control_data->acd_setup_desc
int sc_txfree; /* number of free Tx descriptors */
int sc_txnext; /* next ready Tx descriptor */
int sc_ntxsegs; /* number of transmit segs per pkt */
/*
* Note we rely on MCLBYTES being a power of two. Because the `length'
* field is only 11 bits, we must subtract 1 from the length to avoid
* having it truncated to 0!
*/
static __inline void
atw_init_rxdesc(struct atw_softc *sc, int x)
{
struct atw_rxsoft *rxs = &sc->sc_rxsoft[x];
struct atw_rxdesc *rxd = &sc->sc_rxdescs[x];
struct mbuf *m = rxs->rxs_mbuf;
