/*
* Core definitions and data structures shareable across OS platforms.
*
* Copyright (c) 1994-2002 Justin T. Gibbs.
* Copyright (c) 2000-2002 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* Id: //depot/aic7xxx/aic7xxx/aic79xx.h#94 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.15 2003/06/28 04:45:25 gibbs Exp $
*/
/*
* Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
*/
#define AHD_COPY_SCB_COL_IDX(dst, src) \
do { \
dst->hscb->scsiid = src->hscb->scsiid; \
dst->hscb->lun = src->hscb->lun; \
} while (0)
#define AHD_NEVER_COL_IDX 0xFFFF
/**************************** Driver Constants ********************************/
/*
* The maximum number of supported targets.
*/
#define AHD_NUM_TARGETS 16
/*
* The maximum number of supported luns.
* The identify message only supports 64 luns in non-packetized transfers.
* You can have 2^64 luns when information unit transfers are enabled,
* but until we see a need to support that many, we support 256.
*/
#define AHD_NUM_LUNS_NONPKT 64
#define AHD_NUM_LUNS 256
/*
* The maximum transfer per S/G segment.
* Limited by MAXPHYS or a 24bit counter.
*/
#define AHD_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
/*
* The maximum amount of SCB storage in hardware on a controller.
* This value represents an upper bound. Due to software design,
* we may not be able to use this number.
*/
#define AHD_SCB_MAX 512
/*
* The maximum number of concurrent transactions supported per driver instance.
* Sequencer Control Blocks (SCBs) store per-transaction information.
*/
#define AHD_MAX_QUEUE AHD_SCB_MAX
/*
* Define the size of our QIN and QOUT FIFOs. They must be a power of 2
* in size and accommodate as many transactions as can be queued concurrently.
*/
#define AHD_QIN_SIZE AHD_MAX_QUEUE
#define AHD_QOUT_SIZE AHD_MAX_QUEUE
#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
/*
* The maximum amount of SCB storage we allocate in host memory.
*/
#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
/*
* Ring Buffer of incoming target commands.
* We allocate 256 to simplify the logic in the sequencer
* by using the natural wrap point of an 8bit counter.
*/
#define AHD_TMODE_CMDS 256
/* Reset line assertion time in us */
#define AHD_BUSRESET_DELAY 25
/******************* Chip Characteristics/Operating Settings *****************/
/*
* Chip Type
* The chip order is from least sophisticated to most sophisticated.
*/
typedef enum {
AHD_NONE = 0x0000,
AHD_CHIPID_MASK = 0x00FF,
AHD_AIC7901 = 0x0001,
AHD_AIC7902 = 0x0002,
AHD_AIC7901A = 0x0003,
AHD_PCI = 0x0100, /* Bus type PCI */
AHD_PCIX = 0x0200, /* Bus type PCIX */
AHD_BUS_MASK = 0x0F00
} ahd_chip;
/*
* Features available in each chip type.
*/
typedef enum {
AHD_FENONE = 0x00000,
AHD_WIDE = 0x00001,/* Wide Channel */
AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
AHD_RTI = 0x04000,/* Retained Training Support */
AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
AHD_AIC7901_FE = AHD_FENONE,
AHD_AIC7901A_FE = AHD_FENONE,
AHD_AIC7902_FE = AHD_MULTI_FUNC
} ahd_feature;
/*
* Bugs in the silicon that we work around in software.
*/
typedef enum {
AHD_BUGNONE = 0x0000,
/*
* Rev A hardware fails to update LAST/CURR/NEXTSCB
* correctly in certain packetized selection cases.
*/
AHD_SENT_SCB_UPDATE_BUG = 0x0001,
/* The wrong SCB is accessed to check the abort pending bit. */
AHD_ABORT_LQI_BUG = 0x0002,
/* Packetized bitbucket crosses packet boundaries. */
AHD_PKT_BITBUCKET_BUG = 0x0004,
/* The selection timer runs twice as long as its setting. */
AHD_LONG_SETIMO_BUG = 0x0008,
/* The Non-LQ CRC error status is delayed until phase change. */
AHD_NLQICRC_DELAYED_BUG = 0x0010,
/* The chip must be reset for all outgoing bus resets. */
AHD_SCSIRST_BUG = 0x0020,
/* Some PCIX fields must be saved and restored across chip reset. */
AHD_PCIX_CHIPRST_BUG = 0x0040,
/* MMAPIO is not functional in PCI-X mode. */
AHD_PCIX_MMAPIO_BUG = 0x0080,
/* Reads to SCBRAM fail to reset the discard timer. */
AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
/* Bug workarounds that can be disabled on non-PCIX busses. */
AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
| AHD_PCIX_MMAPIO_BUG
| AHD_PCIX_SCBRAM_RD_BUG,
/*
* LQOSTOP0 status set even for forced selections with ATN
* to perform non-packetized message delivery.
*/
AHD_LQO_ATNO_BUG = 0x0200,
/* FIFO auto-flush does not always trigger. */
AHD_AUTOFLUSH_BUG = 0x0400,
/* The CLRLQO registers are not self-clearing. */
AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
/* The PACKETIZED status bit refers to the previous connection. */
AHD_PKTIZED_STATUS_BUG = 0x1000,
/* "Short Luns" are not placed into outgoing LQ packets correctly. */
AHD_PKT_LUN_BUG = 0x2000,
/*
* Only the FIFO allocated to the non-packetized connection may
* be in use during a non-packetzied connection.
*/
AHD_NONPACKFIFO_BUG = 0x4000,
/*
* Writing to a DFF SCBPTR register may fail if concurrent with
* a hardware write to the other DFF SCBPTR register. This is
* not currently a concern in our sequencer since all chips with
* this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
* occur in non-packetized connections.
*/
AHD_MDFF_WSCBPTR_BUG = 0x8000,
/* SGHADDR updates are slow. */
AHD_REG_SLOW_SETTLE_BUG = 0x10000,
/*
* Changing the MODE_PTR coincident with an interrupt that
* switches to a different mode will cause the interrupt to
* be in the mode written outside of interrupt context.
*/
AHD_SET_MODE_BUG = 0x20000,
/* Non-packetized busfree revision does not work. */
AHD_BUSFREEREV_BUG = 0x40000,
/*
* Paced transfers are indicated with a non-standard PPR
* option bit in the neg table, 160MHz is indicated by
* sync factor 0x7, and the offset if off by a factor of 2.
*/
AHD_PACED_NEGTABLE_BUG = 0x80000,
/* LQOOVERRUN false positives. */
AHD_LQOOVERRUN_BUG = 0x100000,
/*
* Controller write to INTSTAT will lose to a host
* write to CLRINT.
*/
AHD_INTCOLLISION_BUG = 0x200000,
/*
* The GEM318 violates the SCSI spec by not waiting
* the mandated bus settle delay between phase changes
* in some situations. Some aic79xx chip revs. are more
* strict in this regard and will treat REQ assertions
* that fall within the bus settle delay window as
* glitches. This flag tells the firmware to tolerate
* early REQ assertions.
*/
AHD_EARLY_REQ_BUG = 0x400000,
/*
* The LED does not stay on long enough in packetized modes.
*/
AHD_FAINT_LED_BUG = 0x800000
} ahd_bug;
/*
* Configuration specific settings.
* The driver determines these settings by probing the
* chip/controller's configuration.
*/
typedef enum {
AHD_FNONE = 0x00000,
AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
AHD_USEDEFAULTS = 0x00004,/*
* For cards without an seeprom
* or a BIOS to initialize the chip's
* SRAM, we use the default target
* settings.
*/
AHD_SEQUENCER_DEBUG = 0x00008,
AHD_RESET_BUS_A = 0x00010,
AHD_EXTENDED_TRANS_A = 0x00020,
AHD_TERM_ENB_A = 0x00040,
AHD_SPCHK_ENB_A = 0x00080,
AHD_STPWLEVEL_A = 0x00100,
AHD_INITIATORROLE = 0x00200,/*
* Allow initiator operations on
* this controller.
*/
AHD_TARGETROLE = 0x00400,/*
* Allow target operations on this
* controller.
*/
AHD_RESOURCE_SHORTAGE = 0x00800,
AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
AHD_INT50_SPEEDFLEX = 0x02000,/*
* Internal 50pin connector
* sits behind an aic3860
*/
AHD_BIOS_ENABLED = 0x04000,
AHD_ALL_INTERRUPTS = 0x08000,
AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
AHD_CURRENT_SENSING = 0x40000,
AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
AHD_HP_BOARD = 0x100000,
AHD_RESET_POLL_ACTIVE = 0x200000,
AHD_UPDATE_PEND_CMDS = 0x400000,
AHD_RUNNING_QOUTFIFO = 0x800000,
AHD_HAD_FIRST_SEL = 0x1000000
} ahd_flag;
/*
* The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
* consists of a "hardware SCB" mirroring the fields available on the card
* and additional information the kernel stores for each transaction.
*
* To minimize space utilization, a portion of the hardware scb stores
* different data during different portions of a SCSI transaction.
* As initialized by the host driver for the initiator role, this area
* contains the SCSI cdb (or a pointer to the cdb) to be executed. After
* the cdb has been presented to the target, this area serves to store
* residual transfer information and the SCSI status byte.
* For the target role, the contents of this area do not change, but
* still serve a different purpose than for the initiator role. See
* struct target_data for details.
*/
/*
* Status information embedded in the shared portion of
* an SCB after passing the cdb to the target. The kernel
* driver will only read this data for transactions that
* complete abnormally.
*/
struct initiator_status {
uint32_t residual_datacnt; /* Residual in the current S/G seg */
uint32_t residual_sgptr; /* The next S/G for this transfer */
uint8_t scsi_status; /* Standard SCSI status byte */
};
struct target_status {
uint32_t residual_datacnt; /* Residual in the current S/G seg */
uint32_t residual_sgptr; /* The next S/G for this transfer */
uint8_t scsi_status; /* SCSI status to give to initiator */
uint8_t target_phases; /* Bitmap of phases to execute */
uint8_t data_phase; /* Data-In or Data-Out */
uint8_t initiator_tag; /* Initiator's transaction tag */
};
/*
* Initiator mode SCB shared data area.
* If the embedded CDB is 12 bytes or less, we embed
* the sense buffer address in the SCB. This allows
* us to retrieve sense information without interrupting
* the host in packetized mode.
*/
typedef uint32_t sense_addr_t;
#define MAX_CDB_LEN 16
#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
union initiator_data {
struct {
uint64_t cdbptr;
uint8_t cdblen;
} cdb_from_host;
uint8_t cdb[MAX_CDB_LEN];
struct {
uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
sense_addr_t sense_addr;
} cdb_plus_saddr;
};
/*
* Target mode version of the shared data SCB segment.
*/
struct target_data {
uint32_t spare[2];
uint8_t scsi_status; /* SCSI status to give to initiator */
uint8_t target_phases; /* Bitmap of phases to execute */
uint8_t data_phase; /* Data-In or Data-Out */
uint8_t initiator_tag; /* Initiator's transaction tag */
};
struct hardware_scb {
/*0*/ union {
union initiator_data idata;
struct target_data tdata;
struct initiator_status istatus;
struct target_status tstatus;
} shared_data;
/*
* A word about residuals.
* The scb is presented to the sequencer with the dataptr and datacnt
* fields initialized to the contents of the first S/G element to
* transfer. The sgptr field is initialized to the bus address for
* the S/G element that follows the first in the in core S/G array
* or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
* S/G entry for this transfer (single S/G element transfer with the
* first elements address and length preloaded in the dataptr/datacnt
* fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
* The SG_FULL_RESID flag ensures that the residual will be correctly
* noted even if no data transfers occur. Once the data phase is entered,
* the residual sgptr and datacnt are loaded from the sgptr and the
* datacnt fields. After each S/G element's dataptr and length are
* loaded into the hardware, the residual sgptr is advanced. After
* each S/G element is expired, its datacnt field is checked to see
* if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
* residual sg ptr and the transfer is considered complete. If the
* sequencer determines that there is a residual in the transfer, or
* there is non-zero status, it will set the SG_STATUS_VALID flag in
* sgptr and DMA the scb back into host memory. To summarize:
*
* Sequencer:
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
* or residual_sgptr does not have SG_LIST_NULL set.
*
* o We are transferring the last segment if residual_datacnt has
* the SG_LAST_SEG flag set.
*
* Host:
* o A residual can only have occurred if a completed scb has the
* SG_STATUS_VALID flag set. Inspection of the SCSI status field,
* the residual_datacnt, and the residual_sgptr field will tell
* for sure.
*
* o residual_sgptr and sgptr refer to the "next" sg entry
* and so may point beyond the last valid sg entry for the
* transfer.
*/
#define SG_PTR_MASK 0xFFFFFFF8
/*16*/ uint16_t tag; /* Reused by Sequencer. */
/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
/*19*/ uint8_t scsiid; /*
* Selection out Id
* Our Id (bits 0-3) Their ID (bits 4-7)
*/
/*20*/ uint8_t lun;
/*21*/ uint8_t task_attribute;
/*22*/ uint8_t cdb_len;
/*23*/ uint8_t task_management;
/*24*/ uint64_t dataptr;
/*32*/ uint32_t datacnt; /* Byte 3 is spare. */
/*36*/ uint32_t sgptr;
/*40*/ uint32_t hscb_busaddr;
/*44*/ uint32_t next_hscb_busaddr;
/********** Long lun field only downloaded for full 8 byte lun support ********/
/*48*/ uint8_t pkt_long_lun[8];
/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
/*56*/ uint8_t spare[8];
};
/************************ Kernel SCB Definitions ******************************/
/*
* Some fields of the SCB are OS dependent. Here we collect the
* definitions for elements that all OS platforms need to include
* in there SCB definition.
*/
/*
* Definition of a scatter/gather element as transferred to the controller.
* The aic7xxx chips only support a 24bit length. We use the top byte of
* the length to store additional address bits and a flag to indicate
* that a given segment terminates the transfer. This gives us an
* addressable range of 512GB on machines with 64bit PCI or with chips
* that can support dual address cycles on 32bit PCI buses.
*/
struct ahd_dma_seg {
uint32_t addr;
uint32_t len;
#define AHD_DMA_LAST_SEG 0x80000000
#define AHD_SG_HIGH_ADDR_MASK 0x7F000000
#define AHD_SG_LEN_MASK 0x00FFFFFF
};
/*
* The current state of this SCB.
*/
typedef enum {
SCB_FLAG_NONE = 0x00000,
SCB_TRANSMISSION_ERROR = 0x00001,/*
* We detected a parity or CRC
* error that has effected the
* payload of the command. This
* flag is checked when normal
* status is returned to catch
* the case of a target not
* responding to our attempt
* to report the error.
*/
SCB_OTHERTCL_TIMEOUT = 0x00002,/*
* Another device was active
* during the first timeout for
* this SCB so we gave ourselves
* an additional timeout period
* in case it was hogging the
* bus.
*/
SCB_DEVICE_RESET = 0x00004,
SCB_SENSE = 0x00008,
SCB_CDB32_PTR = 0x00010,
SCB_RECOVERY_SCB = 0x00020,
SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
SCB_ABORT = 0x00100,
SCB_ACTIVE = 0x00200,
SCB_TARGET_IMMEDIATE = 0x00400,
SCB_PACKETIZED = 0x00800,
SCB_EXPECT_PPR_BUSFREE = 0x01000,
SCB_PKT_SENSE = 0x02000,
SCB_CMDPHASE_ABORT = 0x04000,
SCB_ON_COL_LIST = 0x08000,
SCB_SILENT = 0x10000,/*
* Be quiet about transmission type
* errors. They are expected and we
* don't want to upset the user. This
* flag is typically used during DV.
*/
SCB_FREEZE_QUEUE = 0x20000,
SCB_REQUEUE = 0x40000,
} scb_flag;
struct scb_data {
/*
* TAILQ of lists of free SCBs grouped by device
* collision domains.
*/
struct scb_tailq free_scbs;
/*
* Per-device lists of SCBs whose tag ID would collide
* with an already active tag on the device.
*/
struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
/*
* SCBs that will not collide with any active device.
*/
struct scb_list any_dev_free_scb_list;
/*
* Mapping from tag to SCB.
*/
struct scb *scbindex[AHD_SCB_MAX];
int scbs_left; /* unallocated scbs in head map_node */
int sgs_left; /* unallocated sgs in head map_node */
int sense_left; /* unallocated sense in head map_node */
uint16_t numscbs;
uint16_t maxhscbs; /* Number of SCBs on the card */
uint8_t init_level; /*
* How far we've initialized
* this structure.
*/
};
/*
* Connection descriptor for select-in requests in target mode.
*/
struct target_cmd {
uint8_t scsiid; /* Our ID and the initiator's ID */
uint8_t identify; /* Identify message */
uint8_t bytes[22]; /*
* Bytes contains any additional message
* bytes terminated by 0xFF. The remainder
* is the cdb to execute.
*/
uint8_t cmd_valid; /*
* When a command is complete, the firmware
* will set cmd_valid to all bits set.
* After the host has seen the command,
* the bits are cleared. This allows us
* to just peek at host memory to determine
* if more work is complete. cmd_valid is on
* an 8 byte boundary to simplify setting
* it on aic7880 hardware which only has
* limited direct access to the DMA FIFO.
*/
uint8_t pad[7];
};
/*
* Number of events we can buffer up if we run out
* of immediate notify ccbs.
*/
#define AHD_TMODE_EVENT_BUFFER_SIZE 8
struct ahd_tmode_event {
uint8_t initiator_id;
uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
#define EVENT_TYPE_BUS_RESET 0xFF
uint8_t event_arg;
};
/*
* Per enabled lun target mode state.
* As this state is directly influenced by the host OS'es target mode
* environment, we let the OS module define it. Forward declare the
* structure here so we can store arrays of them, etc. in OS neutral
* data structures.
*/
#ifdef AHD_TARGET_MODE
struct ahd_tmode_lstate {
struct cam_path *path;
struct ccb_hdr_slist accept_tios;
struct ccb_hdr_slist immed_notifies;
struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
uint8_t event_r_idx;
uint8_t event_w_idx;
};
#else
struct ahd_tmode_lstate;
#endif
/******************** Transfer Negotiation Datastructures *********************/
#define AHD_TRANS_CUR 0x01 /* Modify current negotiation status */
#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
#define AHD_PERIOD_10MHz 0x19
/*
* Per-initiator current, goal and user transfer negotiation information. */
struct ahd_initiator_tinfo {
struct ahd_transinfo curr;
struct ahd_transinfo goal;
struct ahd_transinfo user;
};
/*
* Per enabled target ID state.
* Pointers to lun target state as well as sync/wide negotiation information
* for each initiator<->target mapping. For the initiator role we pretend
* that we are the target and the targets are the initiators since the
* negotiation is the same regardless of role.
*/
struct ahd_tmode_tstate {
struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
/*
* Per initiator state bitmasks.
*/
uint16_t auto_negotiate;/* Auto Negotiation Required */
uint16_t discenable; /* Disconnection allowed */
uint16_t tagenable; /* Tagged Queuing allowed */
};
/* Safe and valid period for async negotiations. */
#define AHD_ASYNC_XFER_PERIOD 0x44
/*
* In RevA, the synctable uses a 120MHz rate for the period
* factor 8 and 160MHz for the period factor 7. The 120MHz
* rate never made it into the official SCSI spec, so we must
* compensate when setting the negotiation table for Rev A
* parts.
*/
#define AHD_SYNCRATE_REVA_120 0x8
#define AHD_SYNCRATE_REVA_160 0x7
/***************************** Lookup Tables **********************************/
/*
* Phase -> name and message out response
* to parity errors in each phase table.
*/
struct ahd_phase_table_entry {
uint8_t phase;
uint8_t mesg_out; /* Message response to parity errors */
const char *phasemsg;
};
/************************** Serial EEPROM Format ******************************/
struct seeprom_config {
/*
* Per SCSI ID Configuration Flags
*/
uint16_t device_flags[16]; /* words 0-15 */
#define CFXFER 0x003F /* synchronous transfer rate */
#define CFXFER_ASYNC 0x3F
#define CFQAS 0x0040 /* Negotiate QAS */
#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
#define CFSTART 0x0100 /* send start unit SCSI command */
#define CFINCBIOS 0x0200 /* include in BIOS scan */
#define CFDISC 0x0400 /* enable disconnection */
#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
#define CFWIDEB 0x1000 /* wide bus device */
#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
/*
* Saved register window mode information
* used for restore on next unpause.
*/
ahd_mode saved_dst_mode;
ahd_mode saved_src_mode;
/*
* Platform specific data.
*/
struct ahd_platform_data *platform_data;
/*
* Bus specific device information.
*/
ahd_bus_intr_t bus_intr;
/*
* Target mode related state kept on a per enabled lun basis.
* Targets that are not enabled will have null entries.
* As an initiator, we keep one target entry for our initiator
* ID to store our sync/wide transfer settings.
*/
struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
char inited_target[AHD_NUM_TARGETS];
/*
* The black hole device responsible for handling requests for
* disabled luns on enabled targets.
*/
struct ahd_tmode_lstate *black_hole;
/*
* Device instance currently on the bus awaiting a continue TIO
* for a command that was not given the disconnect privilege.
*/
struct ahd_tmode_lstate *pending_device;
/*
* Cached version of the hs_mailbox so we can avoid
* pausing the sequencer during mailbox updates.
*/
uint8_t hs_mailbox;
/*
* Incoming and outgoing message handling.
*/
uint8_t send_msg_perror;
ahd_msg_flags msg_flags;
ahd_msg_type msg_type;
uint8_t msgout_buf[12];/* Message we are sending */
uint8_t msgin_buf[12];/* Message we are receiving */
u_int msgout_len; /* Length of message to send */
u_int msgout_index; /* Current index in msgout */
u_int msgin_index; /* Current index in msgin */
/*
* Mapping information for data structures shared
* between the sequencer and kernel.
*/
bus_dma_tag_t parent_dmat;
bus_dma_tag_t shared_data_dmat;
struct map_node shared_data_map;
int shared_data_size;
int sc_dmaflags;
/* Information saved through suspend/resume cycles */
struct ahd_suspend_state suspend_state;
/* Number of enabled target mode device on this card */
u_int enabled_luns;
/* Initialization level of this data structure */
u_int init_level;
/************************ Active Device Information ***************************/
typedef enum {
ROLE_UNKNOWN,
ROLE_INITIATOR,
ROLE_TARGET
} role_t;
struct ahd_devinfo {
int our_scsiid;
int target_offset;
uint16_t target_mask;
u_int target;
u_int lun;
char channel;
role_t role; /*
* Only guaranteed to be correct if not
* in the busfree state.
*/
};
/****************************** PCI Structures ********************************/
#define AHD_PCI_IOADDR0 PCI_MAPREG_START /* I/O BAR*/
#define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Memory BAR */
#define AHD_PCI_IOADDR1 (PCI_MAPREG_START + 12)/* Second I/O BAR */
typedef int (ahd_device_setup_t)(struct ahd_softc *, struct pci_attach_args *);
