/*
* Copyright (c) 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Since we don't support Burst Read, we have to read the clock twice
* until we get two consecutive identical results.
*/
retries = 5;
do {
if ((error = strtc_clock_read(sc, dt)) == 0)
error = strtc_clock_read(sc, &check);
if (error)
return error;
} while (memcmp(dt, &check, sizeof(check)) != 0 && --retries);
return (0);
}
static int
strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt)
{
u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2];
int i, error;
if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
aprint_error_dev(sc->sc_dev,
"strtc_clock_read: failed to acquire I2C bus\n");
return (error);
}
/*
* Check for the HT bit -- if set, then clock lost power & stopped
* If that happened, then clear the bit so that the clock will have
* a chance to run again.
*/
cmdbuf[0] = M41ST84_REG_AL_HOUR;
if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
iic_release_bus(sc->sc_tag, 0);
aprint_error_dev(sc->sc_dev,
"strtc_clock_read: failed to read HT\n");
return (error);
}
if (cmdbuf[1] & M41ST84_AL_HOUR_HT) {
cmdbuf[1] &= ~M41ST84_AL_HOUR_HT;
if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
iic_release_bus(sc->sc_tag, 0);
aprint_error_dev(sc->sc_dev,
"strtc_clock_read: failed to reset HT\n");
return (error);
}
}
/* Read each RTC register in order. */
for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) {
cmdbuf[0] = i;
/* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */
/* XXX: Wait, isn't that what rtc_offset in todr_gettime() is for? */
dt->dt_year = bcdtobin(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR;
return (0);
}
static int
strtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
{
struct strtc_softc *sc = ch->cookie;
uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2];
int i, error;
/*
* Convert our time representation into something the M41ST84
* can understand.
*/
bcd[M41ST84_REG_CSEC] = bintobcd(0); /* must always write as 0 */
bcd[M41ST84_REG_SEC] = bintobcd(dt->dt_sec);
bcd[M41ST84_REG_MIN] = bintobcd(dt->dt_min);
bcd[M41ST84_REG_CENHR] = bintobcd(dt->dt_hour);
bcd[M41ST84_REG_DATE] = bintobcd(dt->dt_day);
bcd[M41ST84_REG_DAY] = bintobcd(dt->dt_wday);
bcd[M41ST84_REG_MONTH] = bintobcd(dt->dt_mon);
bcd[M41ST84_REG_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100);
if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
aprint_error_dev(sc->sc_dev,
"strtc_clock_write: failed to acquire I2C bus\n");
return (error);
}
if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
iic_release_bus(sc->sc_tag, 0);
aprint_error_dev(sc->sc_dev,
"strtc_clock_write: failed to Hold Clock\n");
return (error);
}
/*
* Check for the HT bit -- if set, then clock lost power & stopped
* If that happened, then clear the bit so that the clock will have
* a chance to run again.
*/
cmdbuf[0] = M41ST84_REG_AL_HOUR;
if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
iic_release_bus(sc->sc_tag, 0);
aprint_error_dev(sc->sc_dev,
"strtc_clock_write: failed to read HT\n");
return (error);
}
if (cmdbuf[1] & M41ST84_AL_HOUR_HT) {
cmdbuf[1] &= ~M41ST84_AL_HOUR_HT;
if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
iic_release_bus(sc->sc_tag, 0);
aprint_error_dev(sc->sc_dev,
"strtc_clock_write: failed to reset HT\n");
return (error);
}
}
/*
* Write registers in reverse order. The last write (to the Seconds
* register) will undo the Clock Hold, above.
*/
for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) {
cmdbuf[0] = i;
if ((error = iic_exec(sc->sc_tag,
i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0)) != 0) {
iic_release_bus(sc->sc_tag, 0);
aprint_error_dev(sc->sc_dev,
"strtc_clock_write: failed to write rtc "
" at 0x%x\n", i);
/* XXX: Clock Hold is likely still asserted! */
return (error);
}
}
