/*-
* Copyright (c) 1998 Minoura Makoto
* Copyright (c) 1996 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Gordon W. Ross.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Zilog Z8530 Dual UART driver (machine-dependent part)
*
* X68k uses one Z8530 built-in. Channel A is for RS-232C serial port;
* while channel B is dedicated to the mouse.
* Extra Z8530's can be installed for serial ports. This driver
* supports up to 5 chips including the built-in one.
*/
/*
* Some warts needed by z8530tty.c -
* The default parity REALLY needs to be the same as the PROM uses,
* or you can not see messages done with printf during boot-up...
*/
int zs_def_cflag = (CREAD | CS8 | HUPCL);
int zscn_def_cflag = (CREAD | CS8 | HUPCL);
/*
* X68k provides a 5.0 MHz clock to the ZS chips.
*/
#define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */
static int zshard(void *);
static int zs_get_speed(struct zs_chanstate *);
/*
* Is the zs chip present?
*/
static int
zs_match(device_t parent, cfdata_t cf, void *aux)
{
struct intio_attach_args *ia = aux;
struct zsdevice *zsaddr = (void *)ia->ia_addr;
int i;
if (strcmp(ia->ia_name, "zsc") != 0)
return 0;
for (i = 0; i < ZS_MAXDEV; i++)
if (zsaddr == (void *)zs_physaddr[i]) /* XXX */
break;
if (i == ZS_MAXDEV) {
/* not a recognized address */
return 0;
}
ia->ia_size = 8;
if (intio_map_allocate_region(parent, ia, INTIO_MAP_TESTONLY))
return 0;
if (badaddr((void *)IIOV(zsaddr)))
return 0;
return (1);
}
/*
* Attach a found zs.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct intio_attach_args *ia = aux;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct zs_chanstate *cs;
int r __diagused;
int s, channel;
zsc->zsc_dev = self;
aprint_normal("\n");
zsc->zsc_addr = (void *)ia->ia_addr;
ia->ia_size = 8;
r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
#ifdef DIAGNOSTIC
if (r)
panic("zs: intio IO map corruption");
#endif
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
device_t child;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splzs();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
child = config_found(self, (void *)&zsc_args, zs_print,
CFARGS_NONE);
#if ZSTTY > 0
if (zc == conschan &&
((child && strcmp(device_xname(child), "zstty0")) ||
child == NULL)) /* XXX */
panic("%s: console device mismatch", __func__);
#endif
if (child == NULL) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splzs();
/* interrupt vector */
zs_write_reg(cs, 2, ia->ia_intr);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
if (args->channel != -1)
aprint_normal(" channel %d", args->channel);
return UNCONF;
}
/*
* For x68k-port, we don't use autovectored interrupt.
* We do not need to look at all of the zs chips.
*/
static int
zshard(void *arg)
{
struct zsc_softc *zsc = arg;
int rval;
int s;
/*
* Actually, zs hardware ipl is 5.
* Here we disable all interrupts to shorten the zshard
* handling time. Otherwise, too many characters are
* dropped.
*/
s = splhigh();
rval = zsc_intr_hard(zsc);
/* We are at splzs here, so no need to lock. */
if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
softint_schedule(zsc->zsc_softintr_cookie);
splx(s);
return (rval);
}
/*
* Compute the current baud rate given a ZS channel.
*/
static int
zs_get_speed(struct zs_chanstate *cs)
{
int tconst;
/*
* MD functions for setting the baud rate and control modes.
*/
int
zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */)
{
int tconst, real_bps;
if (bps == 0)
return (0);
#ifdef DIAGNOSTIC
if (cs->cs_brg_clk == 0)
panic("zs_set_speed");
#endif
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
if (tconst < 0)
return (EINVAL);
/* Convert back to make sure we can do it. */
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
#if 0 /* XXX */
/* XXX - Allow some tolerance here? */
if (real_bps != bps)
return (EINVAL);
#else
/*
* Since our PCLK has somewhat strange value,
* we have to allow tolerance here.
*/
if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst)
return (EINVAL);
#endif
/****************************************************************
* Console support functions (x68k specific!)
* Note: this code is allowed to know about the layout of
* the chip registers, and uses that to keep things simple.
* XXX - I think I like the mvme167 code better. -gwr
****************************************************************/
/*
* Handle user request to enter kernel debugger.
*/
void
zs_abort(struct zs_chanstate *cs)
{
int rr0;
/* Wait for end of break to avoid PROM abort. */
/* XXX - Limit the wait? */
do {
rr0 = *cs->cs_reg_csr;
ZS_DELAY();
} while (rr0 & ZSRR0_BREAK);