/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _VAX_BUS_H_
#define _VAX_BUS_H_
#ifdef BUS_SPACE_DEBUG
#include <sys/systm.h> /* for printf() prototype */
/*
* Macros for sanity-checking the aligned-ness of pointers passed to
* bus space ops. These are not strictly necessary on the VAX, but
* could lead to performance improvements, and help catch problems
* with drivers that would creep up on other architectures.
*/
#define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \
((((u_long)(p)) & (sizeof(t)-1)) == 0)
/*
* int bus_space_subregion(bus_space_tag_t t,
* bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
* bus_space_handle_t *nbshp);
*
* Get a new handle for a subregion of an already-mapped area of bus space.
*/
/*
* int bus_space_free(bus_space_tag_t t,
* bus_space_handle_t bsh, bus_size_t size);
*
* Free a region of bus space.
*/
#define bus_space_free(t, h, s) \
(*(t)->vbs_free)((t)->vbs_cookie, (h), (s))
/*
* Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
*/
#define bus_space_vaddr(t, h) \
((void *) (h))
/*
* Mmap bus space for a user application.
*/
#define bus_space_mmap(t, a, o, p, f) \
(*(t)->vbs_mmap)((t)->vbs_cookie, (a), (o), (p), (f))
/*
* u_intN_t bus_space_read_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset);
*
* Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset.
*/
/*
* void bus_space_read_multi_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t *addr, size_t count);
*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
static __inline void
vax_mem_read_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint8_t *, size_t),
vax_mem_read_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint16_t *, size_t),
vax_mem_read_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint32_t *, size_t);
#define bus_space_read_multi_1(t, h, o, a, c) \
vax_mem_read_multi_1((t), (h), (o), (a), (c))
#define bus_space_read_multi_2(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
vax_mem_read_multi_2((t), (h), (o), (a), (c)); \
} while (0)
#define bus_space_read_multi_4(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
vax_mem_read_multi_4((t), (h), (o), (a), (c)); \
} while (0)
static __inline void
vax_mem_read_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t *a, size_t c)
{
const bus_addr_t addr = h + o;
for (; c != 0; c--, a++)
*a = *(volatile uint8_t *)(addr);
}
static __inline void
vax_mem_read_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t *a, size_t c)
{
const bus_addr_t addr = h + o;
for (; c != 0; c--, a++)
*a = *(volatile uint16_t *)(addr);
}
static __inline void
vax_mem_read_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t *a, size_t c)
{
const bus_addr_t addr = h + o;
for (; c != 0; c--, a++)
*a = *(volatile uint32_t *)(addr);
}
/*
* void bus_space_read_region_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t *addr, size_t count);
*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into
* buffer provided.
*/
#define bus_space_read_region_1(t, h, o, a, c) \
do { \
vax_mem_read_region_1((t), (h), (o), (a), (c)); \
} while (0)
#define bus_space_read_region_2(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
vax_mem_read_region_2((t), (h), (o), (a), (c)); \
} while (0)
#define bus_space_read_region_4(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
vax_mem_read_region_4((t), (h), (o), (a), (c)); \
} while (0)
static __inline void
vax_mem_read_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t *a, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr++, a++)
*a = *(volatile uint8_t *)(addr);
}
static __inline void
vax_mem_read_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t *a, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr += 2, a++)
*a = *(volatile uint16_t *)(addr);
}
static __inline void
vax_mem_read_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t *a, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr += 4, a++)
*a = *(volatile uint32_t *)(addr);
}
/*
* void bus_space_write_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t value);
*
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
#define bus_space_write_1(t, h, o, v) \
do { \
__USE(t); \
((void)(*(volatile uint8_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_2(t, h, o, v) \
do { \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
__USE(t); \
((void)(*(volatile uint16_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_4(t, h, o, v) \
do { \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
__USE(t); \
((void)(*(volatile uint32_t *)((h) + (o)) = (v))); \
} while (0)
/*
* void bus_space_write_multi_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* const u_intN_t *addr, size_t count);
*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
* provided to bus space described by tag/handle/offset.
*/
static __inline void
vax_mem_write_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
const uint8_t *, size_t),
vax_mem_write_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
const uint16_t *, size_t),
vax_mem_write_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
const uint32_t *, size_t);
#define bus_space_write_multi_1(t, h, o, a, c) \
do { \
vax_mem_write_multi_1((t), (h), (o), (a), (c)); \
} while (0)
#define bus_space_write_multi_2(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
vax_mem_write_multi_2((t), (h), (o), (a), (c)); \
} while (0)
#define bus_space_write_multi_4(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
vax_mem_write_multi_4((t), (h), (o), (a), (c)); \
} while (0)
static __inline void
vax_mem_write_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint8_t *a, size_t c)
{
const bus_addr_t addr = h + o;
for (; c != 0; c--, a++)
*(volatile uint8_t *)(addr) = *a;
}
static __inline void
vax_mem_write_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint16_t *a, size_t c)
{
const bus_addr_t addr = h + o;
for (; c != 0; c--, a++)
*(volatile uint16_t *)(addr) = *a;
}
static __inline void
vax_mem_write_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint32_t *a, size_t c)
{
const bus_addr_t addr = h + o;
for (; c != 0; c--, a++)
*(volatile uint32_t *)(addr) = *a;
}
/*
* void bus_space_write_region_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* const u_intN_t *addr, size_t count);
*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
* to bus space described by tag/handle starting at `offset'.
*/
static __inline void
vax_mem_write_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
const uint8_t *, size_t),
vax_mem_write_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
const uint16_t *, size_t),
vax_mem_write_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
const uint32_t *, size_t);
#define bus_space_write_region_1(t, h, o, a, c) \
vax_mem_write_region_1((t), (h), (o), (a), (c))
#define bus_space_write_region_2(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
vax_mem_write_region_2((t), (h), (o), (a), (c)); \
} while (0)
#define bus_space_write_region_4(t, h, o, a, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
vax_mem_write_region_4((t), (h), (o), (a), (c)); \
} while (0)
static __inline void
vax_mem_write_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint8_t *a, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr++, a++)
*(volatile uint8_t *)(addr) = *a;
}
static __inline void
vax_mem_write_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint16_t *a, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr++, a++)
*(volatile uint16_t *)(addr) = *a;
}
static __inline void
vax_mem_write_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
const uint32_t *a, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr++, a++)
*(volatile uint32_t *)(addr) = *a;
}
/*
* void bus_space_set_multi_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
* size_t count);
*
* Write the 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle/offset `count' times.
*/
#define bus_space_set_multi_1(t, h, o, v, c) \
vax_mem_set_multi_1((t), (h), (o), (v), (c))
#define bus_space_set_multi_2(t, h, o, v, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
vax_mem_set_multi_2((t), (h), (o), (v), (c)); \
} while (0)
#define bus_space_set_multi_4(t, h, o, v, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
vax_mem_set_multi_4((t), (h), (o), (v), (c)); \
} while (0)
static __inline void
vax_mem_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t v, size_t c)
{
bus_addr_t addr = h + o;
while (c--)
*(volatile uint8_t *)(addr) = v;
}
static __inline void
vax_mem_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t v, size_t c)
{
bus_addr_t addr = h + o;
while (c--)
*(volatile uint16_t *)(addr) = v;
}
static __inline void
vax_mem_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t v, size_t c)
{
bus_addr_t addr = h + o;
while (c--)
*(volatile uint32_t *)(addr) = v;
}
/*
* void bus_space_set_region_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
* size_t count);
*
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle starting at `offset'.
*/
#define bus_space_set_region_1(t, h, o, v, c) \
vax_mem_set_region_1((t), (h), (o), (v), (c))
#define bus_space_set_region_2(t, h, o, v, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
vax_mem_set_region_2((t), (h), (o), (v), (c)); \
} while (0)
#define bus_space_set_region_4(t, h, o, v, c) \
do { \
__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
vax_mem_set_region_4((t), (h), (o), (v), (c)); \
} while (0)
static __inline void
vax_mem_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint8_t v, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr++)
*(volatile uint8_t *)(addr) = v;
}
static __inline void
vax_mem_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint16_t v, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr += 2)
*(volatile uint16_t *)(addr) = v;
}
static __inline void
vax_mem_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
uint32_t v, size_t c)
{
bus_addr_t addr = h + o;
for (; c != 0; c--, addr += 4)
*(volatile uint32_t *)(addr) = v;
}
/*
* void bus_space_copy_region_N(bus_space_tag_t tag,
* bus_space_handle_t bsh1, bus_size_t off1,
* bus_space_handle_t bsh2, bus_size_t off2,
* size_t count);
*
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1 += 4, addr2 += 4)
*(volatile uint32_t *)(addr2) =
*(volatile uint32_t *)(addr1);
} else {
/* dest after src: copy backwards */
for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
c != 0; c--, addr1 -= 4, addr2 -= 4)
*(volatile uint32_t *)(addr2) =
*(volatile uint32_t *)(addr1);
}
}
/*
* Bus read/write barrier methods.
*
* void bus_space_barrier(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* bus_size_t len, int flags);
*
* Note: the vax does not currently require barriers, but we must
* provide the flags to MI code.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
/*
* Flags used in various bus DMA methods.
*/
#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
#define BUS_DMA_BUS2 0x020
#define BUS_DMA_BUS3 0x040
#define BUS_DMA_BUS4 0x080
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
#define VAX_BUS_DMA_SPILLPAGE BUS_DMA_BUS1 /* VS4000 kludge */
/*
* Private flags stored in the DMA map.
*/
#define DMAMAP_HAS_SGMAP 0x80000000 /* sgva/len are valid */
/*
* vax_bus_t
*
* Busses supported by NetBSD/vax, used by internal
* utility functions. NOT TO BE USED BY MACHINE-INDEPENDENT
* CODE!
*/
typedef enum {
VAX_BUS_MAINBUS,
VAX_BUS_SBI,
VAX_BUS_MASSBUS,
VAX_BUS_UNIBUS, /* Also handles QBUS */
VAX_BUS_BI,
VAX_BUS_XMI,
VAX_BUS_TURBOCHANNEL
} vax_bus_t;
/*
* bus_dma_segment_t
*
* Describes a single contiguous DMA transaction. Values
* are suitable for programming into DMA registers.
*/
struct vax_bus_dma_segment {
bus_addr_t ds_addr; /* DMA address */
bus_size_t ds_len; /* length of transfer */
};
typedef struct vax_bus_dma_segment bus_dma_segment_t;
struct proc;
/*
* bus_dma_tag_t
*
* A machine-dependent opaque type describing the implementation of
* DMA for a given bus.
*/
struct vax_bus_dma_tag {
void *_cookie; /* cookie used in the guts */
bus_addr_t _wbase; /* DMA window base */
bus_size_t _wsize; /* DMA window size */
/*
* Some chipsets have a built-in boundary constraint, independent
* of what the device requests. This allows that boundary to
* be specified. If the device has a more restrictive constraint,
* the map will use that, otherwise this boundary will be used.
* This value is ignored if 0.
*/
bus_size_t _boundary;
/*
* A bus may have more than one SGMAP window, so SGMAP
* windows also get a pointer to their SGMAP state.
*/
struct vax_sgmap *_sgmap;
/*
* Internal-use only utility methods. NOT TO BE USED BY
* MACHINE-INDEPENDENT CODE!
*/
bus_dma_tag_t (*_get_tag)(bus_dma_tag_t, vax_bus_t);
/*
* bus_dmamap_t
*
* Describes a DMA mapping.
*/
struct vax_bus_dmamap {
/*
* PRIVATE MEMBERS: not for use my machine-independent code.
*/
bus_size_t _dm_size; /* largest DMA transfer mappable */
int _dm_segcnt; /* number of segs this map can map */
bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
bus_size_t _dm_boundary; /* don't cross this */
int _dm_flags; /* misc. flags */
/*
* This is used only for SGMAP-mapped DMA, but we keep it
* here to avoid pointless indirection.
*/
int _dm_pteidx; /* PTE index */
int _dm_ptecnt; /* PTE count */
u_long _dm_sgva; /* allocated sgva */
bus_size_t _dm_sgvalen; /* svga length */
/*
* PUBLIC MEMBERS: these are used by machine-independent code.
*/
bus_size_t dm_maxsegsz; /* largest possible segment */
bus_size_t dm_mapsize; /* size of the mapping */
int dm_nsegs; /* # valid segments in mapping */
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
};