/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Gordon W. Ross.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Sun3/E SCSI driver (machine-dependent portion).
* The machine-independent parts are in ncr5380sbc.c
*
* XXX - Mostly from the si driver. Merge?
*/
/*
* Transfers smaller than this are done using PIO
* (on assumption they're not worth DMA overhead)
*/
#define MIN_DMA_LEN 128
/*
* Transfers larger than 65535 bytes need to be split-up.
* (Some of the FIFO logic has only 16 bits counters.)
* Make the size an integer multiple of the page size
* to avoid buf/cluster remap problems. (paranoid?)
*/
#define MAX_DMA_LEN 0xE000
/*
* This structure is used to keep track of mapped DMA requests.
*/
struct se_dma_handle {
int dh_flags;
#define SIDH_BUSY 1 /* This DH is in use */
#define SIDH_OUT 2 /* DMA does data out (write) */
u_char * dh_addr; /* KVA of start of buffer */
int dh_maplen; /* Length of KVA mapping. */
long dh_dma; /* Offset in DMA buffer. */
};
/*
* The first structure member has to be the ncr5380_softc
* so we can just cast to go back and fourth between them.
*/
struct se_softc {
struct ncr5380_softc ncr_sc;
volatile struct se_regs *sc_regs;
int sc_adapter_type;
int sc_adapter_iv; /* int. vec */
int sc_options; /* options for this instance */
int sc_reqlen; /* requested transfer length */
struct se_dma_handle *sc_dma;
/* DMA command block for the OBIO controller. */
void *sc_dmacmd;
};
/* Options for disconnect/reselect, DMA, and interrupts. */
#define SE_NO_DISCONNECT 0xff
#define SE_NO_PARITY_CHK 0xff00
#define SE_FORCE_POLLING 0x10000
#define SE_DISABLE_DMA 0x20000
#ifdef DEBUG
if (se_debug) {
printf("%s\n", __func__);
}
#endif
/* The reset bits in the CSR are active low. */
se->se_csr = 0;
delay(10);
se->se_csr = SE_CSR_SCSI_RES /* | SE_CSR_INTR_EN */ ;
delay(10);
/* Make sure the DMA engine is stopped. */
se->dma_addr = 0;
se->dma_cntr = 0;
se->se_ivec = sc->sc_adapter_iv;
}
/*
* This is called when the bus is going idle,
* so we want to enable the SBC interrupts.
* That is controlled by the DMA enable!
* Who would have guessed!
* What a NASTY trick!
*/
void
se_intr_on(struct ncr5380_softc *ncr_sc)
{
struct se_softc *sc = (struct se_softc *)ncr_sc;
volatile struct se_regs *se = sc->sc_regs;
/* receive mode should be safer */
se->se_csr &= ~SE_CSR_SEND;
/* Clear the count so nothing happens. */
se->dma_cntr = 0;
/*
* This is called when the bus is idle and we are
* about to start playing with the SBC chip.
*/
void
se_intr_off(struct ncr5380_softc *ncr_sc)
{
struct se_softc *sc = (struct se_softc *)ncr_sc;
volatile struct se_regs *se = sc->sc_regs;
se->se_csr &= ~SE_CSR_INTR_EN;
}
/*
* This function is called during the COMMAND or MSG_IN phase
* that precedes a DATA_IN or DATA_OUT phase, in case we need
* to setup the DMA engine before the bus enters a DATA phase.
*
* On the VME version, setup the start address, but clear the
* count (to make sure it stays idle) and set that later.
* XXX: The VME adapter appears to suppress SBC interrupts
* when the FIFO is not empty or the FIFO count is non-zero!
* XXX: Need to copy data into the DMA buffer...
*/
void
se_dma_setup(struct ncr5380_softc *ncr_sc)
{
struct se_softc *sc = (struct se_softc *)ncr_sc;
struct sci_req *sr = ncr_sc->sc_current;
struct se_dma_handle *dh = sr->sr_dma_hand;
volatile struct se_regs *se = sc->sc_regs;
long data_pa;
int xlen;
/*
* Get the DMA mapping for this segment.
* XXX - Should separate allocation and mapin.
*/
data_pa = 0; /* XXX se_dma_kvtopa(dh->dh_dma); */
data_pa += (ncr_sc->sc_dataptr - dh->dh_addr);
if (data_pa & 1)
panic("%s: bad pa=0x%lx", __func__, data_pa);
xlen = ncr_sc->sc_datalen;
xlen &= ~1; /* XXX: necessary? */
sc->sc_reqlen = xlen; /* XXX: or less? */
if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
#ifdef DEBUG
printf("%s: DMA not running\n", __func__);
#endif
return;
}
ncr_sc->sc_state &= ~NCR_DOINGDMA;
/* First, halt the DMA engine. */
se->se_csr &= ~SE_CSR_INTR_EN; /* VME only */
/* Set an impossible phase to prevent data movement? */
*ncr_sc->sci_tcmd = PHASE_INVALID;
/* Note that timeout may have set the error flag. */
if (ncr_sc->sc_state & NCR_ABORTING)
goto out;
/* XXX: Wait for DMA to actually finish? */
/*
* Now try to figure out how much actually transferred
*/
resid = se->dma_cntr & 0xFFFF;
if (dh->dh_flags & SIDH_OUT)
if ((resid > 0) && (resid < sc->sc_reqlen))
resid++;
ntrans = sc->sc_reqlen - resid;
if (csr & SE_CSR_SBC_IP) {
claimed = ncr5380_intr(&sc->ncr_sc);
#ifdef DEBUG
if (!claimed) {
printf("%s: spurious from SBC\n", __func__);
}
#endif
/* Yes, we DID cause this interrupt. */
claimed = 1;
}
return claimed;
}
/*****************************************************************
* Common functions for DMA
****************************************************************/
/*
* Allocate a DMA handle and put it in sc->sc_dma. Prepare
* for DMA transfer. On the Sun3/E, this means we have to
* allocate space in the DMA buffer for this transfer.
*/
void
se_dma_alloc(struct ncr5380_softc *ncr_sc)
{
struct se_softc *sc = (struct se_softc *)ncr_sc;
struct sci_req *sr = ncr_sc->sc_current;
struct scsipi_xfer *xs = sr->sr_xs;
struct se_dma_handle *dh;
int i, xlen;
u_long addr;
#ifdef DIAGNOSTIC
if (sr->sr_dma_hand != NULL)
panic("%s: already have DMA handle", __func__);
#endif
/* If the DMA start addr is misaligned then do PIO */
if ((addr & 1) || (xlen & 1)) {
printf("%s: misaligned.\n", __func__);
return;
}
/* Make sure our caller checked sc_min_dma_len. */
if (xlen < MIN_DMA_LEN)
panic("%s: xlen=0x%x", __func__, xlen);
/*
* Never attempt single transfers of more than 63k, because
* our count register may be only 16 bits (an OBIO adapter).
* This should never happen since already bounded by minphys().
* XXX - Should just segment these...
*/
if (xlen > MAX_DMA_LEN) {
printf("%s: excessive xlen=0x%x\n", __func__, xlen);
ncr_sc->sc_datalen = xlen = MAX_DMA_LEN;
}
/* Find free DMA handle. Guaranteed to find one since we have
as many DMA handles as the driver has processes. */
for (i = 0; i < SCI_OPENINGS; i++) {
if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
goto found;
}
panic("se: no free DMA handles.");
found:
dh = &sc->sc_dma[i];
dh->dh_flags = SIDH_BUSY;
/* Copy the "write" flag for convenience. */
if (xs->xs_control & XS_CTL_DATA_OUT)
dh->dh_flags |= SIDH_OUT;
/*
* Poll (spin-wait) for DMA completion.
* Called right after xx_dma_start(), and
* xx_dma_stop() will be called next.
* Same for either VME or OBIO.
*/
void
se_dma_poll(struct ncr5380_softc *ncr_sc)
{
struct se_softc *sc = (struct se_softc *)ncr_sc;
struct sci_req *sr = ncr_sc->sc_current;
volatile struct se_regs *se = sc->sc_regs;
int tmo;
/* Make sure DMA started successfully. */
if (ncr_sc->sc_state & NCR_ABORTING)
return;
/*
* XXX: The Sun driver waits for ~SE_CSR_DMA_ACTIVE here
* XXX: (on obio) or even worse (on vme) a 10mS. delay!
* XXX: I really doubt that is necessary...
*/
/* Wait for any "DMA complete" or error bits. */
tmo = POLL_TIMO;
for (;;) {
if (se->se_csr & CSR_MASK)
break;
if (--tmo <= 0) {
printf("se: DMA timeout (while polling)\n");
/* Indicate timeout as MI code would. */
sr->sr_flags |= SR_OVERDUE;
break;
}
delay(100);
}
NCR_TRACE("se_dma_poll: waited %d\n",
POLL_TIMO - tmo);
