/*
* Copyright (c) 1996
* The President and Fellows of Harvard College. All rights reserved.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgements:
* This product includes software developed by Harvard University.
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgements:
* This product includes software developed by Harvard University.
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)pte.h 8.1 (Berkeley) 6/11/93
*/
/*
* Sun-4 (sort of), 4c (SparcStation), and 4m Page Table Entries
* (Sun calls them `Page Map Entries').
*/
#ifndef _LOCORE
/*
* Segment maps contain `pmeg' (Page Map Entry Group) numbers.
* A PMEG is simply an index that names a group of 32 (sun4) or
* 64 (sun4c) PTEs.
* Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits
* to hold the hardware MMU resource number.
*/
typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */
/*
* Region maps contain `smeg' (Segment Entry Group) numbers.
* An SMEG is simply an index that names a group of 64 PMEGs.
*/
typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */
#endif
/*
* Address translation works as follows:
*
* (for sun4c and 2-level sun4)
* 1. test va<31:29> -- these must be 000 or 111 (or you get a fault)
* 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number;
* use this to index the segment maps, yielding a 7 or 9 bit value.
* (for 3-level sun4)
* 1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number;
* use this to index the region maps, yielding a 10 bit value.
* 2. take the value from (1) above and concatenate va<17:12> to
* get a `segment map entry' index. This gives a 9 bit value.
* (for sun4c)
* 3. take the value from (2) above and concatenate va<17:12> to
* get a `page map entry' index. This gives a 32-bit PTE.
* (for sun4)
* 3. take the value from (2 or 3) above and concatenate va<17:13> to
* get a `page map entry' index. This gives a 32-bit PTE.
**
* For sun4m:
* 1. Use context_reg<3:0> to index the context table (located at
* (context_reg << 2) | ((ctx_tbl_ptr_reg >> 2) << 6) ). This
* gives a 32-bit page-table-descriptor (PTP).
* 2. Use va<31:24> to index the region table located by the PTP from (1):
* PTP<31:6> << 10. This gives another PTP for the segment tables
* 3. Use va<23:18> to index the segment table located by the PTP from (2)
* as follows: PTP<31:4> << 8. This gives another PTP for the page tbl.
* 4. Use va<17:12> to index the page table given by (3)'s PTP:
* PTP<31:4> << 8. This gives a 32-bit PTE.
*
* In other words:
*
* struct sun4_3_levelmmu_virtual_addr {
* u_int va_reg:8, (virtual region)
* va_seg:6, (virtual segment)
* va_pg:5, (virtual page within segment)
* va_off:13; (offset within page)
* };
* struct sun4_virtual_addr {
* u_int :2, (required to be the same as bit 29)
* va_seg:12, (virtual segment)
* va_pg:5, (virtual page within segment)
* va_off:13; (offset within page)
* };
* struct sun4c_virtual_addr {
* u_int :2, (required to be the same as bit 29)
* va_seg:12, (virtual segment)
* va_pg:6, (virtual page within segment)
* va_off:12; (offset within page)
* };
*
* struct sun4m_virtual_addr {
* u_int va_reg:8, (virtual region)
* va_seg:6, (virtual segment within region)
* va_pg:6, (virtual page within segment)
* va_off:12; (offset within page)
* };
*
* Then, given any `va':
*
* extern smeg_t regmap[16][1<<8]; (3-level MMU only)
* extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4)
* extern int ptetable[128][1<<6]; ([512][1<<5] for sun4)
*
* extern u_int s4m_ctxmap[16]; (sun4m SRMMU only)
* extern u_int s4m_regmap[16][1<<8]; (sun4m SRMMU only)
* extern u_int s4m_segmap[1<<8][1<<6]; (sun4m SRMMU only)
* extern u_int s4m_pagmap[1<<14][1<<6]; (sun4m SRMMU only)
*
* (the above being in the hardware, accessed as Alternate Address Spaces on
* all machines but the Sun4m SRMMU, in which case the tables are in physical
* kernel memory. In the 4m architecture, the tables are not laid out as
* 2-dim arrays, but are sparsely allocated as needed, and point to each
* other.)
*
* if (cputyp==CPU_SUN4M || cputyp==CPU_SUN4D) // SPARC Reference MMU
* regptp = s4m_ctxmap[curr_ctx];
* if (!(regptp & SRMMU_TEPTD)) TRAP();
* segptp = *(u_int *)(((regptp & ~0x3) << 4) | va.va_reg);
* if (!(segptp & SRMMU_TEPTD)) TRAP();
* pagptp = *(u_int *)(((segptp & ~0x3) << 4) | va.va_seg);
* if (!(pagptp & SRMMU_TEPTD)) TRAP();
* pte = *(u_int *)(((pagptp & ~0x3) << 4) | va.va_pg);
* if (!(pte & SRMMU_TEPTE)) TRAP(); // like PG_V
* if (usermode && PTE_PROT_LEVEL(pte) > 0x5) TRAP();
* if (writing && !PTE_PROT_LEVEL_ALLOWS_WRITING(pte)) TRAP();
* if (!(pte & SRMMU_PG_C)) DO_NOT_USE_CACHE_FOR_THIS_ACCESS();
* pte |= SRMMU_PG_U;
* if (writing) pte |= PG_M;
* physaddr = ((pte & SRMMU_PG_PFNUM) << SRMMU_PGSHIFT)|va.va_off;
* return;
* if (mmu_3l)
* physreg = regmap[curr_ctx][va.va_reg];
* physseg = segmap[physreg][va.va_seg];
* else
* physseg = segmap[curr_ctx][va.va_seg];
* pte = ptetable[physseg][va.va_pg];
* if (!(pte & PG_V)) TRAP();
* if (writing && !pte.pg_w) TRAP();
* if (usermode && pte.pg_s) TRAP();
* if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS();
* pte |= PG_U; (mark used/accessed)
* if (writing) pte |= PG_M; (mark modified)
* ptetable[physseg][va.va_pg] = pte;
* physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off;
*/
/* number of PTEs that map one segment (not number that fit in one segment!) */
#if defined(SUN4) && (defined(SUN4C) || defined(SUN4M) || defined(SUN4D))
extern int nptesg;
#define NPTESG nptesg /* (which someone will have to initialize) */
#else
#define NPTESG (NBPSG / NBPG)
#endif
/* virtual address to virtual region number */
#define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255)
/* virtual address to virtual segment number */
#define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63)
/* Define the virtual address space hole */
#define MMU_HOLE_START 0x20000000
#define MMU_HOLE_END 0xe0000000
/* there is no `struct pte'; we just use `int'; this is for non-4M only */
#define PG_V 0x80000000
#define PG_PROT 0x60000000 /* both protection bits */
#define PG_W 0x40000000 /* allowed to write */
#define PG_S 0x20000000 /* supervisor only */
#define PG_NC 0x10000000 /* non-cacheable */
#define PG_TYPE 0x0c000000 /* both type bits */
#define PG_OBMEM 0x00000000 /* on board memory */
#define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */
#define PG_VME16 0x08000000 /* 16-bit-data VME space */
#define PG_VME32 0x0c000000 /* 32-bit-data VME space */
#if defined(SUN4M) || defined(SUN4D)
#define PG_SUN4M_OBMEM 0x0 /* No type bits=>obmem on 4m */
#define PG_SUN4M_OBIO 0xf /* obio maps to 0xf on 4M */
#define SRMMU_PGTYPE 0xf0000000 /* Top 4 bits of pte PPN give type */
#endif
#define PG_U 0x02000000
#define PG_M 0x01000000
#define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */
#define PG_IOC 0x00800000 /* IO cache, not used yet */
#define PG_WIRED 0x00400000 /* S/W only; in MBZ area */
#define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */
#define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */
#define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */
#define PG_M_SHIFT4M 5 /* shift to get SRMMU_PG_M,R on 4m */
/*efine PG_NOACC 0 ** XXX */
#define PG_KR 0x20000000
#define PG_KW 0x60000000
#define PG_URKR 0
#define PG_UW 0x40000000
/*
* These are needed in the register window code
* to check the validity of (ostensible) user stack PTEs.
*/
#define PG_VSHIFT 29 /* (va>>vshift)==0 or -1 => valid */
/* XXX fix this name, it is a va shift not a pte bit shift! */