/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)psl.h 8.1 (Berkeley) 6/11/93
*/
#ifndef PSR_IMPL
/*
* SPARC Process Status Register (in psl.h for hysterical raisins). This
* doesn't exist on the V9.
*
* The picture in the Sun manuals looks like this:
* 1 1
* 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
* | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
* | | |n z v c| |C|F| | |S|T| |
* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
*/
/*
* 32-bit code requires TSO or at best PSO since that's what's supported on
* SPARC V8 and earlier machines.
*
* 64-bit code sets the memory model in the ELF header.
*
* We're running kernel code in TSO for the moment so we don't need to worry
* about possible memory barrier bugs.
*/
/*
* Register window handlers. These point to generic routines that check the
* stack pointer and then vector to the real handler. We could optimize this
* if we could guarantee only 32-bit or 64-bit stacks.
*/
#define WSTATE_KERN 026
#define WSTATE_USER 022
#define CWP 0x01f
/* 64-byte alignment -- this seems the best place to put this. */
#define SPARC64_BLOCK_SIZE 64
#define SPARC64_BLOCK_ALIGN 0x3f
/*
* GCC pseudo-functions for manipulating PSR (primarily PIL field).
*/
static __inline __attribute__((__always_inline__)) int
getpsr(void)
{
int psr;
static __inline __attribute__((__always_inline__)) void
spl0(void)
{
int psr, oldipl;
/*
* wrpsr xors two values: we choose old psr and old ipl here,
* which gives us the same value as the old psr but with all
* the old PIL bits turned off.
*/
__asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory");
oldipl = psr & PSR_PIL;
__asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
/*
* Three instructions must execute before we can depend
* on the bits to be changed.
*/
__asm volatile("nop; nop; nop");
}
/*
* PIL 1 through 14 can use this macro.
* (spl0 and splhigh are special since they put all 0s or all 1s
* into the ipl field.)
*/
#define _SPLSET(name, newipl) \
static __inline __attribute__((__always_inline__)) void name(void) \
{ \
int psr; \
__asm volatile("rd %%psr,%0" : "=r" (psr)); \
psr &= ~PSR_PIL; \
__asm volatile("wr %0,%1,%%psr" : : \
"r" (psr), "n" ((newipl) << 8)); \
__asm volatile("nop; nop; nop" : : : "memory"); \
}
/* Raise IPL and return previous value */
static __inline __always_inline int
splraiseipl(ipl_cookie_t icookie)
{
int newipl = icookie._ipl;
int psr, oldipl;
__asm volatile("rd %%psr,%0" : "=r" (psr));
oldipl = psr & PSR_PIL;
newipl <<= 8;
if (newipl <= oldipl)
return (oldipl);