/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)instr.h 8.1 (Berkeley) 6/11/93
*/
/*
* An instruction.
*/
union instr {
int i_int; /* as a whole */
/*
* The first level of decoding is to use the top 2 bits.
* This gives us one of three `formats', which usually give
* a second level of decoding.
*/
struct {
u_int i_op:2; /* first-level decode */
u_int :30;
} i_any;
/* one last branch: BPr */
struct {
u_int :2; /* 00 */
u_int i_annul:1; /* annul bit */
u_int :1; /* 0 */
u_int i_rcond:4; /* register condition */
u_int :3; /* 011 */
int i_disphi:2; /* branch displacement, hi bits */
u_int i_pred:1; /* branch prediction bit */
u_int i_rs1:1; /* source register 1 */
u_int i_displo:16; /* branch displacement, lo bits */
} i_branch_pr;
/*
* Format 3 instructions (memory reference; arithmetic, logical,
* shift, and other miscellaneous operations). The second-level
* decode almost always makes use of an `rd' and `rs1', however
* (see also IOP3_reg and IOP3_mem).
*
* Beyond that, the low 14 bits may be broken up in one of three
* different ways, if at all:
* 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
* 1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
* 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only]
*/
struct {
u_int :2; /* 10 or 11 */
u_int i_rd:5; /* destination register */
u_int i_op3:6; /* second-level decode */
u_int i_rs1:5; /* source register 1 */
u_int i_low14:14; /* varies */
} i_op3;
/*
* Memory forms. These set i_op=3 and use simm13 or asi layout.
* Memory references without an ASI should use 0, but the actual
* ASI field is simply ignored.
*/
struct {
u_int :2; /* 11 only */
u_int i_rd:5; /* destination register */
u_int i_op3:6; /* second-level decode (see IOP3_mem) */
u_int i_rs1:5; /* source register 1 */
u_int i_i:1; /* immediate vs asi */
u_int i_low13:13; /* depend on i bit */
} i_loadstore;
/*
* Memory and register forms.
* These come in quite a variety and we do not
* attempt to break them down much.
*/
struct {
u_int :2; /* 10 or 11 */
u_int i_rd:5; /* destination register */
u_int i_op3:6; /* second-level decode */
u_int i_rs1:5; /* source register 1 */
u_int i_i:1; /* immediate bit (1) */
int i_simm13:13; /* signed immediate */
} i_simm13;
struct {
u_int :2; /* 10 or 11 */
u_int i_rd:5; /* destination register */
u_int i_op3:6; /* second-level decode */
u_int i_rs1:5; /* source register 1 */
u_int i_i:1; /* immediate vs asi */
u_int i_asi:8; /* asi */
u_int i_rs2:5; /* source register 2 */
} i_asi;
struct {
u_int :2; /* 10 only (register, no memory) */
u_int i_rd:5; /* destination register */
u_int i_op3:6; /* second-level decode (see IOP3_reg) */
u_int i_rs1:5; /* source register 1 */
u_int i_opf:9; /* coprocessor 3rd-level decode */
u_int i_rs2:5; /* source register 2 */
} i_opf;
/*
* Format 4 instructions (movcc, fmovr, fmovcc, and tcc). The
* second-level decode almost always makes use of an `rd' and either
* `rs1' or `cond'.
*
* Beyond that, the low 14 bits may be broken up in one of three
* different ways, if at all:
* 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
* 1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
* 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] */
struct {
u_int :2; /* 10 */
u_int i_rd:5; /* destination register */
u_int i_op3:6; /* second-level decode */
u_int i_rs1:5; /* source register 1 */
u_int i_low14:14; /* varies */
} i_op4;
/*
* Internal macros for building instructions. These correspond 1-to-1 to
* the names above. Note that x << y | z == (x << y) | z.
*/
#define _I_ANY(op, b) ((op) << 30 | (b))
/*
* (Since these are sparse, we skip the enumerations for now.)
* FPop values. All appear in both FPop1 and FPop2 spaces, but arithmetic
* ops should happen only with FPop1 and comparison only with FPop2.
* The type sits in the low two bits; those bits are given as zero here.
*/
#define FMOV 0x00
#define FNEG 0x04
#define FABS 0x08
#define FSQRT 0x28
#define FADD 0x40
#define FSUB 0x44
#define FMUL 0x48
#define FDIV 0x4c
#define FCMP 0x50
#define FCMPE 0x54
#define FSMULD 0x68
#define FDMULX 0x6c
#define FTOX 0x80
#define FXTOS 0x84
#define FXTOD 0x88
#define FXTOQ 0x8c
#define FTOS 0xc4
#define FTOD 0xc8
#define FTOQ 0xcc
#define FTOI 0xd0
