/*
* Copyright (c) 1999, 2000 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* EBus support for PCI based SPARC systems (ms-IIep, Ultra).
* EBus is documented in PCIO manual (Sun Part#: 802-7837-01).
*/
/*
* "reg" contains exactly the info we'd get by processing
* "ranges", so don't bother with "ranges" and use "reg" directly.
*/
struct ofw_pci_register *sc_reg;
int sc_nreg;
};
/*
* here are our bus space and bus DMA routines.
*/
static paddr_t ebus_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
static int _ebus_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
vaddr_t, bus_space_handle_t *);
static void *ebus_intr_establish(bus_space_tag_t, int, int,
int (*)(void *), void *, void (*)(void));
/*
* Working around PROM bogosity.
*
* EBus doesn't have official OFW binding. sparc64 has a de-facto
* standard but patching it in in prompatch.c and then decoding it
* here would be an overkill for ms-IIep.
*
* So we assume that all ms-IIep based systems use PCIO chip only in
* "motherboard mode" with interrupt lines wired directly to ms-IIep
* interrupt inputs.
*
* Note that this is ineligible for prompatch.c, as we are not
* correcting PROM to conform to some established standard, this hack
* is tied to this version of ebus driver and as such it's better stay
* private to the driver.
*/
/*
* XXX: This assumes single EBus. However I don't think any ms-IIep
* system ever used more than one. In any case, without looking at a
* system with multiple PCIO chips I don't know how to correctly
* program the driver to handle PROM glitches in them, so for the time
* being just use globals.
*/
static const struct msiiep_ebus_intr_wiring *wiring_map;
static int wiring_map_size;
static int ebus_init_wiring_table(struct ebus_softc *);
static int
ebus_match(device_t parent, cfdata_t cf, void *aux)
{
struct pci_attach_args *pa = aux;
char name[10];
int node;
/* Only attach if there's a PROM node. */
node = PCITAG_NODE(pa->pa_tag);
if (node == -1)
return (0);
/* not found? we should have failed in pci_attach_hook then. */
panic("ebus_init_wiring_table: unknown model %s", model);
}
/*
* attach an ebus and all its children. this code is modeled
* after the sbus code which does similar things.
*/
static void
ebus_attach(device_t parent, device_t self, void *aux)
{
struct ebus_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
struct ebus_attach_args ea;
bus_space_tag_t sbt;
bus_dma_tag_t dmatag;
bus_space_handle_t hLED;
pcireg_t base14;
int node, error;
char devinfo[256];
/*
* Setup ranges. The interesting thing is that we use "reg"
* not "ranges", since "reg" on ebus has exactly the data we'd
* get by processing "ranges".
*/
error = prom_getprop(node, "reg", sizeof(struct ofw_pci_register),
&sc->sc_nreg, &sc->sc_reg);
if (error)
panic("%s: unable to read ebus registers (error %d)",
device_xname(self), error);
/*
* now attach all our children
*/
DPRINTF(EDB_CHILD, ("ebus node %08x, searching children...\n", node));
devhandle_t selfh = device_handle(self);
for (node = firstchild(node); node; node = nextsibling(node)) {
char *name = prom_getpropstring(node, "name");
static int
ebus_setup_attach_args(struct ebus_softc *sc,
bus_space_tag_t bustag, bus_dma_tag_t dmatag, int node,
struct ebus_attach_args *ea)
{
int n, err;
/*
* On Ultra the bar is the _offset_ of the BAR in PCI config
* space but in (some?) ms-IIep systems (e.g. Krups) it's the
* _number_ of the BAR - e.g. BAR1 is represented by 1 in
* Krups PROM, while on Ultra it's 0x14. Fix it here.
*/
for (n = 0; n < ea->ea_nreg; ++n)
if (ea->ea_reg[n].hi < PCI_MAPREG_START) {
ea->ea_reg[n].hi = PCI_MAPREG_START
+ ea->ea_reg[n].hi * sizeof(pcireg_t);
}
err = prom_getprop(node, "address", sizeof(uint32_t),
&ea->ea_nvaddr, &ea->ea_vaddr);
if (err != ENOENT) {
if (err != 0)
return (err);
if (ea->ea_name)
free((void *)ea->ea_name, M_DEVBUF);
if (ea->ea_reg)
free((void *)ea->ea_reg, M_DEVBUF);
if (ea->ea_intr)
free((void *)ea->ea_intr, M_DEVBUF);
if (ea->ea_vaddr)
free((void *)ea->ea_vaddr, M_DEVBUF);
}
static int
ebus_print(void *aux, const char *p)
{
struct ebus_attach_args *ea = aux;
int i;
if (p)
aprint_normal("%s at %s", ea->ea_name, p);
for (i = 0; i < ea->ea_nreg; ++i)
aprint_normal("%s bar %x offset 0x%x", i == 0 ? "" : ",",
ea->ea_reg[i].hi, ea->ea_reg[i].lo);
for (i = 0; i < ea->ea_nintr; ++i)
aprint_normal(" line %d", ea->ea_intr[i]);
return (UNCONF);
}
/*
* bus space and bus DMA methods below here
*/
static bus_dma_tag_t
ebus_alloc_dma_tag(struct ebus_softc *sc, bus_dma_tag_t pdt)
{
bus_dma_tag_t dt;
/*
* bus space support. <sparc64/dev/psychoreg.h> has a discussion
* about PCI physical addresses, which also applies to ebus.
*/
static int
_ebus_bus_map(bus_space_tag_t t, bus_addr_t ba, bus_size_t size, int flags,
vaddr_t va, bus_space_handle_t *hp)
{
struct ebus_softc *sc = t->cookie;
u_int bar;
paddr_t offset;
int i;
bar = BUS_ADDR_IOSPACE(ba);
offset = BUS_ADDR_PADDR(ba);
DPRINTF(EDB_BUSMAP,
("\n_ebus_bus_map: bar %d offset %08x sz %x flags %x va %p\n",
(int)bar, (uint32_t)offset, (uint32_t)size,
flags, (void *)va));
/* EBus has only two BARs */
if (PCI_MAPREG_NUM(bar) > 1) {
DPRINTF(EDB_BUSMAP,
("\n_ebus_bus_map: impossible bar\n"));
return (EINVAL);
}
/*
* Almost all of the interesting ebus children are mapped by
* BAR1, the last entry in sc_reg[], so work our way backwards.
*/
for (i = sc->sc_nreg - 1; i >= 0; --i) {
bus_addr_t pciaddr;
uint32_t ss;
/* EBus only does MEM32 */
ss = sc->sc_reg[i].phys_hi & OFW_PCI_PHYS_HI_SPACEMASK;
if (ss != OFW_PCI_PHYS_HI_SPACE_MEM32)
continue;
if (bar != (sc->sc_reg[i].phys_hi
& OFW_PCI_PHYS_HI_REGISTERMASK))
continue;
static paddr_t
ebus_bus_mmap(bus_space_tag_t t, bus_addr_t ba, off_t off, int prot, int flags)
{
/* XXX: not implemented yet */
return (-1);
}
/*
* Install an interrupt handler for a EBus device.
*/
static void *
ebus_intr_establish(bus_space_tag_t t, int pri, int level,
int (*handler)(void *), void *arg,
void (*fastvec)(void))
{
static void
ebus_blink(void *zero)
{
register int s;
s = splhigh();
*ebus_LED = ~*ebus_LED;
splx(s);
/*
* Blink rate is:
* full cycle every second if completely idle (loadav = 0)
* full cycle every 2 seconds if loadav = 1
* full cycle every 3 seconds if loadav = 2
* etc.
*/
s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1));
callout_reset(&ebus_blink_ch, s, ebus_blink, NULL);
}
#endif