/*
* Copyright 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Simon Burge for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* cpu_rmixl_watchpoint_init - initialize COP0 watchpoint stuff
*
* clear IEU_DEFEATURE[DBE] to ensure T_WATCH on watchpoint exception
* set COP0 watchhi and watchlo
*
* disable all watchpoints
*/
static void
cpu_rmixl_watchpoint_init(void)
{
uint32_t r;
r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE);
r &= ~__BIT(7); /* DBE */
rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r);
cpuwatch_clr_all();
}
/*
* cpu_xls616_erratum
*
* on the XLS616, COUNT/COMPARE clock regs seem to interact between
* threads on a core
*
* the symptom of the error is retarded clock interrupts
* and very slow apparent system performance
*
* other XLS chips may have the same problem.
* we may need to add other PID checks.
*/
static inline bool
cpu_xls616_erratum(device_t parent, struct cpucore_attach_args *ca)
{
#if 0
if (mips_options.mips_cpu->cpu_pid == MIPS_XLS616) {
if (ca->ca_thread > 0) {
aprint_error_dev(parent, "XLS616 CLOCK ERRATUM: "
"deconfigure cpu%d\n", ca->ca_thread);
return true;
}
}
#endif
return false;
}
#ifdef DIAGNOSTIC
/* Ensure our current stack can be used by the firmware */
uint64_t sp;
__asm__ volatile("move %0, $sp\n" : "=r"(sp));
#ifdef _LP64
/* can be made into a KSEG0 addr */
KASSERT(MIPS_XKPHYS_P(sp));
KASSERT((MIPS_XKPHYS_TO_PHYS(sp) >> 32) == 0);
#else
/* is a KSEG0 addr */
KASSERT(MIPS_KSEG0_P(sp));
#endif /* _LP64 */
#endif /* DIAGNOSTIC */
#ifndef _LP64
/*
* Ensure 'ci' is a KSEG0 address for trampoline args
* to avoid TLB fault in cpu_trampoline() when loading ci_idlelwp
*/
KASSERT(MIPS_KSEG0_P(ci));
#endif
/*
* Ensure 'ta' is a KSEG0 address for trampoline args
* to avoid TLB fault in trampoline when loading args.
*
* Note:
* RMI firmware only passes the lower 32-bit half of 'ta'
* to rmixl_cpu_trampoline (the upper half is clear)
* so rmixl_cpu_trampoline must reconstruct the missing upper half
* rmixl_cpu_trampoline "knows" 'ta' is a KSEG0 address
* and sign-extends to make an LP64 KSEG0 address.
*/
KASSERT(MIPS_KSEG0_P(ta));
/*
* marshal args for rmixl_cpu_trampoline;
* note for non-LP64 kernel, use of intptr_t
* forces sign extension of 32 bit pointers
*/
stacktop = (uintptr_t)l->l_md.md_utf - CALLFRAME_SIZ;
ta->ta_sp = (uint64_t)(intptr_t)stacktop;
ta->ta_lwp = (uint64_t)(intptr_t)l;
ta->ta_cpuinfo = (uint64_t)(intptr_t)ci;
