/*
* Copyright (c) 2009 Miodrag Vallat.
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)machConst.h 8.1 (Berkeley) 6/10/93
*
* machConst.h --
*
* Machine dependent constants.
*
* Copyright (C) 1989 Digital Equipment Corporation.
* Permission to use, copy, modify, and distribute this software and
* its documentation for any purpose and without fee is hereby granted,
* provided that the above copyright notice appears in all copies.
* Digital Equipment Corporation makes no representations about the
* suitability of this software for any purpose. It is provided "as is"
* without express or implied warranty.
*
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
* v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
* v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
*/
/*
* The bits in the cause register.
*
* Bits common to r3000 and r4000:
*
* MIPS_CR_BR_DELAY Exception happened in branch delay slot.
* MIPS_CR_COP_ERR Coprocessor error.
* MIPS_CR_IP Interrupt pending bits defined below.
* (same meaning as in CAUSE register).
* MIPS_CR_EXC_CODE The exception type (see exception codes below).
*
* Differences:
* r3k has 4 bits of exception type, r4k has 5 bits.
*/
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
#define MIPS_CR_COP_ERR_CU1 1
#define MIPS_CR_COP_ERR_CU2 2
#define MIPS_CR_COP_ERR_CU3 3
#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
/*
* The bits in the status register. All bits are active when set to 1.
*
* R3000 status register fields:
* MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
* MIPS_SR_TS TLB shutdown.
*
* MIPS_SR_INT_IE Master (current) interrupt enable bit.
*
* Differences:
* r3k has cache control is via frobbing SR register bits, whereas the
* r4k cache control is via explicit instructions.
* r3k has a 3-entry stack of kernel/user bits, whereas the
* r4k has kernel/supervisor/user.
*/
#define MIPS_SR_COP_USABILITY 0xf0000000
#define MIPS_SR_COP_0_BIT 0x10000000
#define MIPS_SR_COP_1_BIT 0x20000000
#define MIPS_SR_COP_2_BIT 0x40000000
#define MIPS_SR_INT_IE 0x00000001
/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
/*#define MIPS_SR_INT_MASK 0x0000ff00*/
/*
* The R2000/R3000-specific status register bit definitions.
* all bits are active when set to 1.
*
* MIPS_SR_PARITY_ERR Parity error.
* MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
* MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
* MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
* MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
* Interrupt enable bits defined below.
* MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
* MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
* MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
* MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
*/
/*
* R4000 status register bit definitions,
* where different from r2000/r3000.
*/
#define MIPS3_SR_XX 0x80000000
#define MIPS3_SR_RP 0x08000000
#define MIPS3_SR_FR 0x04000000
#define MIPS3_SR_RE 0x02000000
/*
* The floating point version and status registers.
*/
#define MIPS_FIR $0 /* FP Implementation and Revision Register */
#define MIPS_FCSR $31 /* FP Control/Status Register */
/*
* Bits defined for EBASE (CP0 register 15, select 1).
*/
#define MIPS_EBASE_EXC_BASE_SHIFT 12
#define MIPS_EBASE_EXC_BASE __BITS(29, MIPS_EBASE_EXC_BASE_SHIFT)
#define MIPS_EBASE_CPUNUM __BITS(9, 0)
#define MIPS_EBASE_CPUNUM_WIDTH 10 /* used by asm code */
/*
* Hints for the prefetch instruction
*/
/*
* Prefetched data is expected to be read (not modified)
*/
#define PREF_LOAD 0
#define PREF_LOAD_STREAMED 4 /* but not reused extensively; it */
/* "streams" through cache. */
#define PREF_LOAD_RETAINED 6 /* and reused extensively; it should */
/* be "retained" in the cache. */
/*
* Prefetched data is expected to be stored or modified
*/
#define PREF_STORE 1
#define PREF_STORE_STREAMED 5 /* but not reused extensively; it */
/* "streams" through cache. */
#define PREF_STORE_RETAINED 7 /* and reused extensively; it should */
/* be "retained" in the cache. */
/*
* data is no longer expected to be used. For a WB cache, schedule a
* writeback of any dirty data and afterwards free the cache lines.
*/
#define PREF_WB_INV 25
#define PREF_NUDGE PREF_WB_INV
/*
* Prepare for writing an entire cache line without the overhead
* involved in filling the line from memory.
*/
#define PREF_PREPAREFORSTORE 30
/*
* CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
*/
#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
#define MIPS_R4650 0x22 /* QED R4650 ISA III */
#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
#define MIPS_LOONGSON2 0x63 /* ICT Loongson-2 ISA III */
/*
* CPU revision IDs for some prehistoric processors.
*/
/* For MIPS_TX4900 */
#define MIPS_REV_TX4927 0x22
/* For MIPS_LOONGSON2 */
#define MIPS_REV_LOONGSON2E 0x02
#define MIPS_REV_LOONGSON2F 0x03
/*
* CPU processor revision IDs for company ID == 1 (MIPS)
*/
#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */
#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */
#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
#define MIPS_1004K 0x99 /* MIPS 1004Kc/1004Kf ISA 32 Rel 2 */
#define MIPS_1074K 0x9a /* MIPS 1074Kc/1074Kf ISA 32 Rel 2 */
#define MIPS_interAptiv 0xa1 /* MIPS interAptiv ISA 32 R3 MT */
/*
* CPU processor revision IDs for company ID == 2 (Broadcom)
*/
#define MIPS_BCM3302 0x90 /* MIPS 4KEc_R2-like? ISA 32 Rel 2 */
/*
* Alchemy (company ID 3) use the processor ID field to denote the CPU core
* revision and the company options field do donate the SOC chip type.
*/
/* CPU processor revision IDs */
#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
/* CPU company options IDs */
#define MIPS_AU1000 0x00
#define MIPS_AU1500 0x01
#define MIPS_AU1100 0x02
#define MIPS_AU1550 0x03
/*
* CPU processor revision IDs for company ID == 4 (SiByte)
*/
#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
#define MIPS_SB1_11 0x11 /* SiByte SB1 (rev 0x11) ISA 64 */
/*
* CPU processor revision IDs for company ID == 5 (SandCraft)
*/
#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
/*
* CPU revision IDs for company ID == 12 (RMI)
* note: unlisted Rev values may indicate pre-production silicon
*/
#define MIPS_XLR_B2 0x04 /* RMI XLR Production Rev B2 */
#define MIPS_XLR_C4 0x91 /* RMI XLR Production Rev C4 */
/*
* CPU processor IDs for company ID == 12 (RMI)
*/
#define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */
#define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */
#define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */
#define MIPS_XLR532B 0x09 /* RMI XLR532-B ISA 64 */
#define MIPS_XLR716B 0x0a /* RMI XLR716-B ISA 64 */
#define MIPS_XLR732B 0x0b /* RMI XLR732-B ISA 64 */
#define MIPS_XLR732C 0x00 /* RMI XLR732-C ISA 64 */
#define MIPS_XLR716C 0x02 /* RMI XLR716-C ISA 64 */
#define MIPS_XLR532C 0x08 /* RMI XLR532-C ISA 64 */
#define MIPS_XLR516C 0x0a /* RMI XLR516-C ISA 64 */
#define MIPS_XLR508C 0x0b /* RMI XLR508-C ISA 64 */
#define MIPS_XLR308C 0x0f /* RMI XLR308-C ISA 64 */
#define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
#define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
#define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
#define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
#define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
#define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
#define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
#define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
#define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
#define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
#define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
/*
* CPU processor IDs for company ID == 13 (Cavium)
*/
#define MIPS_CN38XX 0x00 /* Cavium Octeon CN38XX ISA 64 */
#define MIPS_CN31XX 0x01 /* Cavium Octeon CN31XX ISA 64 */
#define MIPS_CN30XX 0x02 /* Cavium Octeon CN30XX ISA 64 */
#define MIPS_CN58XX 0x03 /* Cavium Octeon CN58XX ISA 64 */
#define MIPS_CN56XX 0x04 /* Cavium Octeon CN56XX ISA 64 */
#define MIPS_CN50XX 0x06 /* Cavium Octeon CN50XX ISA 64 */
#define MIPS_CN52XX 0x07 /* Cavium Octeon CN52XX ISA 64 */
#define MIPS_CN63XX 0x90 /* Cavium Octeon CN63XX ISA 64 */
#define MIPS_CN68XX 0x91 /* Cavium Octeon CN68XX ISA 64 */
#define MIPS_CN66XX 0x92 /* Cavium Octeon CN66XX ISA 64 */
#define MIPS_CN61XX 0x93 /* Cavium Octeon CN61XX ISA 64 */
#define MIPS_CNF71XX 0x94 /* Cavium Octeon CNF71XX ISA 64 */
#define MIPS_CN78XX 0x95 /* Cavium Octeon CN78XX ISA 64 */
#define MIPS_CN70XX 0x96 /* Cavium Octeon CN70XX ISA 64 */
#define MIPS_CN73XX 0x97 /* Cavium Octeon CN73XX ISA 64 */
#define MIPS_CNF75XX 0x98 /* Cavium Octeon CNF75XX ISA 64 */
/*
* CPU processor revision IDs for company ID == 7 (Microsoft)
*/
#define MIPS_eMIPS 0x04 /* MSR's eMIPS */
/*
* CPU processor revision IDs for company ID == e1 (Ingenic)
*/
#define MIPS_XBURST 0x02 /* Ingenic XBurst */
/*
* FPU processor revision ID
*/
#define MIPS_SOFT 0x00 /* Software emulation ISA I */
#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
#ifdef MIPS3_LOONGSON2
/*
* Loongson 2E/2F specific defines
*/
/*
* Address Window registers physical addresses
*
* The Loongson 2F processor has an AXI crossbar with four possible bus
* masters, each one having four programmable address windows.
*
* Each window is defined with three 64-bit registers:
* - a base address register, defining the address in the master address
* space (base register).
* - an address mask register, defining which address bits are valid in this
* window. A given address matches a window if (addr & mask) == base.
* - the location of the window base in the target, as well at the target
* number itself (mmap register). The lower 20 bits of the address are
* forced as zeroes regardless of their value in this register.
* The translated address is thus (addr & ~mask) | (mmap & ~0xfffff).
*/
