/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Device driver for Alchemy Semiconductor Au1x00 Ethernet Media
* Access Controller.
*
* TODO:
*
* Better Rx buffer management; we want to get new Rx buffers
* to the chip more quickly than we currently do.
*/
/*
* The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer
* must consist of a single DMA segment, and must be aligned to a 2K
* boundary. Therefore, this driver does not perform DMA directly
* to/from mbufs. Instead, we copy the data to/from buffers allocated
* at device attach time.
*
* We also skip the bus_dma dance. The MAC is built in to the CPU, so
* there's little point in not making assumptions based on the CPU type.
* We also program the Au1X00 cache to be DMA coherent, so the buffers
* are accessed via KSEG0 addresses.
*/
#define AUMAC_NTXDESC 4
#define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1)
struct aumac_buf {
vaddr_t buf_vaddr; /* virtual address of buffer */
bus_addr_t buf_paddr; /* DMA address of buffer */
};
/*
* Software state per device.
*/
struct aumac_softc {
device_t sc_dev; /* generic device information */
bus_space_tag_t sc_st; /* bus space tag */
bus_space_handle_t sc_mac_sh; /* MAC space handle */
bus_space_handle_t sc_macen_sh; /* MAC enable space handle */
bus_space_handle_t sc_dma_sh; /* DMA space handle */
struct ethercom sc_ethercom; /* Ethernet common data */
void *sc_sdhook; /* shutdown hook */
int sc_irq;
void *sc_ih; /* interrupt cookie */
struct mii_data sc_mii; /* MII/media information */
/* Get the MAC address. */
ea = prop_dictionary_get(device_properties(self), "mac-address");
if (ea == NULL) {
aprint_error_dev(self, "unable to get mac-addr property\n");
return;
}
KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
enaddr = prop_data_data_nocopy(ea);
/* Map the device. */
if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE],
MACx_SIZE, 0, &sc->sc_mac_sh) != 0) {
aprint_error_dev(self, "unable to map MAC registers\n");
return;
}
if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE],
MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) {
aprint_error_dev(self, "unable to map MACEN registers\n");
return;
}
if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE],
MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) {
aprint_error_dev(self, "unable to map MACDMA registers\n");
return;
}
/* Make sure the MAC is powered off. */
aumac_powerdown(sc);
/* Hook up the interrupt handler. */
sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL,
aumac_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self,
"unable to register interrupt handler\n");
return;
}
sc->sc_irq = aa->aa_irq[0];
au_intr_disable(sc->sc_irq);
/*
* Allocate space for the transmit and receive buffers.
*/
if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0,
&pglist, 1, 0))
return;
/* Make sure the interface is shutdown during reboot. */
sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc);
if (sc->sc_sdhook == NULL)
aprint_error_dev(self,
"WARNING: unable to establish shutdown hook\n");
return;
}
/*
* aumac_shutdown:
*
* Make sure the interface is stopped at reboot time.
*/
static void
aumac_shutdown(void *arg)
{
struct aumac_softc *sc = arg;
aumac_stop(&sc->sc_ethercom.ec_if, 1);
/*
* XXX aumac_stop leaves device powered up at the moment
* XXX but this still isn't enough to keep yamon happy... :-(
*/
bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0);
}
/*
* Loop through the send queue, setting up transmit descriptors
* unitl we drain the queue, or use up all available transmit
* descriptors.
*/
for (;;) {
/* Grab a packet off the queue. */
IFQ_POLL(&ifp->if_snd, m);
if (m == NULL)
return;
/* Get a spare descriptor. */
if (sc->sc_txfree == 0) {
/* No more slots left. */
AUMAC_EVCNT_INCR(&sc->sc_ev_txstall);
return;
}
nexttx = sc->sc_txnext;
IFQ_DEQUEUE(&ifp->if_snd, m);
/*
* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
*/
/* Zero out the remainder of any short packets. */
if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN))
memset((char *)sc->sc_txbufs[nexttx].buf_vaddr +
m->m_pkthdr.len, 0,
ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len);
/* Try to get more packets going. */
aumac_start(ifp);
}
/*
* aumac_ioctl: [ifnet interface function]
*
* Handle control requests from the operator.
*/
static int
aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data)
{
struct aumac_softc *sc = ifp->if_softc;
int s, error;
s = splnet();
error = ether_ioctl(ifp, cmd, data);
if (error == ENETRESET) {
/*
* Multicast list has changed; set the hardware filter
* accordingly.
*/
if (ifp->if_flags & IFF_RUNNING)
aumac_set_filter(sc);
error = 0;
}
/* Try to get more packets going. */
aumac_start(ifp);
splx(s);
return error;
}
/*
* aumac_intr:
*
* Interrupt service routine.
*/
static int
aumac_intr(void *arg)
{
struct aumac_softc *sc = arg;
int status;
/*
* There aren't really any interrupt status bits on the
* Au1X00 MAC, and each MAC has a dedicated interrupt
* in the CPU's built-in interrupt controller. Just
* check for new incoming packets, and then Tx completions
* (for status updating).
*/
if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0)
return 0;
status = aumac_rxintr(sc);
status += aumac_txintr(sc);
rnd_add_uint32(&sc->rnd_source, status);
return status;
}
/*
* aumac_txintr:
*
* Helper; handle transmit interrupts.
*/
static int
aumac_txintr(struct aumac_softc *sc)
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
uint32_t stat;
int i;
int pkts = 0;
for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC;
i = AUMAC_NEXTTX(i)) {
if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0)
break;
pkts++;
if (stat & TX_STAT_EC) {
if_statadd_ref(ifp, nsr, if_collisions, 16);
} else if (TX_STAT_CC(stat)) {
if_statadd_ref(ifp, nsr, if_collisions,
TX_STAT_CC(stat));
}
IF_STAT_PUTREF(ifp);
sc->sc_txfree++;
/* Try to queue more packets. */
if_schedule_deferred_start(ifp);
}
if (pkts)
AUMAC_EVCNT_INCR(&sc->sc_ev_txintr);
/* Update the dirty descriptor pointer. */
sc->sc_txdirty = i;
/*
* If there are no more pending transmissions, cancel the watchdog
* timer.
*/
if (sc->sc_txfree == AUMAC_NTXDESC)
ifp->if_timer = 0;
return pkts;
}
/*
* aumac_rxintr:
*
* Helper; handle receive interrupts.
*/
static int
aumac_rxintr(struct aumac_softc *sc)
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
struct mbuf *m;
uint32_t stat;
int i, len;
int pkts = 0;
for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) {
if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0)
break;
pkts++;
stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_RX_STAT(i));
#define PRINTERR(str) \
do { \
error++; \
printf("%s: %s\n", device_xname(sc->sc_dev), str); \
} while (0)
if (stat & RX_STAT_ERRS) {
int error = 0;
#if 0 /*
* Missed frames are a semi-frequent occurrence with this hardware,
* and reporting of them just makes everything run slower and fills
* the system log. Be silent.
*
* Additionally, this missed bit indicates an error with the previous
* packet, and not with this one! So PRINTERR is definitely wrong
* here.
*
* These should probably all be converted to evcnt counters anyway.
*/
if (stat & RX_STAT_MI)
PRINTERR("missed frame");
#endif
if (stat & RX_STAT_UC)
PRINTERR("unknown control frame");
if (stat & RX_STAT_LE)
PRINTERR("short frame");
if (stat & RX_STAT_CR)
PRINTERR("CRC error");
if (stat & RX_STAT_ME)
PRINTERR("medium error");
if (stat & RX_STAT_CS)
PRINTERR("late collision");
if (stat & RX_STAT_FL)
PRINTERR("frame too big");
if (stat & RX_STAT_RF)
PRINTERR("runt frame (collision)");
if (stat & RX_STAT_WT)
PRINTERR("watch dog");
if (stat & RX_STAT_DB) {
if (stat & (RX_STAT_CS | RX_STAT_RF |
RX_STAT_CR)) {
if (!error)
goto pktok;
} else
PRINTERR("dribbling bit");
}
#undef PRINTERR
if_statinc(ifp, if_ierrors);
dropit:
/* reuse the current descriptor */
AUMAC_INIT_RXDESC(sc, i);
continue;
}
pktok:
len = RX_STAT_L(stat);
/*
* The Au1X00 MAC includes the CRC with every packet;
* trim it off here.
*/
len -= ETHER_CRC_LEN;
/*
* Truncate the packet if it's too big to fit in
* a single mbuf cluster.
*/
if (len > MCLBYTES - 2)
len = MCLBYTES - 2;
MGETHDR(m, M_DONTWAIT, MT_DATA);
if (m == NULL) {
printf("%s: unable to allocate Rx mbuf\n",
device_xname(sc->sc_dev));
goto dropit;
}
if (len > MHLEN - 2) {
MCLGET(m, M_DONTWAIT);
if ((m->m_flags & M_EXT) == 0) {
printf("%s: unable to allocate Rx cluster\n",
device_xname(sc->sc_dev));
m_freem(m);
goto dropit;
}
}
/* Pass it on. */
if_percpuq_enqueue(ifp->if_percpuq, m);
}
if (pkts)
AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr);
if (pkts == AUMAC_NRXDESC)
AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall);
/* Update the receive pointer. */
sc->sc_rxptr = i;
return pkts;
}
/*
* aumac_tick:
*
* One second timer, used to tick the MII.
*/
static void
aumac_tick(void *arg)
{
struct aumac_softc *sc = arg;
int s;
/*
* aumac_init: [ifnet interface function]
*
* Initialize the interface. Must be called at splnet().
*/
static int
aumac_init(struct ifnet *ifp)
{
struct aumac_softc *sc = ifp->if_softc;
int i, error = 0;
/* Cancel any pending I/O, reset MAC. */
aumac_stop(ifp, 0);
/* Set up the transmit ring. */
for (i = 0; i < AUMAC_NTXDESC; i++) {
bus_space_write_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_TX_STAT(i), 0);
bus_space_write_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_TX_LEN(i), 0);
bus_space_write_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr);
}
sc->sc_txfree = AUMAC_NTXDESC;
sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_TX_ADDR(0)));
sc->sc_txdirty = sc->sc_txnext;
/* Set up the receive ring. */
for (i = 0; i < AUMAC_NRXDESC; i++)
AUMAC_INIT_RXDESC(sc, i);
sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh,
MACDMA_RX_ADDR(0)));
/* Set the station address. */
bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH,
enaddr[4] | (enaddr[5] << 8));
bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW,
enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
(enaddr[3] << 24));
sc->sc_control |= CONTROL_HP;
mchash[0] = mchash[1] = 0;
/*
* Set up the multicast address filter by passing all multicast
* addresses through a CRC generator, and then using the high
* order 6 bits as an index into the 64-bit multicast hash table.
* The high order bits select the word, while the rest of the bits
* select the bit within the word.
*/
ETHER_LOCK(ec);
ETHER_FIRST_MULTI(step, ec, enm);
while (enm != NULL) {
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
/*
* We must listen to a range of multicast addresses.
* For now, just accept all multicasts, rather than
* trying to set only those filter bits needed to match
* the range. (At this time, the only use of address
* ranges is for IP multicast routing, for which the
* range is large enough to require all bits set.)
*/
ETHER_UNLOCK(ec);
goto allmulti;
}
/*
* aumac_mii_wait:
*
* Wait for the MII interface to not be busy.
*/
static int
aumac_mii_wait(struct aumac_softc *sc, const char *msg)
{
int i;
for (i = 0; i < 10000; i++) {
if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh,
MAC_MIICTRL) & MIICTRL_MB) == 0)
return 0;
delay(10);
}
printf("%s: MII failed to %s\n", device_xname(sc->sc_dev), msg);
return ETIMEDOUT;
}
/*
* aumac_mii_readreg: [mii interface function]
*
* Read a PHY register on the MII.
*/
static int
aumac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
{
struct aumac_softc *sc = device_private(self);
int rv;
if ((rv = aumac_mii_wait(sc, "become ready")) != 0)
return rv;
/*
* aumac_mii_writereg: [mii interface function]
*
* Write a PHY register on the MII.
*/
static int
aumac_mii_writereg(device_t self, int phy, int reg, uint16_t val)
{
struct aumac_softc *sc = device_private(self);
int rv;
if ((rv = aumac_mii_wait(sc, "become ready")) != 0)
return rv;
