/*-
* Copyright (c) 1999-2002
* Shin Takemura and PocketBSD Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the PocketBSD project
* and its contributors.
* 4. Neither the name of the project nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/*
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
const struct ipl_sr_map __ipl_sr_map_vr = {
.sr_bits = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_SOFT_INT_MASK
| MIPS_INT_MASK_0,
[IPL_SCHED] = MIPS_SOFT_INT_MASK
| MIPS_INT_MASK_0
| MIPS_INT_MASK_1,
[IPL_DDB] = MIPS_INT_MASK,
[IPL_HIGH] = MIPS_INT_MASK,
},
};
void
vr_find_dram(paddr_t addr, paddr_t end)
{
int n;
char *page;
#ifdef NARLY_MEMORY_PROBE
int x, i;
#endif
#ifdef VR_FIND_DRAMLIM
if (VR_FIND_DRAMLIM < end)
end = VR_FIND_DRAMLIM;
#endif /* VR_FIND_DRAMLIM */
n = mem_cluster_cnt;
for (; addr < end; addr += PAGE_SIZE) {
page = (char *)MIPS_PHYS_TO_KSEG1(addr);
/*
XXX see port-hpcmips/42934
if (badaddr(page, 4))
goto bad;
*/
/* stop memory probing at first memory image */
if (memcmp(page, (void *)MIPS_PHYS_TO_KSEG0(0), 128) == 0)
return;
*(volatile int *)(page+0) = 0xa5a5a5a5;
*(volatile int *)(page+4) = 0x5a5a5a5a;
wbflush();
if (*(volatile int *)(page+0) != 0xa5a5a5a5)
goto bad;
*(volatile int *)(page+0) = 0x5a5a5a5a;
*(volatile int *)(page+4) = 0xa5a5a5a5;
wbflush();
if (*(volatile int *)(page+0) != 0x5a5a5a5a)
goto bad;
#ifdef NARLY_MEMORY_PROBE
x = random();
for (i = 0; i < PAGE_SIZE; i += 4)
*(volatile int *)(page+i) = (x ^ i);
wbflush();
for (i = 0; i < PAGE_SIZE; i += 4)
if (*(volatile int *)(page+i) != (x ^ i))
goto bad;
x = random();
for (i = 0; i < PAGE_SIZE; i += 4)
*(volatile int *)(page+i) = (x ^ i);
wbflush();
for (i = 0; i < PAGE_SIZE; i += 4)
if (*(volatile int *)(page+i) != (x ^ i))
goto bad;
#endif /* NARLY_MEMORY_PROBE */
if (!mem_clusters[n].size)
mem_clusters[n].start = addr;
mem_clusters[n].size += PAGE_SIZE;
continue;
bad:
if (mem_clusters[n].size)
++n;
continue;
}
if (mem_clusters[n].size)
++n;
mem_cluster_cnt = n;
}
void
vr_fb_init(void **kernend)
{
/* Nothing to do */
}
while (ppl < (ipl = splintr(&ipending))) {
/* Deal with unneded compare interrupts occasionally so that
* we can keep spllowersoftclock. */
if (ipending & MIPS_INT_MASK_5) {
mips3_cp0_compare_write(0);
}
if (ipending & MIPS_INT_MASK_1) {
(*vr_intr_handler[1])(vr_intr_arg[1], pc, status);
}
int
vr_null_handler(void *arg, vaddr_t pc, uint32_t status)
{
printf("vr_null_handler\n");
return (0);
}
/*
int x4181 = VR4181;
int x4101 = VR4101;
int x4102 = VR4102;
int x4111 = VR4111;
int x4121 = VR4121;
int x4122 = VR4122;
int xo4181 = ONLY_VR4181;
int xo4101 = ONLY_VR4101;
int xo4102 = ONLY_VR4102;
int xo4111_4121 = ONLY_VR4111_4121;
int g4101=VRGROUP_4101;
int g4102=VRGROUP_4102;
int g4181=VRGROUP_4181;
int g4102_4121=VRGROUP_4102_4121;
int g4111_4121=VRGROUP_4111_4121;
int g4102_4122=VRGROUP_4102_4122;
int g4111_4122=VRGROUP_4111_4122;
int single_vrip_base=SINGLE_VRIP_BASE;
int vrip_base_addr=VRIP_BASE_ADDR;
*/