/*
* Copyright (c) 2003 Naoto Shimazaki.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NAOTO SHIMAZAKI AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE NAOTO OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* XXX
* this function is too much specific for the device.
*/
int
i28f128_probe(void *base)
{
static const u_int8_t vendor_code[] = {
0x89, /* manufacturer code: intel */
0x18, /* device code: 28F128 */
};
static int
block_write(void *dst, const void *src)
{
int status;
const u_int16_t *p;
u_int16_t *q;
const u_int16_t *fence;
int i;
const int wbuf_count = I28F128_WBUF_SIZE >> 1;
/* dst must be aligned to block boundary. */
if (I28F128_BLOCK_MASK & (u_int32_t) dst)
return -1;
if (memcmp(dst, src, I28F128_BLOCK_SIZE) == 0)
return 0;
if ((status = block_erase(dst)) != 0)
return status;
p = src;
q = dst;
fence = p + (I28F128_BLOCK_SIZE >> 1);
do {
do {
REGWRITE_2(dst, 0, I28F128_WRITE_BUFFER);
status = REGREAD_2(dst, 0);
} while (!ISSET(status, I28F128_XS_BUF_AVAIL));
REGWRITE_2(dst, 0, wbuf_count - 1);
for (i = wbuf_count; i > 0; i--, p++, q++)
REGWRITE_2(q, 0, *p);
REGWRITE_2(dst, 0, I28F128_WBUF_CONFIRM);
do {
REGWRITE_2(dst, 0, I28F128_READ_STATUS);
status = REGREAD_2(dst, 0);
} while (!(status & I28F128_S_READY));