/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by IWAMOTO Toshihiro.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Platform dependent part for SA-11[01]1 companion chip on hpcarm.
*/
for (i = 0, mask = 1; i < 32; i++, mask <<= 1)
if (intstat.lo & mask) {
/*
* Clear intr status before calling intr handlers.
* This cause stray interrupts, but clearing
* after calling intr handlers cause intr lossage.
*/
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
SACCIC_INTSTATCLR0, 1 << i);
for (ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next)
softint_schedule(ih->ih_soft);
}
for (i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1)
if (intstat.hi & mask) {
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
SACCIC_INTSTATCLR1, 1 << i);
for (ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next)
softint_schedule(ih->ih_soft);
}
return 1;
}