/*
* Copyright (c) 2005, Miodrag Vallat
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
/*-
* Copyright (c) 2020, 2025 Izumi Tsutsui. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* 425e and 362/382 EVRX specific hardware
*/
/*
* RAMDAC (Bt458) on 425e EVRX is found at offset 0x00060000 from SGC bus PA.
* RAMDAC (Bt474) on 362/382 EVRX is also found at offset 0x00060000
* from DIO scode (132) + STI_DIO_SCODE_OFFSET PA (i.e. 0x01800000).
*
* Offset 0x040000 length 0x1c0000 is mapped in MI sti via ROM region 2
* on both 425e and 362/382.
*/
#define STI_EVRX_REGNO2OFFSET 0x00020000 /* 0x00060000 - 0x00040000 */
/* bitmap memory can be accessed at offset +0x200000 */
#define STI_EVRX_FBOFFSET 0x00200000
/* These registers are partially common between Bt474 and Bt458 */
#define EVRX_BT4xx_ADDR EVRX_BT458_ADDR
#define EVRX_BT4xx_CMAP EVRX_BT458_CMAP
#define EVRX_BT4xx_CTRL EVRX_BT458_CTRL
/* Identify the board model by dd_grid */
rom_dd = &ssc->sc_rom->rom_dd;
grid0 = rom_dd->dd_grid[0];
scr = ssc->sc_scr;
switch (grid0) {
case STI_DD_EVRX:
case STI_DD_382C:
case STI_DD_3X2V:
/*
* 425e and 362/382 on-board EVRX framebuffer.
*/
sc->sc_bitmap = base + STI_EVRX_FBOFFSET;
/*
* initialize Bt458/474 RAMDAC and preserve initial color map
*/
sti_evrx_resetramdac(scr);
sti_evrx_resetcmap(scr);
scr->setupfb = sti_evrx_setupfb;
scr->putcmap = sti_evrx_putcmap;
break;
case STI_DD_CRX:
/*
* HP A1659A CRX on some 425t variants.
*/
sc->sc_bitmap = base + STI_CRX_FBOFFSET;
break;
default:
/*
* Unsupported variants.
* Use default common sti(4) attachment (no bitmap support).
*/
sti_end_attach(ssc);
return;
}
/*
* Initialize the Bt458. When we write to control registers,
* the address is not incremented automatically. So we specify
* it ourselves for each control register.
*/
/* all planes will be read */
bus_space_write_1(bst, bsh, EVRX_BT4xx_ADDR, 0x04);
bus_space_write_1(bst, bsh, EVRX_BT4xx_CTRL, 0xff);
#if 0
/*
* HP-UX woodInitializeHardware() doesn't touch these
* Bt458 specific registers. Maybe initialized by STI ROM?
*/
/* all planes have non-blink */
bus_space_write_1(bst, bsh, EVRX_BT458_ADDR, 0x05);
bus_space_write_1(bst, bsh, EVRX_BT458_CTRL, 0x00);